DATASHEET

ISL84684
®
Data Sheet
July 31, 2007
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Dual SPDT Analog Switch
The Intersil ISL84684 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+3.6V supply. Targeted applications include battery powered
equipment that benefits from low rON (0.35Ω) and fast
switching speeds (tON = 50ns, tOFF = 27ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84684 is offered in small form factor packages, alleviating
board space limitations.
The ISL84684 is a committed dual single-pole/double-throw
(SPDT) that consists of two normally open (NO) and two
normally (NC) switches. This configuration can be used as a
dual 2-to-1 multiplexer. The ISL84684 is pin compatible with
the MAX4684 and MAX4685.
TABLE 1. FEATURES AT A GLANCE
FN6088.5
Features
• Drop in Replacement for the MAX4684 and MAX4685
• ON-Resistance (rON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.35Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω
• rON Matching Between Channels . . . . . . . . . . . . . . . .0.055Ω
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . .0.03Ω
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.2μW
• Fast Switching Action (V+ = +3.0V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV
• Guaranteed Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Available in 10 Ld 3x3 TDFN and 10 Ld MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
ISL84684
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
Number of Switches
2
SW
SPDT or 2-1 MUX
3V rON
0.35Ω
3V tON/tOFF
50ns/27ns
1.8V rON
0.55Ω
1.8V tON/tOFF
70ns/54ns
Packages
10 Ld 3x3 Thin DFN, 10 Ld MSOP
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84684
Pinout
Ordering Information
(Note 1)
ISL84684
(10 LD TDFN, MSOP)
TOP VIEW
PART
NUMBER
10 NO2
V+ 1
9 COM2
NO1 2
PART
MARKING
TEMP.
RANGE
(°C)
ISL84684IIZ-T*
684Z
-40 to +85
10 Ball WLCSP W4x3.10A
ISL84684IR
684
-40 to +85
10 Ld 3x3 TDFN L10.3x3A
ISL84684IR-T*
684
-40 to +85
10 Ld 3x3 TDFN L10.3x3A
Tape and Reel
8 IN2
COM1 3
PACKAGE
PKG.
DWG.
#
IN1 4
7 NC2
ISL84684IU
4684
-40 to +85
10 Ld MSOP
M10.118
NC1 5
6 GND
ISL84684IU-T*
4684
-40 to +85
10 Ld MSOP
Tape and Reel
M10.118
ISL84684IRZ
(Note)
684Z
-40 to +85
10 Ld 3x3 TDFN L10.3x3A
(Pb-free)
ISL84684IRZ-T* 684Z
(Note)
-40 to +85
10 Ld 3x3 TDFN L10.3x3A
Tape and Reel
(Pb-free)
ISL84684IUZ
(Note)
4684Z
-40 to +85
10 Ld MSOP
(Pb-free)
M10.118
ISL84684IUZ-T* 4684Z
(Note)
-40 to +85
10 Ld MSOP
Tape and Reel
(Pb-free)
M10.118
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
PIN NC1 and NC2
PIN NO1 and NO2
0
ON
OFF
1
OFF
ON
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
PIN
V+
FUNCTION
System Power Supply Input (+1.65V to +3.6V)
GND
Ground Connection
IN
Digital Control Input
COM
*Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
2
FN6088.5
July 31, 2007
ISL84684
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4kV
Thermal Resistance (Typical)
θJA (°C/W)
10 Ld 3x3 TDFN Package (Note 3) . . . . . . . . . . . . .
110
10 Ld MSOP Package (Note 3) . . . . . . . . . . . . . . . .
190
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
Full
0
-
V+
V
25
-
0.35
0.5
Ω
Full
-
-
0.7
Ω
25
-
0.055
0.07
Ω
Full
-
-
0.08
Ω
25
-
0.03
0.15
Ω
Full
-
-
0.15
Ω
25
-4
-
4
nA
Full
-40
-
40
nA
25
-5
-
5
nA
Full
-60
-
60
nA
25
-
50
-
ns
Full
-
60
-
ns
25
-
27
-
ns
Full
-
35
-
ns
Full
-
9
-
ns
TYP
MAX
(Notes 5, 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON Resistance, rON
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON, (Note 8)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1)
Break-Before-Make Time Delay, tD V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 3)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
94
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
62
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-85
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
-
0.005
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
65
-
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
181
-
pF
3
FN6088.5
July 31, 2007
ISL84684
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Note 4),
Unless Otherwise Specified.
TEMP
(°C)
MIN
(Notes 5, 6)
TYP
Full
1.65
-
3.6
V
25
-
-
40
nA
Full
-
-
750
nA
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
μA
PARAMETER
TEST CONDITIONS
MAX
(Notes 5, 6) UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
TYP
MAX
(Notes 5, 6) UNITS
Full
0
-
V+
V
25
-
0.55
-
Ω
Full
-
0.6
-
Ω
25
-
70
-
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON-Resistance, rON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
(See Figure 1)
Full
-
80
-
ns
25
-
54
-
ns
Full
-
65
-
ns
Break-Before-Make Time Delay, tD
V+ = 2.0V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
(See Figure 3)
Full
-
10
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
42
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-95
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
70
-
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
186
-
pF
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1.0
-
-
V
Full
-0.5
-
0.5
μA
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (See Note 9)
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
9. Limits established by characterization and are not production tested.
4
FN6088.5
July 31, 2007
ISL84684
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
tr < 5ns
tf < 5ns
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
COM
IN
VOUT
90%
SWITCH
OUTPUT
VOUT
NO or NC
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------R L + r ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO or NC
ΔVOUT
VG
GND
IN
CL
V+
LOGIC
INPUT
ON
ON
LOGIC
INPUT
OFF
0V
Q = ΔVOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
VNX
NO
VOUT
COM
NC
0V
RL
50Ω
IN
SWITCH
OUTPUT
VOUT
C
90%
LOGIC
INPUT
CL
35pF
GND
0V
tD
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5
FN6088.5
July 31, 2007
ISL84684
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
rON = V1/100mA
NO or NC
NO or NC
IN
VNX
0V or V+
100mA
IN
V1
0V or V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
IN
0V or V+
0V or V+
IMPEDANCE
ANALYZER
NC or NO
COM
ANALYZER
COM
NC
GND
RL
Signal direction through switch is reversed; worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
V+
The ISL84684 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 3.6V supply with low
ON-resistance (0.35Ω) and high speed operation
(tON = 50ns, tOFF = 27ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (60nA max), and its tiny
TDFN and MSOP packages. The ultra low ON-resistance and
rON flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
OPTIONAL
PROTECTION
RESISTOR
C
100Ω
NO
COM
NC
IN
GND
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL84684 IC (see Figure 8).
6
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
FN6088.5
July 31, 2007
ISL84684
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation, the sub-microamp IDD current of
the IC produces an insignificant voltage drop across the
100Ω series resistor resulting in no impact to switch
operation or performance.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provide additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 9). The resistor
limits the input current below the threshold that produces
permanent damage and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins as shown in Figure 9 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current.
.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNX
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL84684 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84684 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer
to the “Electrical Specification” tables on page 2 and “Typical
Performance Curves” on page 9 for details.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 18). At 2.7V,
the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output minimum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
7
FN6088.5
July 31, 2007
ISL84684
High-Frequency Performance
In 50Ω systems, the ISL84684 has a -3dB bandwidth of
120MHz (see Figure 19). The frequency response is very
consistent over a wide V+ range and for varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 20 details the high off Isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 62dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and V+ or GND.
8
FN6088.5
July 31, 2007
ISL84684
trytyrtyryryeeyrteff
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.35
0.70
ICOM = 100mA
ICOM = 100mA
0.65
0.34
0.60
0.33
V+ = 1.65V
V+ = 2.7V
0.32
rON (Ω)
rON (Ω)
0.55
0.31
V+ = 1.8V
0.45
V+ = 3V
0.30
0.50
V+ = 2V
0.40
0.29
0.35
V+ = 3.3V
0.28
0
0.5
1.0
1.5
2.0
2.5
3.0
0.30
3.5
0
0.5
1.0
VCOM (V)
1.5
2.0
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.40
0.40
V+ = 3.3V
ICOM = 100mA
V+ = 2.7V
ICOM = 100mA
+85°C
0.35
0.30
0.35
rON (Ω)
rON (Ω)
+85°C
+25°C
+25°C
0.30
0.25
-40°C
-40°C
0.20
0.25
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.5
+85°C
0.55
1.5
VCOM (V)
2.0
2.5
3.0
150
-40°C
100
0.45
Q (pC)
rON (Ω)
1.0
200
V+ = 1.8V
ICOM = 100mA
+25°C
0.50
0.5
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
0.60
0
0.40
V+ = 4.3V
50
V+ = 1.8V
0
0.35
V+ = 3V
-50
0.30
0.25
-100
0
0.5
1.0
VCOM (V)
1.5
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
9
2.0
0
1
2
3
4
5
VCOM (V)
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
FN6088.5
July 31, 2007
ISL84684
200
250
150
200
100
tON (ns)
tOFF (ns)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
+85°C
+85°C
150
+25°C
+25°C
-40°C
50
0
1.0
100
-40°C
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
25
1.0
4.5
FIGURE 16. TURN-OFF TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
1.0
0.9
2.5
3.0
V+ (V)
3.5
4.0
4.5
VINH
0.7
V+ = 3V
0
GAIN
-20
0
PHASE
20
40
0.6
VINL
60
0.5
80
0.4
0.3
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
1M
100
600M
FIGURE 19. FREQUENCY RESPONSE
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
10
V+ = 3.0V
-20
20
-30
30
-40
40
-50
50
ISOLATION
-60
60
-70
70
80
-80
CROSSTALK
-90
90
-100
100
-110
1k
10k
100k
1M
10M
100M
Die Characteristics
OFF ISOLATION (dB)
-10
CROSSTALK (dB)
10M
100M
FREQUENCY (Hz)
PHASE (°)
VINH AND VINL (V)
2.0
FIGURE 17. TURN-ON TIME vs SUPPLY VOLTAGE
1.1
0.8
1.5
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
110
500M
FREQUENCY (Hz)
FIGURE 20. CROSSTALK AND OFF ISOLATION
10
FN6088.5
July 31, 2007
ISL84684
Wafer Level Chip Scale Package (WLCSP)
W4x3.10A
4X3 ARRAY 10 BALL WAFER LEVEL CHIP SCALE PACKAGE
E
SYMBOL
MILLIMETERS
NOTES
A
0.64 +0.05 -0.10
-
A1
0.29 ±0.02
-
PIN 1 ID
D
TOP VIEW
bb
A2
A
A1
b
A2
0.35 REF.
-
b
θ 0.37 ±0.03
-
bb
θ 0.30 REF.
-
D
1.50 ±0.05
-
D1
1.00 BASIC
-
E
2.00 ±0.05
-
E1
1.50 BASIC
-
e
0.50 BASIC
-
SD
0.00 BASIC
-
SE
0.25 BASIC
-
N
10
3
Rev. 1 10/05
SIDE VIEW
NOTES:
1. Dimensions are in Millimeters.
2. Dimensioning and tolerancing conform to ASME 14.5M-1994.
E1
3. Symbol “N” is the actual number of solder balls.
e
SE
C
B
SD
D1
A
1
2
3
4
b
BOTTOM VIEW
11
FN6088.5
July 31, 2007
ISL84684
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
E
A3
6
INDEX
AREA
TOP VIEW
B
//
A
C
SEATING
PLANE
0.08 C
b
0.20
0.25
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
A3
SIDE VIEW
D2
(DATUM B)
0.10 C
0.20 REF
7
8
N
10
2
Nd
5
3
Rev. 3 3/06
D2/2
NOTES:
6
INDEX
AREA
1
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
8
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
12
FN6088.5
July 31, 2007
ISL84684
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
0.20 (0.008)
1 2
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X θ
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
MIN
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
-A-
0.50 BSC
E
L1
e
D
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1
θ
α
-
10
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6088.5
July 31, 2007