81313LTxx

GS81313LT18/36GK-833/714/625
144Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
260-Pin BGA
Com & Ind Temp
HSTL I/O
Up to 833 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
Clocking and Addressing Schemes
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The GS81313LT18/36GK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
4Mb x 36 and 8Mb x 18 organizations available
833 MHz maximum operating frequency
833 MT/s peak transaction rate (in millions per second)
60 Gb/s peak data bandwidth (in x36 devices)
Common I/O DDR Data Bus
Non-multiplexed SDR Address Bus
One operation - Read or Write - per clock cycle
Burst of 2 Read and Write operations
3 cycle Read Latency
On-chip ECC with virtually zero SER
1.25V ~ 1.3V core voltage
1.2V ~ 1.3V HSTL I/O interface
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaDDR-IIIe™ Family Overview
SigmaDDR-IIIe ECCRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Parameter Synopsis
Speed Grade
Max Operating Frequency
Read Latency
VDD
-833
833 MHz
3 cycles
1.2V to 1.35V
-714
714 MHz
3 cycles
1.2V to 1.35V
-625
625 MHz
3 cycles
1.2V to 1.35V
Rev: 1.12 5/2016
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
8M x 18 Pinout (Top View)
5
6
7
8
1
2
3
4
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCH
(CFG)
MCL
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
NUIO
VSS
NUI
MCL
MCL
NC
(RSVD)
MCL
(SIOM)
PZT0
NUI
VSS
DQ0
VSS
C
DQ17
VDDQ
NUI
VDDQ
VSS
SA
VDD
SA
VSS
VDDQ
NUI
VDDQ
NUIO
D
VSS
NUIO
VSS
NUI
SA
VDDQ
NC
(288 Mb)
VDDQ
SA
NUI
VSS
DQ1
VSS
E
DQ16
VDDQ
NUI
VDD
VSS
SA
VSS
SA
VSS
VDD
NUI
VDDQ
NUIO
F
VSS
NUIO
VSS
NUI
SA
VDD
VDDQ
VDD
SA
NUI
VSS
DQ2
VSS
G
DQ15
NUIO
NUI
NUI
VSS
SA
MZT1
SA
VSS
NUI
NUI
DQ3
NUIO
H
DQ14
VDDQ
NUI
VDDQ
SA
VDDQ
R/W
VDDQ
SA
VDDQ
NUI
VDDQ
NUIO
J
VSS
NUIO
VSS
NUI
VSS
SA
VSS
SA
VSS
NUI
VSS
DQ4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
VSS
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
DQ13
VSS
NUI
VSS
SA
VSS
SA
VSS
NUI
VSS
NUIO
VSS
N
NUIO
VDDQ
NUI
VDDQ
PLL
VDDQ
LD
VDDQ
MCH
VDDQ
NUI
VDDQ
DQ5
P
NUIO
DQ12
NUI
NUI
VSS
SA
MZT0
SA
VSS
NUI
NUI
NUIO
DQ6
R
VSS
DQ11
VSS
NUI
MCH
VDD
VDDQ
VDD
RST
NUI
VSS
NUIO
VSS
T
NUIO
VDDQ
NUI
VDD
VSS
SA
VSS
SA
VSS
VDD
NUI
VDDQ
DQ7
U
VSS
DQ10
VSS
NUI
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
NUI
VSS
NUIO
VSS
V
NUIO
VDDQ
NUI
VDDQ
VSS
SA
(x18)
VDD
SA
(B2)
VSS
VDDQ
NUI
VDDQ
DQ8
W
VSS
DQ9
VSS
NUI
TCK
MCL
RCS
MCL
TMS
NUI
VSS
NUIO
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5B, 6B, 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.12 5/2016
2/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
4M x 36 Pinout (Top View)
5
6
7
8
1
2
3
4
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCL
(CFG)
MCL
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
DQ35
VSS
NUI
MCL
MCL
NC
(RSVD)
MCL
(SIOM)
PZT0
NUI
VSS
DQ0
VSS
C
DQ26
VDDQ
NUI
VDDQ
VSS
SA
VDD
SA
VSS
VDDQ
NUI
VDDQ
DQ9
D
VSS
DQ34
VSS
NUI
SA
VDDQ
NC
(288 Mb)
VDDQ
SA
NUI
VSS
DQ1
VSS
E
DQ25
VDDQ
NUI
VDD
VSS
SA
VSS
SA
VSS
VDD
NUI
VDDQ
DQ10
F
VSS
DQ33
VSS
NUI
SA
VDD
VDDQ
VDD
SA
NUI
VSS
DQ2
VSS
G
DQ24
DQ32
NUI
NUI
VSS
SA
MZT1
SA
VSS
NUI
NUI
DQ3
DQ11
H
DQ23
VDDQ
NUI
VDDQ
SA
VDDQ
R/W
VDDQ
SA
VDDQ
NUI
VDDQ
DQ12
J
VSS
DQ31
VSS
NUI
VSS
SA
VSS
SA
VSS
NUI
VSS
DQ4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
VSS
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
DQ22
VSS
NUI
VSS
SA
VSS
SA
VSS
NUI
VSS
DQ13
VSS
N
DQ30
VDDQ
NUI
VDDQ
PLL
VDDQ
LD
VDDQ
MCH
VDDQ
NUI
VDDQ
DQ5
P
DQ29
DQ21
NUI
NUI
VSS
SA
MZT0
SA
VSS
NUI
NUI
DQ14
DQ6
R
VSS
DQ20
VSS
NUI
MCH
VDD
VDDQ
VDD
RST
NUI
VSS
DQ15
VSS
T
DQ28
VDDQ
NUI
VDD
VSS
SA
VSS
SA
VSS
VDD
NUI
VDDQ
DQ7
U
VSS
DQ19
VSS
NUI
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
NUI
VSS
DQ16
VSS
V
DQ27
VDDQ
NUI
VDDQ
VSS
NUI
(x18)
VDD
SA
(B2)
VSS
VDDQ
NUI
VDDQ
DQ8
W
VSS
DQ18
VSS
NUI
TCK
MCL
RCS
MCL
TMS
NUI
VSS
DQ17
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5B, 6B, 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.12 5/2016
3/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Pin Description
Symbol
SA
Description
Type
Address — Read or Write Address is registered on CK.
Input
DQ[35:0]
Write/Read Data — Registered on KD and KD during Write operations; aligned with CQ and CQ
during Read operations.
DQ[17:0] - x18 and x36.
DQ[35:18] - x36 only.
QVLD[1:0]
Read Data Valid — Driven high one half cycle before valid Read Data.
I/O
Output
CK, CK
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Input
KD[1:0],
KD[1:0]
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch Write Data (DQ[17:0] in x36, DQ[8:0] in x18).
KD1, KD1: latch Write Data (DQ[35:18] in x36, DQ[17:9] in x18).
Input
CQ[1:0],
CQ[1:0]
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with DQ[17:0] in x36, and DQ[8:0] in x18.
CQ1, CQ1: align with DQ[35:18] in x36, and DQ[17:9] in x18.
Output
LD
Load Enable — Registered onCK.
LD = 0: Loads a new address and initiates a Read or Write operation.
LD = 1: Initiates a NOP operation.
Input
R/W
Read / Write Enable — Registered on CK.
R/W = 0: initiates a Write operation when LD = 0.
R/W = 1: initiates a Read operation when LD = 0.
Input
PLL
PLL Enable — Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Input
RST
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Input
ZQ
Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to
program driver impedance.
Input
ZT
ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to
program ODT impedance.
Input
RCS
Current Source Resistor Input — Preferably, should be connected to VSS through an external 2K resistor to provide an accurate current source for the PLL. Alternately, it may be left unconnected, in which case
a less accurate current source for the PLL is derived internally. The less accurate current source results in a
narrower operating range for a given speed grade device, vs. connecting the RCS resistor.
Input
ODT Mode Select — Set the ODT state globally for all input groups. Must be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
Input
MZT[1:0]
Rev: 1.12 5/2016
4/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Symbol
Description
Type
PZT[1:0]
ODT Configuration Select — Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Input
VDD
Core Power Supply
—
VDDQ
I/O Power Supply
—
VREF
Input Reference Voltage — Input buffer reference voltage.
—
VSS
Ground
—
TCK
JTAG Clock — Weakly pulled Low internally.
Input
TMS
JTAG Mode Select — Weakly pulled High internally.
Input
TDI
JTAG Data Input — Weakly pulled High internally.
Input
TDO
JTAG Data Output
MCH
Must Connect High — May be tied to VDDQ directly or via a 1k resistor.
Input
MCL
Must Connect Low — May be tied to VSS directly or via a 1k resistor.
Input
NC
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
NUI
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Input
NUIO
Not Used Input/Output — There is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied/driven Low. They should not be tied/driven High.
I/O
Rev: 1.12 5/2016
Output
5/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
—
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The PLL is disabled.
• The states of LD, and R/W control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• DQ are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 224K (229,376) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 160K cycles.
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.
Note: The PLL pin may be asserted High or de-asserted Low during this time. If asserted High, PLL synchronization begins
immediately after the current source for the PLL is calibrated. If de-asserted Low, PLL synchronization begins after the PLL pin is
asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert PLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.
After the PLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.12 5/2016
6/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
PLL Operation
A PLL is implemented in these devices to control all output timing. It uses the CK input clock as a source, and is enabled when all
of the following conditions are met:
1. RST is de-asserted Low, and
2. The PLL pin is asserted High, and
3. CK cycle time  tKHKH (max), as specified in the AC Timing Specifications section.
Once enabled, the PLL requires 64K stable clock cycles in order to lock/synchronize properly.
When the PLL is enabled, it aligns output clocks and read data to input clocks (with some fixed delay), and it generates all
mid-cycle output timing. See the Output Timing section for more information.
The PLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the PLL to lose lock/
synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see “tKJITcc” in the AC Timing Specifications section
for more information). However, the PLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input
clock frequency is changed.
The PLL is disabled when any of the following conditions are met:
1. RST is asserted High, or
2. The PLL pin is de-asserted Low, or
3. CK is stopped for at least 30ns, or CK cycle time  30ns.
On-Chip Error Correction
These devices implement a single-error correct, single-error detect (SEC-SED) ECC algorithm (specifically, a Hamming Code) on
each 18-bit data word transmitted in DDR fashion on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18],
and D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the
user). As such, these devices actually comprise 184Mb of memory, of which 144Mb are visible to the user.
The ECC algorithm cannot detect multi-bit errors. However, these devices are architected in such a way that a single SER event
very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents the data
transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors results in
the SER mentioned previously (i.e., <0.002 FITs/Mb, measured at sea level).
Not only does the on-chip ECC significantly improve SER performance, but it can also free up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit
“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction).
Depending on the application, such error-bit allocation may be unnecessary in these devices, in which case the entire memory array
can be utilized for data storage, effectively providing 12.5% greater storage capacity compared to SRAMs of the same density not
equipped with on-chip ECC.
Rev: 1.12 5/2016
7/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Clock Truth Table
SA
LD
R/W
Current Operation
DQ (D)
DQ (Q)
CK
(tn)
CK
(tn)
CK
(tn)
(tn)
KD
(tn)
KD
(tn+½)
V
1
X
NOP
X
X
Hi-Z / other
V
0
0
Write
D1
D2
Hi-Z / other
V
0
1
Read
X
X
CQ
(tn+3)
Q1
CQ
(tn+3½)
Q2
Notes:
1. 1 = High 0 = Low; V = Valid; X = don’t care.
2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
4. When DQ ODT is disabled, DQ pins are tri-stated for one cycle in response to NOP and Write commands, 3 cycles after the command is
sampled. See the DQ ODT Control section below for how the state of the DQ pins is controlled when DQ ODT is enabled.
Rev: 1.12 5/2016
8/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
DQ ODT Control
A robust methodology has been developed for these devices for controlling when DQ ODT is enabled and disabled during
Write-to-Read and Read-to-Write transitions. Specifically, the methodology can ensure that the DQ bus is never pulled to VDDQ/2
by the SRAM ODT and/or by the controller ODT during the transitions (or at any other time). Such a condition is best avoided,
because if an input signal is pulled to VDDQ/2 (i.e. to VREF - the switch point of the diff-amp receiver), it could cause the receiver
to enter a meta-stable state and consume more power than it normally would otherwise. This could result in the device’s operating
currents being higher than specified.
The fundamental concept of the methodology is - both the SRAM and the controller drive the DQ bus Low (with DQ ODT
disabled) at all times except:
1. When a particular device is driving the DQ bus with valid data, and
2. From shortly before to shortly after a particular device is receiving valid data on the DQ bus, during which time the receiving
device enables its DQ ODT.
And, during Write-to-Read and Read-to-Write transitions, each device enables and disables its DQ ODT while the other device is
driving DQ Low, thereby ensuring that the DQ bus is never pulled to VDDQ/2.
Note: This methodology also reduces power consumption, since there will be no DC current through either device’s DQs when
both devices are driving Low.
In order for this methodology to work as described, the controller must have the ability to:
1. Place the SRAM into “DQ Drive Low Mode” at the appropriate times (i.e. before and after the SRAM drives read data), and
2. Place the SRAM into “DQ ODT Mode” at the appropriate times (i.e. before, during, and after the SRAM receives write data).
That ability is provided via the existing R/W control pin.
When the SRAM samples R/W High (regardless of the state of LD), it disables its DQ ODT, and drives the DQ bus Low except
while driving valid read data in response to Read operations.
When the SRAM samples R/W Low (regardless of the state of LD), it disables its DQ drivers, and enables its DQ ODT.
Note that NOPs initiated with R/W High and LD High are referred to as “NOPr” operations.
Note that NOPs initiated with R/W Low and LD High are referred to as “NOPw” operations.
This extended definition of the R/W control pin allows the controller to:
• Place the SRAM in DQ ODT Mode, via NOPw operations, before initiating Write operations.
• Keep the SRAM in DQ ODT Mode, via NOPw operations, after initiating Write operations.
• Place the SRAM in DQ Drive Low Mode, via NOPr operations, before initiating Read operations.
• Keep the SRAM in DQ Drive Low Mode, via NOPr operations, after initiating Read operations.
Operation Sequence Rule
Because of how R/W is used to control the state of the DQs, when a Read operation is initiated in cycle “n”, R/W must be driven
“high” in cycle “n+1” (i.e. a Read operation must always be followed by a Read or NOPr operation) in order to ensure that the DQ
state in cycle “n+3” is “Read Data”.
Rev: 1.12 5/2016
9/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
DQ Clock Truth Table
In the Truth Table below, gray shading indicates invalid operation sequences; they violate the Operation Sequence Rule.
LD
R/W
CK
(tn)
CK
(tn)
1
1
0
Prior
Operation
Current
Operation
Future
Operation
(tn-1)
(tn)
(tn+1)
Read
NOPw
NOPw, NOPr, or Write
NOPw
Read
NOPr
NOPw, NOPr, or Write
NOPr
Read
Write
NOPw, NOPr, or Write
Write
0
1
0
Read
0
1
NOPw, NOPr, or Write
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Write or NOPw
Read or NOPr
Read
Write or NOPw
Read
Read or NOPr
Read
Write or NOPw
Read
Read or NOPr
DQ State
CK
(tn+2)
Undefined
Terminated
Read Data
0
Undefined
Terminated
Read Data
0
CK
(tn+3)
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Terminated
0
Undefined
Read Data
Undefined
Read Data
Note: 1 = High; 0 = Low; X = don’t care.
Rev: 1.12 5/2016
10/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
NOPr and NOPw Requirements
The number of NOPw and NOPr needed during Write -> Read transitions, and the number of NOPr and NOPw needed during Read
-> Write transitions, are as follows:
Write -> Read Transition
NOPw (after Write)
Read -> Write Transition
NOPr (before Read)
NOPr (after Read)
NOPw (before Write)
min
typ
min
typ
min
typ
min
typ
0
0
0
1~2
2
3~4
3
4~5
Notes:
1. Min NOPw after Write (0) ensures that the SRAM disables DQ ODT 2.5 cycles after it latches the last piece of write data. Typ
NOPw is the same as Min NOPw because it is sufficient to ensure that the controller stops driving the last piece of write data
before SRAM DQ ODT disable reaches it (as the result of a subsequent NOPr or Read), regardless of SRAM tKQ, prop delay
between SRAM and controller, and operating frequency.
2. Min NOPr before Read (0) ensures that the SRAM drives Low 1 cycle before it begins driving the first piece of read data. Typ
NOPr is greater than Min NOPr in order to ensure that the controller enables DQ ODT after SRAM Low drive reaches it (and
before the SRAM drives the first piece of read data), accounting for SRAM tKQ, prop delay between SRAM and controller, and
operating frequency.
3. Min NOPr after Read (2) ensures that the SRAM drives Low for 1 cycle after it stops driving the last piece of read data and before
it enables DQ ODT (as the result of a subsequent NOPw). Typ NOPr is greater than Min NOPr in order to ensure that the controller
disables DQ ODT after SRAM Low drive reaches is (and before the SRAM enables DQ ODT), accounting for SRAM tKQ, prop
delay between SRAM and controller, and operating frequency.
4. Min NOPw before Write (3) ensures that the SRAM enables DQ ODT 1 cycle before it latches the first piece of write data. Typ
NOPw is greater than Min NOPw in order to ensure that the controller begins driving the first piece of write data after SRAM
DQ ODT enable reaches it, accounting for SRAM tKQ, prop delay between SRAM and controller, and operating frequency.
DQ ODT Control Timing Diagram
Write1
NOPr1
Read1
NOPr2
NOPr3
NOPr4
NOPw1
NOPw2
NOPw3
NOPw4
Write2
CK, KD
SA
A1
A2
A3
LD
R/W
tKHQV
tKHDQT
DQ D11 D12
tKHDQT
Q21 Q22
D31
CQ
Note: In the diagram above, the controller is disabling its DQ ODT except from the beginning of NOPr4 to the beginning of NOPw3.
And while it is disabling its DQ ODT, the controller is driving DQ Low when it isn’t driving write data. Whereas, the SRAM is
enabling its DQ ODT except from the beginning of NOPr2 to the beginning of NOPw3. And while it is disabling its DQ ODT, the
SRAM is driving DQ Low when it isn’t driving read data.
Rev: 1.12 5/2016
11/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Input Timing
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various
synchronous inputs. Specifically:
CK latches all address (SA) inputs.
CK latches all control (LD, R/W) inputs.
KD[1:0] and KD[1:0] latch particular write data (DQ) inputs, as follows:
• KD0 and KD0 latch DQ[17:0] in x36, and DQ[8:0] in x18.
• KD1 and KD1 latch DQ[35:18] in x36, and DQ[17:9] in x18.
Output Timing
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is
tightly aligned with read data in order to enable reliable source-synchronous data transmission.
These devices utilize a PLL to control output timing. When the PLL is enabled, it generates 0 and 180 phase clocks from CK
that control read data output clock (CQ, CQ), read data (DQ), and read data valid (QVLD) output timing, as follows:
• CK+0 generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.
• .CK+180 generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.
When the PLL is enabled, CQ is aligned to an internally-delayed version of CK. See the AC Timing Specifications for more
information.
CQ[1:0] and CQ[1:0] align with particular DQ and QVLD outputs, as follows:
• CQ0 and CQ0 align with DQ[17:0], QVLD0 in x36 devices, and DQ[8:0], QVLD0 in x18 devices.
• CQ1 and CQ1 align with DQ[35:18], QVLD1 in x36 devices, and DQ[17:9], QVLD0 in x18 devices.
Rev: 1.12 5/2016
12/29
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© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Driver Impedance Control
Programmable Driver Impedance is implemented on the following output signals:
• CQ, CQ, DQ, QVLD.
Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and VSS.
Driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.
Output Signal
Pull-Down Impedance (ROUTL)
Pull-Up Impedance (ROUTH)
CQ, CQ, DQ, QVLD
RQ*0.2  15%
RQ*0.2  15%
Notes:
1. ROUTL and ROUTH apply when 175 RQ  225.
2. The mismatch between ROUTL and ROUTH is less than 10%, guaranteed by design.
ODT Impedance Control
Programmable ODT Impedance is implemented on the following input signals:
• CK, CK, KD, KD, SA, LD, R/W, DQ.
ODT impedance is programmed by connecting an external resistor RT between the ZT pin and VSS.
ODT impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system
Input Signal
CK, CK, KD, KD
PZT[1:0]
MZT[1:0]
Pull-Down Impedance (RINL)
Pull-Up Impedance (RINH)
X0
XX
disabled
disabled
01
RT  15%
RT  15%
10
RT*2  20%
RT*2  20%
XX
disabled
disabled
01
RT  15%
RT  15%
10
RT*2  20%
RT*2  20%
01
RT  15%
RT  15%
10
RT*2  20%
RT*2  20%
X1
0X
SA, LD, R/W
DQ
1X
XX
Notes:
1. When MZT[1:0] = 00, ODT is disabled on all inputs. MZT[1:0] = 11 is reserved for future use.
2. RINL and RINH apply when 105 RT  135
3. The mismatch between RINL and RINH is less than 10%, guaranteed by design.
4. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to VDDQ / 2 (i.e., to the switch point of the
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.
This could result in the device’s operating currents being higher.
Rev: 1.12 5/2016
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© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Core Supply Voltage
VDD
-0.3 to +1.4
V
I/O Supply Voltage
VDDQ
-0.3 to VDD
V
VIN1
-0.3 to VDDQ + 0.3
VIN2
VDDQ - 1.5 to +1.7
Input Voltage (LS)
VIN3
Junction Temperature
Storage Temperature
Input Voltage (HS)
Notes
V
2
-0.3 to VDDQ + 0.3
V
3
TJ
0 to 125
C
TSTG
-55 to 125
C
Notes:
1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time
may affect reliability of this component.
2. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, DQ, LD, R/W. VIN1 and VIN2 must both be met.
3. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Core Supply Voltage
VDD
1.2
1.25
1.35
V
I/O Supply Voltage
VDDQ
1.15
1.2
VDD
V
Commercial Junction Temperature
TJC
0
—
85
C
Industrial Junction Temperature
TJI
-40
—
100
C
Notes
Note: For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF, and Inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
Thermal Impedances
Package
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
FBGA
13.67
10.28
9.31
3.08
0.13
Rev: 1.12 5/2016
14/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
I/O Capacitance
Parameter
Symbol
Min
Max
Units
Notes
Input Capacitance
CIN
—
5.0
pF
1, 3
Output Capacitance
COUT
—
5.5
pF
2, 3
Notes:
1. VIN = VDDQ/2.
2. VOUT = VDDQ/2.
3. TA = 25C, f = 1 MHz.
Input Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Notes
DC Input Reference Voltage
VREFdc
0.48 * VDDQ
0.50 * VDDQ
0.52 * VDDQ
V
—
DC Input High Voltage (HS)
VIH1dc
VREF + 0.08
0.80 * VDDQ
VDDQ + 0.15
V
1, 6
DC Input Low Voltage (HS)
VIL1dc
-0.15
0.20 * VDDQ
VREF - 0.08
V
2, 6
DC Input High Voltage (LS)
VIH2dc
0.75 * VDDQ
VDDQ
VDDQ + 0.15
V
7
DC Input Low Voltage (LS)
VIL2dc
-0.15
0
0.25 * VDDQ
V
7
AC Input Reference Voltage
VREFac
0.47 * VDDQ
0.50 * VDDQ
0.53 * VDDQ
V
3
AC Input High Voltage (HS)
VIH1ac
VREF + 0.15
0.80 * VDDQ
VDDQ + 0.25
V
1, 4~6
AC Input Low Voltage (HS)
VIL1ac
-0.25
0.20 * VDDQ
VREF - 0.15
V
2, 4~6
AC Input High Voltage (LS)
VIH2ac
VDDQ - 0.2
VDDQ
VDDQ + 0.25
V
4, 7
AC Input Low Voltage (LS)
VIL2ac
-0.25
0
0.2
V
4, 7
Notes:
1. “Typ” parameter applies when Controller ROUTH = 40 and SRAM RINH = RINL = 120.
2. “Typ” parameter applies when Controller ROUTL = 40 and SRAM RINH = RINL = 120.
3. VREFac is equal to VREFdc plus noise.
4. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, DQ, LD, R/W.
7. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.
Rev: 1.12 5/2016
15/29
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© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Output Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Notes
DC Output High Voltage
VOHdc
—
0.80 * VDDQ
VDDQ + 0.15
V
1, 3
DC Output Low Voltage
VOLdc
-0.15
0.20 * VDDQ
—
V
2, 3
AC Output High Voltage
VOHac
—
0.80 * VDDQ
VDDQ + 0.25
V
1, 3
AC Output Low Voltage
VOLac
-0.25
0.20 * VDDQ
—
V
2, 3
Note:
1. “Typ” parameter applies when SRAM ROUTH = 40 and Controller RINH = RINL = 120.
2. “Typ” parameter applies when SRAM ROUTL = 40 and Controller RINH = RINL = 120.
3. Parameters apply to: CQ, CQ, DQ, QVLD.
Leakage Currents
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Min
Max
Units
Notes
ILI1
-2
2
uA
1, 2
ILI2
-20
2
uA
1, 3
ILI3
-2
20
uA
1, 4
ILO
-2
2
uA
5, 6
Notes:
1. VIN = VSS to VDDQ.
2. Parameters apply to CK, CK, KD, KD, SA, DQ, LD, R/W when ODT is disabled.
Parameters apply to MZT, PZT.
3. Parameters apply to PLL, TMS, TDI (weakly pulled up).
4. Parameters apply to RST, TCK (weakly pulled down).
5. VOUT = VSS to VDDQ.
6. Parameters apply to CQ, CQ, DQ, QVLD, TDO.
Rev: 1.12 5/2016
16/29
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© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Operating Currents
Parameter
Symbol
VDD (nom)
625 MHz
714 MHz
833 MHz
Units
x18 Operating Current
IDD
1.25V
1200
1300
1400
mA
x36 Operating Current
IDD
1.25V
1500
1650
1800
mA
Notes:
1. IOUT = 0 mA; VIN = VIH or VIL.
2. Applies at 50% Reads + 50% Writes.
AC Test Conditions
Parameter
Symbol
Conditions
Units
Core Supply Voltage
VDD
1.2 to 1.35
V
I/O Supply Voltage
VDDQ
1.15 to 1.25
V
Input Reference Voltage
VREF
0.6
V
Input High Level
VIH
0.9
V
Input Low Level
VIL
0.3
V
Input Rise and Fall Time
—
2.0
V/ns
Input and Output Reference Level
—
0.6
V
Note: Output Load Conditions RQ = 200. Refer to figure below.
AC Test Output Load
50
Output
50
VDDQ/2
5 pF
Rev: 1.12 5/2016
17/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
AC Timing Specifications (independent of device speed grade)
Parameter
Symbol
Min
Max
Units Notes
Input Clock Timing
Clk High Pulse Width
tKHKL
0.45
—
cycles
1
Clk Low Pulse Width
tKLKH
0.45
—
cycles
1
Clk High to Clk High
tKHKH
0.45
0.55
cycles
2
Clk High to Write Data Clk High
tKHKDH
-250
+250
ps
3
Clk Cycle-to-Cycle Jitter
tKJITcc
—
60
ps
1,4,5
PLL Lock Time
tKlock
65,536
—
cycles
6
Clk Static to PLL Reset
tKreset
30
—
ns
7,12
Output Timing
Clk High to Output Valid / Hold
tKHQV/X
+0.4
+1.2
ns
8
Clk High to Output State Transition
tKHDQT
+0.4
+1.2
ns
8
Clk High to Echo Clock High
tKHCQH
+0.4
+1.2
ns
9
Echo Clk High to Output Valid / Hold
tCQHQV/X
-120
+120
ps
10,12
Echo Clk High to Echo Clock High
tCQHCQH
0.5*tKHKH (nom) - 50
0.5*tKHKH (nom) + 50
ps
11,12
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter specifiesCK CK and KD KD requirements.
3. Parameter specifies CK KD and CK KD requirements.
4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge). 
As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to  30ps. 
And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to  15ps.
5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed
grade, tKHKH (min) of that speed grade must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For
example, if the actual C2C Jitter is 100ps, then tKHKH (min) for the -714 speed grade is derated to 1.42ns (1.4ns + 0.5*(100ps - 60ps)).
6. VDD slew rate must be < 0.1V DC per 50ns for PLL lock retention. PLL lock time begins once VDD and input clock are stable.
7. Parameter applies to CK.
8. Parameters apply to DQ, and are referenced to CK.
9. Parameter specifies CK CQ timing.
10. Parameters apply to DQ, QVLD and are referenced to CQ & CQ.
11. Parameter specifies CQ CQ timing. tKHKH (nom) is the nominal input clock cycle time applied to the device.
12. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.12 5/2016
18/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
AC Timing Specifications (variable with device speed grade)
Parameter
Symbol
–833
Min
–714
Max
Min
–625
Units Notes
Max
Min
Max
6.0
1.6
6.0
ns
1
Input Clock Timing
Clk Cycle Time
tKHKH
1.2
6.0
1.4
Input Setup, Hold, and Pulse Width Timing
Input Valid to Clk High
tIVKH
150
—
150
—
160
—
ps
2
Clk High to Input Hold
tKHIX
150
—
150
—
160
—
ps
2
Input Pulse Width
tIPW
200
—
200
—
200
—
ps
2,3
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameters apply to SA, and are referenced to CK.
Parameters apply to LD, R/W, and are referenced to CK.
Parameters apply to DQ, and are referenced to KD & KD.
3. Parameter specifies input pulse width requirements for each individual address, control, and data input. Per-pin deskew must be performed, to center the valid window of each individual input around the clock edge that latches it, in order for these parameters to be relevant to the application. The parameter is not tested; it is guaranteed by design and verified through extensive corner-lot characterization.
Rev: 1.12 5/2016
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© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Read and Write Timing Diagram
Write
Write
NOPr
Read
Read
NOPr
NOPr
NOPr
NOPw
NOPw
NOPw
KD
tKHKH
tKHKL tKLKH tKHKH
tKHKH
tKHKL tKLKH tKHKH
KD
tKHKDH
tKHKDH
CK
CK
tIVKH tKHIX
SA A1
A2
A3
A4
tIVKH tKHIX
LD
R/W
tKHIX
(to KD) tIVKH
DQ
D11
tKHIX (to KD)
tIVKH
D12
D21
tKHQX
tKHQV
D22
Q31
Q32
Q41
Q42
QVLD
tCQHQX
tKHCQH
tCQHQV
tCQHQX
tCQHQV
CQ
tCQHCQH
CQ
Rev: 1.12 5/2016
20/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
JTAG Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,
etc.), ECCRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices
contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data
Registers.
The TAP consists of the following four signals:
Pin
Pin Name
I/O
Description
TCK
Test Clock
I
Induces (clocks) TAP Controller state transitions.
TMS
Test Mode Select
I
Inputs commands to the TAP Controller.
Sampled on the rising edge of TCK.
TDI
Test Data In
I
Inputs data serially to the TAP Registers.
Sampled on the rising edge of TCK.
TDO
Test Data Out
O
Outputs data serially from the TAP Registers.
Driven from the falling edge of TCK.
Concurrent TAP and Normal ECCRAM Operation
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only
exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.
Disabling the TAP
When JTAG is not used, TCK should be tied Low to prevent clocking the ECCRAM. TMS and TDI should either be tied High
through a pull-up resistor or left unconnected. TDO should be left unconnected.
JTAG DC Operating Conditions
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VTIH
0.75 * VDDQ
VDDQ + 0.15
V
1
JTAG Input Low Voltage
VTIL
–0.15
0.25 * VDDQ
V
1
JTAG Output High Voltage
VTOH
VDDQ – 0.2
—
V
2, 3
JTAG Output Low Voltage
VTOL
—
0.2
V
2, 4
Notes:
1. Parameters apply to TCK, TMS, and TDI.
2. Parameters apply to TDO.
3. ITOH = –2.0 mA.
4. ITOL = 2.0 mA.
Rev: 1.12 5/2016
21/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
JTAG AC Timing Specifications
Parameter
Symbol
Min
Max
Units
TCK Cycle Time
tTHTH
50
—
ns
TCK High Pulse Width
tTHTL
20
—
ns
TCK Low Pulse Width
tTLTH
20
—
ns
TMS Setup Time
tMVTH
10
—
ns
TMS Hold Time
tTHMX
10
—
ns
TDI Setup Time
tDVTH
10
—
ns
TDI Hold Time
tTHDX
10
—
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
10
—
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
10
—
ns
TCK Low to TDO Valid
tTLQV
—
10
ns
TCK Low to TDO Hold
tTLQX
0
—
ns
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
Rev: 1.12 5/2016
22/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the Test-Logic Reset state in one of two ways:
1. At power up.
2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
TAP Controller State Diagram
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
Update-DR
Rev: 1.12 5/2016
0
23/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
1
1
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction
(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
EXTEST
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with output signals (DQ, QVLD,
CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan Register
contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.
Also disables all ODT.
See the Boundary Scan Register description for more information.
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the
TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the
TAP Controller is in the Shift-DR state.
See the ID Register description for more information.
010
SAMPLE-Z
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also disables all ODT.
Also forces DQ output drivers to a High-Z state.
See the Boundary Scan Register description for more information.
011
PRIVATE
Reserved for manufacturer use only.
100
SAMPLE
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Reserved for manufacturer use only.
110
PRIVATE
Reserved for manufacturer use only.
111
BYPASS
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and
inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Bypass Register description for more information.
000
001
Rev: 1.12 5/2016
24/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the
Shift-DR state.
The ID Register is 32 bits wide, and is encoded as follows:
See BSDL Model
(31:12)
GSI ID
(11:1)
Start Bit
(0)
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 129 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (DQ, QVLD, CQ, CQ) are driven
directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST
instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state
does not appear at the output pins until the TAP Controller has reached the Update-DR state.
The value captured in the boundary scan register for NU pins is determined by the external pin state. The value captured in the
boundary scan register for NC pins is 0 regardless of the external pin state. The value captured in the Internal Cell (Bit 129) is 1.
Output Driver State During EXTEST
EXTEST allows the Internal Cell (Bit 129) in the Boundary Scan Register to control the state of DQ drivers. That is, when Bit 129
= 1, DQ drivers are enabled (i.e., driving High or Low), and when Bit 129 = 0, DQ drivers are disabled (i.e., forced to High-Z
state). See the Boundary Scan Register section for more information.
ODT State During EXTEST and SAMPLE-Z
ODT on all inputs is disabled during EXTEST and SAMPLE-Z.
Rev: 1.12 5/2016
25/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Boundary Scan Register Bit Order Assignment
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 129 is the
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out
through TDO.
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
1
7L
29
12F
57
12W
85
1T
113
1C
2
7K
30
11G
58
10W
86
4R
114
3C
3
9L
31
13G
59
8V
87
2R
115
2B
4
9K
32
10G
60
9U
88
3P
116
4B
5
8J
33
12G
61
8T
89
1P
117
5A
6
7H
34
11H
62
9R
90
4P
118
6A
7
9H
35
13H
63
8P
91
2P
119
6B
8
7G
36
10J
64
9N
92
3N
120
6C
9
8G
37
12J
65
8M
93
1N
121
5D
10
9F
38
13K
66
6M
94
4M
122
6E
11
8E
39
13L
67
7N
95
2M
123
5F
12
7D
40
11L
68
5N
96
3L
124
6G
13
9D
41
12M
69
7P
97
1L
125
5H
14
8C
42
10M
70
6P
98
1K
126
6J
15
7B
43
13N
71
5R
99
2J
127
5K
16
8B
44
11N
72
6T
100
4J
128
5L
17
9B
45
12P
73
7U
101
1H
129
Internal
18
7A
46
10P
74
5U
102
3H
19
9A
47
13P
75
6V
103
2G
20
10B
48
11P
76
6W
104
4G
21
12B
49
12R
77
7Y
105
1G
22
11C
50
10R
78
4W
106
3G
23
13C
51
13T
79
2W
107
2F
24
10D
52
11T
80
3V
108
4F
25
12D
53
12U
81
1V
109
1E
26
11E
54
10U
82
4U
110
3E
27
13E
55
13V
83
2U
111
2D
28
10F
56
11V
84
3T
112
4D
Rev: 1.12 5/2016
26/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
260-Pin BGA Package Drawing (Package GK)
0.08 S C
0.22 S C A S B S
Ø
Ø
Ø
0.50~Ø0.70(260x)
13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
19.00
17.40  0.05
22.00  0.05
1.00
PIN #1 CORNER
13.20  0.05
B
A
1.00
14.00  0.05
12.00
Rev: 1.12 5/2016
C
0.15
0.05
SEATING PLANE
0.40~0.60
0.51 REF
C
4–R0.5 (MAX)
0.50 + 0.03
0.10
HEAT SPREADER
//
1.09 REF
C
2.10 + 0.2/–0.3
0.06
0.05(4X)
Ball Pitch:
1.00 Substrate Thickness:
Ball Diameter:
0.60 Mold Thickness:
0.51
—
27/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Ordering Information — GSI SigmaDDR-IIIe ECCRAM
Org
Part Number
Type
Package
Speed
(MHz)
TA
8M x 18
GS81313LT18GK-833
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
833
C
8M x 18
GS81313LT18GK-714
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
714
C
8M x 18
GS81313LT18GK-625
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
625
C
8M x 18
GS81313LT18GK-833I
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
833
I
8M x 18
GS81313LT18GK-714I
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
714
I
8M x 18
GS81313LT18GK-625I
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
625
I
4M x 36
GS81313LT36GK-833
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
833
C
4M x 36
GS81313LT36GK-714
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
714
C
4M x 36
GS81313LT36GK-625
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
625
C
4M x 36
GS81313LT36GK-833I
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
833
I
4M x 36
GS81313LT36GK-714I
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
714
I
4M x 36
GS81313LT36GK-625I
SigmaDDR-IIIe B2
ROHS-Compliant 260-Pin BGA
625
I
Note: C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.12 5/2016
28/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81313LT18/36GK-833/714/625
Revision History
Rev. Code
Types of Changes
Format or Content
GS81313LT1836GK_r1.05
—
GS81313LT1836GK_r1.06
Content
• Removed leaded BGA package support.
GS81313LT1836GK_r1.07
Content
• Miscellaneous cleanup.
GS81313LT1836GK_r1.08
Content
•
•
•
•
•
•
•
GS81313LT1836GK_r1.09
Content
• Added input pulse width specs.
GS81313LT1836GK_r1.09a
Content
• Updated speed bins to -833, -714, and -625.
• Changed write latency from 1 to 0 cycles (late write to early write).
GS81313LT1836GK_r1.11
Content
• Removed “Preliminary” from data sheets.
• Added IDD specifications.
GS81313LT1836GK_r1.12
Content
• Increased VDD (min) to 1.2V for 625 MHz speed bin. VDD (min) is
now the same value for all speed bins.
Rev: 1.12 5/2016
Revisions
• Initial public release.
Increased VDD (max) to 1.35V.
Added package thermal impedances.
Added tKHKH (max) specs.
Revised tKHKDH specs.
Revised tKHQV, tKHQX, and tKHCQH specs.
Revised tCQHQV and tCQHQX specs.
Banner changed to “Preliminary”, to reflect ES status.
29/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology