PRELIMINARY ionos Embedded Sensor Setup and Imaging Pipeline (monochrome) for Aptina MT9V022, -V023, -V024 -V032, -V033, -V034 ver 1.0 OVERVIEW KEY FEATURES Helion's experience in image processing enables camera designers to use preengineered high quality algorithms directly on their camera system. BLOCK DIAGRAM Sensor Setup Interface I²C Sysclk RESET MT9V022, V032 MT9V023, V033 MT9V024, V034 Sensor Config. • • • • • • • • • • • • • Fast auto exposure with antiflicker and ROI support Fast automatic image sensor setup Automatic gain control Noise reduction for low light conditions Gamma correction True 72dB DR support APIX Transmit Interface with APIX setup Output interface for DSP with FiFo Output interface for CMOS/TTL TFT panel Parameter inserting Testpattern generator Overlay with graphical bitmap objects I²C configuration AE Statistics AE Engine Sensor Data (9:0) Linevalid Framevalid Pixelclock Sensor Capture (Interface) Linearization Defect Correction Fine Gain Gamma Correction Data Output Interface Copyright 2009 Helion GmbH, All Rights Reserved PRELIMINARY APPLICATION LICENSING • • • • The flexibilty of the ionos concept allows fast and at the same time cost-effective camera designs. The creation of an image sensor signal chain can easily be achieved by Helion's ionos-IP. Camera designers can choose ionos IP-blocks from the IP-Pool for customized applications. Image pre- and post-processing Image sensor control FPGA algorithms DSP algorithms Raw Bayer/ Monochrome Image Sensor 60 fps progressive FBAS DVI/Cameralink Encoder ---------------TFT Display Sensor Setup ionos FPGA The ionos Scheme Ready to use Companion Chip Individual Companion Chip Ready to use IP Blocks Image Engine with Standard Feature Set Image Engine with Custom Selectable IP Functions IP Blocks for Image Sensor Configuration, Image Pre-Processing - Sensor Setup - Fast Auto Exposure - Debayering - Color Space Conversion - Gamma Correction - Tonemapping (DRI/HDRI) Raw Bayer/ Monochrome µC / DSP OS like Linux Image Sensor 60 fps progressive Sensor Setup ionos FPGA - Sensor Setup - Fast Auto Exposure - Debayering - Color Space Conversion - Gamma Correction - Tonemapping (DRI/HDRI) Ethernet DELIVERABLES PERFORMANCE • • • • Encrypted, or plain text EDIF netlist Active-HDL automatic simulation macros Test with reference responses Technical documentation • Installation notes • HDL core specification • Datasheet • Synthesis scripts • Example application • Technical support ( optional) • IP Core implementation support • 3 month maintenance • Deliver the IP Core updates, minor or major Device Slices EBR MULT Max. Pixelclock XP2 2869 13 1x 36x36 1x 18x18 42 MHz version changes • Delivery the documentation updates • Email support Copyright 2009 Helion GmbH, All Rights Reserved