CCD linear image sensors S11155-2048-02 S11156-2048-02 Back-thinned CCD image sensors with electronic shutter function The S11155-2048-02 and S11156-2048-02 are back-thinned CCD linear image sensors with an internal electronic shutter for spectrometers. These image sensors use a resistive gate structure that allows a high-speed transfer. Each pixel has a lengthwise size needed by spectrometers but ensures readout with low image lag. Image lag on these products is reduced by nearly a magnitude of 10 as compared to the previous products (S11155-2048-01, S11156-2048-01). Note that the transmission of long wavelengths in the dead layer covering the horizontal shift register was reduced compared to previous products. Features Applications Built-in electronic shutter Spectrometers Minimum integration time: 2 μs Image readout High sensitivity from the ultraviolet region (spectral response range: 200 to 1100 nm) Readout speed: 10 MHz max. Image lag: 0.1% typ. Structure Parameter Pixel size (H × V) Number of total pixels (H × V) Number of effective pixels (H × V) Image size (H × V) Horizontal clock phase Output circuit Package Window*1 Cooling S11155-2048-02 14 × 500 μm S11156-2048-02 14 × 1000 μm 2128 × 1 2048 × 1 28.672 × 0.500 mm 28.672 × 1.000 mm 2-phase Two-stage MOSFET source follower 24-pin ceramic DIP (refer to dimensional outline) Quartz glass*2 Non-cooled *1: Temporary window type (ex. S11155-2048N-02) is available upon request. *2: Resin sealing Resistive gate structure In ordinary CCDs, one pixel contains multiple electrodes and a signal charge is transferred by applying different clock pulses to those electrodes [Figure 1]. In resistive gate structures, a single high-resistance electrode is formed in the active area, and a signal charge is transferred by means of a potential slope that is created by applying different voltages across the electrode [Figure 2]. Compared to a CCD area image sensor which is used as a linear sensor by line binning, a one-dimensional CCD having a resistive gate structure in the active area offers higher speed transfer, allowing readout with low image lag even if the pixel height is large. [Figure 1] Schematic diagram and potential of ordinary 2-phase CCD P1V P2V P1V [Figure 2] Schematic diagram and potential of resistive gate structure P2V REGL REGH STG TG Resistive gate N- N N- N- N N N- N P+ N- N N P P Potential slope KMPDC0320EA www.hamamatsu.com KMPDC0321EB 1 CCD linear image sensors S11155-2048-02, S11156-2048-02 Absolute maximum ratings (Ta=25 °C) Parameter Operating temperature*3 *4 Storage temperature Output transistor drain voltage Reset drain voltage Output amplifier return voltage All reset drain voltage Horizontal input source voltage All reset gate voltage Storage gate voltage Horizontal input gate voltage Summing gate voltage Output gate voltage Reset gate voltage Transfer gate voltage Symbol Topr Tstg VOD VRD Vret VARD VISH VARG VSTG VIG1H, VIG2H VSG VOG VRG VTG VREGH VREGL VP1H, VP2H Tsol High Low Horizontal shift register clock voltage Soldering conditions*5 Resistive gate voltage Min. -50 -50 -0.5 -0.5 -0.5 -0.5 -0.5 -12 -12 -12 -12 -12 -12 -12 Typ. - Max. +60 +70 +25 +18 +18 +18 +18 +15 +15 +15 +15 +15 +15 +15 Unit °C °C V V V V V V V V V V V V -12 - +15 V -12 +15 260 °C, within 5 s, at least 2 mm away from lead roots V - *3: Package temperature *4: The sensor temperature may increase due to heating in high-speed operation. We recommend taking measures to dissipate heat as needed. For more details, refer to the technical information “Resistive gate type CCD linear image sensors with electronic shutter”. *5: Use a soldering iron. Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product within the absolute maximum ratings. Operating conditions (Ta=25 °C) Parameter Output transistor drain voltage Reset drain voltage All reset drain voltage All reset gate voltage High*6 Low*7 Output gate voltage Storage gate voltage Substrate voltage Resistive gate high voltage Resistive gate low voltage High Low High Low Output amplifier return voltage*8 Horizontal input source Test point Horizontal input gate High Horizontal shift register clock voltage Low High Summing gate voltage Low High Reset gate voltage Low High Transfer gate voltage Low External load resistance Symbol VOD VRD VARD VARGH VARGL VOG VSTG VSS VREGHH VREGHL VREGLH VREGLL Vret VISH VIG1H, VIG2H VP1HH, VP2HH VP1HL, VP2HL VSGH VSGL VRGH VRGL VTGH VTGL RL Min. 12 13 13 7 0.5 2.5 2.5 0.5 -10.5 -10.5 -10.5 5 -6 5 -6 7 -6 9.5 -6 2.0 Typ. 15 14 14 8 1 3.5 3.5 0 1 -9.5 VREGHH - 8.0 -9.5 1 VRD -9.5 6 -5 6 -5 8 -5 10.5 -5 2.2 Max. 18 15 15 9 2 4.5 4.5 1.5 -8.5 2 8 -4 8 -4 9 -4 11.5 -4 2.4 Unit V V V V V V V V V V V V V V V V kΩ *6: All reset on *7: All reset off *8: Output amplifier return voltage is a positive voltage with respect to Substrate voltage, but the current flows in the direction of flow out of the sensor. 2 CCD linear image sensors S11155-2048-02, S11156-2048-02 Electrical characteristics [Ta=25 °C, fc=5 MHz, operating conditions: Typ. (P.2), timing chart (P.6, 7)] Parameter Signal output frequency Line rate Horizontal shift register capacitance All reset gate capacitance S11155-2048-02 Resistive gate capacitance S11156-2048-02 Summing gate capacitance Reset gate capacitance Transfer gate capacitance Charge transfer efficiency*9 DC output level Output impedance Output amplifier return current S11155-2048-02 Power consumption S11156-2048-02 Resistive gate resistance*12 S11155-2048-02 S11156-2048-02 Symbol fc LR CP1H, CP2H CARG CREG CSG CRG CTG CTE Vout Zo Iret PAMP*10 PREG*11 PAMP*10 PREG*11 RREG Min. 0.99995 9 50 30 0.4 0.7 Typ. 5 2 200 100 1000 2000 10 10 100 0.99999 10 300 0.4 75 100 75 60 0.7 1.1 Max. 10 4 11 160 90 1.4 2.2 Unit MHz kHz pF pF pF pF pF pF V Ω mA mW kΩ *9: Charge transfer efficiency per pixel of CCD shift register, measured at half of the full well capacity *10: Power consumption of the on-chip amplifier plus load resistance *11: Power consumption at REG *12: Resistance value between REGH and REGL Electrical and optical characteristics [Ta=25 °C, fc=5 MHz, operating conditions: Typ. (P.2), timing chart (P.6, 7)] Parameter Symbol Saturation output voltage Full well capacity*13 Linearity error*14 CCD node sensitivity Non-MPP operation Dark current*15 MPP operation Non-MPP operation Dark output nonuniformity MPP operation Readout noise Dynamic range*16 Defective pixels*17 Spectral response range Peak sensitivity wavelength Photoresponse nonuniformity*18 *19 Average image lag of all pixels Image lag*18 *20 Maximum image lag of all pixels Vsat Fw LR Sv DS DSNU Nr DR λ λp PRNU L S11155-2048-02 Min. Typ. Max. Fw × Sv 150 200 ±3 ±10 9 10 11 100 300 10 40 300 30 45 6670 0 200 to 1100 600 ±3 ±10 0.1 1 1 3 S11156-2048-02 Min. Typ. Max. Fw × Sv 150 200 ±3 ±10 9 10 11 200 600 15 60 300 30 45 6670 0 200 to 1100 600 ±3 ±10 0.1 1 1 3 Unit V ke% μV/eke-/pixel/s % e- rms nm nm % % Operating voltages typ. Signal level=1 ke- to 150 ke-. Defined so that the linearity error is zero when the signal level is at one-half the full well capacity. Dark current is reduced to half for every 5 to 7 °C decrease in temperature. Dynamic range (DR) = Full well capacity / Readout noise Pixels that exceed the DSNU or PRNU maximum Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 660 nm) Fixed pattern noise (peak to peak) × 100 [%] *19: Photoresponse nonuniformity = Signal *20: Percentage of unread signal level when a one-shot light pulse is irradiated so that the output is half the saturation output. The integration time during measurement is 5 μs for the S11155-2048-02 and 20 μs for the S11156-2048-02. For details, see the technical information (resistive gate type CCD linear image sensor with electronic shutter). *13: *14: *15: *16: *17: *18: 3 CCD linear image sensors S11155-2048-02, S11156-2048-02 Spectral response (without window)*21 (Typ. Ta=25 °C) 100 80 0.4 Photosensitivity (A/W) Quantum efficiency (%) (Typ. Ta=25 °C) 0.5 60 40 20 0.3 0.2 0.1 0 200 400 600 800 1000 1200 Wavelength (nm) 0 200 400 600 800 1000 1200 Wavelength (nm) KMPDB0316EA KMPDB0440EA *21: Spectral response with quartz glass is decreased according to the spectral transmittance characteristic of window material. Spectral transmittance characteristic of window material (Typ. Ta=25 °C) 100 Transmittance (%) 80 60 40 20 0 200 300 400 500 600 700 800 900 1000 Wavelength (nm) KMPDB0303EA 4 CCD linear image sensors S11155-2048-02, S11156-2048-02 Device structure (conceptual drawing of top view in dimensional outline) Effective pixels Thinning Horizontal shift register 22 19 18 17 16 Effective pixels 23 Horizontal CCD shift register D77 D78 D79 D80 21 20 Ȇ Ȇ 24 7 Ȇ D1D2 Ȇ Resistive gate area D65 D66 D67 D68 D69 D70 S1 S2 S3 S4 ȆȆ 2 S2045 S2046 S2047 S2048 Thinning Ȇ Ȇ D63 D64 8 D71 D72 D73 D74 D75 D76 Ȇ Ȇ Storage area 14 13 1 Ȇ Ȇ D63 D64 5 3 4 6 Horizontal CCD shift register 9 10 D77 D78 D79 D80 15 11 12 Horizontal shift register Note: When viewed from the direction of the incident light, the horizontal shift register is covered with a thick silicon layer (dead layer). However, long-wavelength light passes through the silicon dead layer and may possibly be detected by the horizontal shift register. To prevent this, provide light shield on that area as needed. Note that the transmission of long wavelengths in the dead layer covering the horizontal shift register was reduced compared to previous products. Signal charges that undergo photoelectric conversion at each pixel of the photosensitive area are directed upward or downward based on the boundary line at the center of the photosensitive area and transferred.Then, they are combined through the horizontal registers and read out by the amplifier. KMPDC0543EB 5 CCD linear image sensors S11155-2048-02, S11156-2048-02 Timing chart Non-MPP operation 1 line output period Tinteg (electronic shutter: open) Tpwar (electronic shutter: closed) ARG REGH, REGL (REGH=+1 V, REGL=-7.0 V) Tpwv Tovr TG Tpwh, Tpws P1H 1 2 3..2127 2128 2129 2130... N* P2H SG Tpwr RG OS D2 D79 D80 D1 D3..D70, S1...S2048, D71..D78 Normal readout period Dummy readout period * Apply clock pulses to the specified terminals during the period of dummy readout. Set the total number of clock pulses N, according to the integration time. KMPDC0541E KMPDC0541EB Parameter Pulse width ARG Rise and fall times Pulse width TG Rise and fall times Pulse width P1H, P2H*22 Rise and fall times Duty ratio Pulse width SG Rise and fall times Duty ratio Pulse width RG Rise and fall times TG - P1H Overlap time S11155-2048-02 Integration time S11156-2048-02 Symbol Tpwar Tprar, Tpfar Tpwv Tprv, Tpfv Tpwh Tprh, Tpfh Tpws Tprs, Tpfs Tpwr Tprr, Tpfr Tovr Tinteg Min. 1 200 2 20 50 10 40 50 10 40 5 5 1 2 2 Typ. 100 50 100 50 15 2 5 20 Max. 60 60 - Unit μs ns μs ns ns ns % ns ns % ns ns μs μs *22: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude. 6 CCD linear image sensors S11155-2048-02, S11156-2048-02 MPP operation 1 line output period Tinteg (electronic shutter: open) Tpwar (electronic shutter: closed) ARG (REGH=+1 V, REGL=-7.0 V) Tpwreg (REGH, REGL=-9.5 V) REGH, REGL Tpwv Tovr Tregtr TG Tpwh, Tpws P1H 1 2 3..2127 2128 2129 2130... N* P2H SG Tpwr RG OS D2 D79 D80 D1 D3..D70, S1...S2048, D71..D78 Normal readout period Dummy readout period * Apply clock pulses to the specified terminals during the period of dummy readout. Set the total number of clock pulses N, according to the integration time. KMPDC0542E KMPDC0542EB Parameter Symbol Min. Typ. *23 Pulse width Tpwar ARG Rise and fall times Tprar, Tpfar 200 Pulse width Tpwreg Tinteg - Tregtr Rise and fall times Tprreg, Tpfreg 100 REGH, REGL S11155-2048-02 2 5 Transfer time Tregtr S11156-2048-02 2 20 Pulse width Tpwv 2 TG Rise and fall times Tprv, Tpfv 20 Pulse width Tpwh 50 100 P1H, P2H*24 Rise and fall times Tprh, Tpfh 10 Duty ratio 40 50 Pulse width Tpws 50 100 SG Rise and fall times Tprs, Tpfs 10 Duty ratio 40 50 Pulse width Tpwr 5 15 RG Rise and fall times Tprr, Tpfr 5 TG - P1H Overlap time Tovr 1 2 S11155-2048-02 2 5 Integration time Tinteg S11156-2048-02 2 20 *23: The Min. value of Tpwar is equal to the normal readout period. *24: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude. Max. 60 60 - Unit μs ns μs ns μs μs ns ns ns % ns ns % ns ns μs μs 7 CCD linear image sensors S11155-2048-02, S11156-2048-02 Dimensional outline (unit: mm) 3.3 ± 0.35 Photosensitive area 28.672 Gold-plated, Alloy 42 0.6 ± 0.05* Index mark 27.94 ± 0.3 +0.05 12 1 0.25-0.03 10.03 ± 0.3 A 10.41 ± 0.25 13 24 Index mark 1.47 Photosensitive surface S11155-2048-02: A=0.500 S11156-2048-02: A=1.000 0.46 ± 0.05 2.54 ± 0.13 1.27 ± 0.2 1.83 ± 0.17 3.0 ± 0.5 1.27 ± 0.25 38.10 ± 0.4 * Glass thickness (refractive index≈1.5) Weight: 3.8 g typ. KMPDA0320EA Pin connections Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20*25 21*25 22 23 24 Symbol OS OD OG SG Vret RD REGL REGH P2H P1H IG2H IG1H ARG ARD ISH SS RD STG STG TG RG Function Output transistor source Output transistor drain Output gate Summing gate Output amplifier return Reset drain Resistive gate (low) Resistive gate (high) CCD horizontal register clock-2 CCD horizontal register clock-1 Test point (horizontal input gate-2) Test point (horizontal input gate-1) All reset gate All reset drain Test point (horizontal input source) Remark (standard operation) RL=2.2 kΩ +15 V +3.5 V Same pulse as P2H +1 V +14 V -7 V (Non-MPP operation) +1 V (Non-MPP operation) +6 V/-5 V +6 V/-5 V -9.5 V -9.5 V +8 V/+1 V +14 V Connect to RD Substrate Reset drain GND +14 V Storage gate Storage gate +3.5 V +3.5 V Transfer gate Reset gate +10.5 V/-5 V +8 V/-5 V *25: Pins 20 and 21 are shorted inside the package. 8 CCD linear image sensors S11155-2048-02, S11156-2048-02 Signal DC level (Reset level) Reset feed-through OS output waveform example (fc=5 MHz, RL=2.2 kΩ, VOD=+15 V) Signal level High-speed signal processing circuit example (using S11155/S11156-2048-02 and analog front-end IC) +3.3 V +5 V To FPGA 10 10 10 0.1 μF +VOD 10 μF 0.1 μF 0.1 μF 0.1 μF 10 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 1 24 23 22 21 20 19 18 17 16 15 14 13 RG TG NC STG STG NC RD SS NC ISH ARD ARG OS OD OG SG Vret RD REGL REGH P2H P1H IG2H IG1H 1 2 3 4 5 6 7 8 9 10 11 12 0.1 μF 0.1 μF 2.2 k 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDATA SCLK SLOAD AVDD AVSS CAPB CAPT VINB CML VING OFFSET VINR AVSS AVDD AD9826KRS D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) DR VSS DR VDD OEB ADCCLK CDSCLK2 CDSCLK1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 10 10 10 10 10 10 10 10 330 330 330 330 To FPGA 0.1 330 S11155/S11156-2048-02 KMPDC0561EA 9 CCD linear image sensors S11155-2048-02, S11156-2048-02 Related information www.hamamatsu.com/sp/ssd/doc_en.html Precautions ∙ Disclaimer ∙ Image sensors Technical information ∙ Resistive gate type CCD linear image sensors with electronic shutter C11165-02 Driver circuit for CCD linear image sensor (sold separately) The C11165-02 is a driver circuit designed for HAMAMATSU CCD linear image sensors S11155-2048-02, S11156-2048-02. The C1116502 can be used in spectrometer when combined with the CCD linear image sensor. Features Built-in 16-bit A/D converter Interface of computer: USB 2.0 Operates by DC+5 V Information described in this material is current as of December, 2015. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. www.hamamatsu.com HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184 U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 08807, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, 1 int. 6, 20020 Arese (Milano), Italy, Telephone: (39) 02-93581733, Fax: (39) 02-93581741 China: Hamamatsu Photonics (China) Co., Ltd.: B1201, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866 Cat. No. KMPD1155E02 Dec. 2015 DN 10