EL7154 ® Data Sheet March 8, 2007 High Speed, Monolithic Pin Driver Features The EL7154 three-state pin driver is particularly well suited for ATE and level shifting applications. The 4A peak drive capability, makes the EL7154 an excellent choice when driving high speed capacitive lines. • Comparatively low cost The P-Channel MOSFET is completely isolated from the power supply, providing a high degree of flexibility. Pin (7) can be grounded, and the output can be taken from pin (8) when a “source follower” output is desired. The N-Channel MOSFET has an isolated drain, but shares a common bus with pre-drivers and level shifter circuits. This is necessary to ensure that the N-Channel device can turn off effectively when VL goes below GND. In some power-FET and IGBT applications, negative drive is desirable to insure effective turn-off. The EL7154 can be used in these applications by returning VL to a moderate negative potential. • Clocking speeds up to 10MHz FN7278.2 • Three-State output • 3V and 5V Input compatible • 20ns Switching/delay time • 4A Peak drive • Isolated drains • Low output impedance: 2.5Ω • Low quiescent current: 5mA • Wide operating voltage: 4.5V to16V • Isolated P-Channel device • Separate ground and VL pins Pinout • Pb-free plus anneal available (RoHS compliant) EL7154 (8 LD PDIP, 8 LD SOIC) TOP VIEW Applications • Loaded circuit board testers VDD 1 VH • Digital testers 8 • Level shifting below GND • IGBT drivers THREE-STATE 2 3 • CCD drivers POUT LEVEL SHIFT AND LOGIC 7 VL 6 INPUT NOUT 4 5 GND VL VL Truth Table THREE-STATE INPUT POUT NOUT 0 0 Open Open 0 1 Open Open 1 0 HIGH Open 1 1 Open LOW Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047, #5,352,578, #5,352,389, #5,351,012, #5,374,898 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7154 Ordering Information PART NUMBER PART MARKING TAPE AND REEL PKG. DWG. # PACKAGE EL7154CN EL7154CN - 8 Ld PDIP MDP0031 EL7154CNZ EL7154CN Z - 8 Ld PDIP* (Pb-free) MDP0031 EL7154CS 7154CS - 8 Ld SOIC MDP0027 EL7154CS-T7 7154CS 7” 8 Ld SOIC MDP0027 EL7154CS-T13 7154CS 13” 8 Ld SOIC MDP0027 EL7154CSZ (See Note) 7154CSZ - 8 Ld SOIC (Pb-free) MDP0027 EL7154CSZ-T7 (See Note) 7154CSZ 7” 8 Ld SOIC (Pb-free) MDP0027 EL7154CSZ-T13 (See Note) 7154CSZ 13” 8 Ld SOIC (Pb-free) MDP0027 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Nominal Operating Voltage Range PIN MIN MAX VL -3 0 VDD to VL 5 15 VH to VL 2 15 -0.5 15 5 15 VDD to VH VDD 2 FN7278.2 March 8, 2007 EL7154 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply (VDD to VL; VH to VL, VH to GND), V+ to VH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V Input Pins . . . . . . . . . . . . . . . . . -0.3V below VL to +0.3V above VDD Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER TA = +25°C, VDD = +12V, VH = +12V, VL = -3V, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current VHVS Input Hysteresis 2.4 VIH = VDD V 0.1 VIL = 0V 0.1 10 µA 0.6 V 10 µA 0.3 V OUTPUT ROH Pull-Up Resistance IOUT = -100mA 1.5 4 Ω ROL Pull-Down Resistance IOUT = +100mA 2 4 Ω IOUT Output Leakage Current VDD/GND 0.2 10 µA IPK Peak Output Current Source/Sink 4.0 IDC Continuous Output Current Source/Sink IS Power Supply Current Inputs = VDD VS Operating Voltage IG Current to GND (Pin 4) IH Off Leakage at VH A 200 mA POWER SUPPLY AC Electrical Specifications PARAMETER 1 2.5 mA 16 V 1 10 µA 1 10 µA TYP MAX UNITS CL = 100pF 4 25 ns CL = 2000pF 20 25 ns 4.5 Pin 8 = 0V TA = +25°C unless otherwise specified DESCRIPTION TEST CONDITIONS MIN SWITCHING CHARACTERISTICS (VDD = VH = 12V; VL = -3V) tR tF Rise Time Fall Time CL = 100pF 4 CL = 2000pF 20 tD-1 Turn-Off Delay Time CL = 2000pF 20 25 ns tD-2 Turn-On Delay Time CL = 2000pF 10 25 ns tD-1 Three-State Delay 25 ns tD-2 Three-State Delay 25 ns 3 FN7278.2 March 8, 2007 EL7154 Timing Table Standard Test Configuration 4 FN7278.2 March 8, 2007 EL7154 Typical Performance Curves FIGURE 1. MAX POWER DERATING CURVES FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 3. INPUT CURRENT vs VOLTAGE FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE FIGURE 5. QUIESCENT SUPPLY CURRENT FIGURE 6. “ON” RESISTANCE vs SUPPLY VOLTAGE FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY 5 FIGURE 8. RISE/FALL TIME vs LOAD FN7278.2 March 8, 2007 EL7154 Typical Applications FIGURE 9. PIN DRIVER FIGURE 10. ADJUSTABLE AMPLITUDE PULSE GENERATOR FIGURE 11. IGBT DRIVER WITH NEGATIVE SWING FIGURE 12. PMDS FOLLOWER FIGURE 13. RESONANT GATE DRIVER 6 FN7278.2 March 8, 2007 EL7154 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 7 FN7278.2 March 8, 2007 EL7154 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN7278.2 March 8, 2007