MIPI D-PHY Interface IP - Documentation

MIPI D-PHY Interface IP
January 2015
Reference Design RD1182
Introduction
The Mobile Industry Processor Interface (MIPI) has become a specification standard for interfacing components in
consumer mobile devices. A very popular MIPI bus which provides high speed connectivity is call the D-PHY. The
MIPI D-PHY specification provides a physical layer definition, which is typically used for camera and display interfacing. The MIPI D-PHY Interface IP allows moderate to advanced FPGA users the capability to receive and transmit data with respect to the MIPI D-PHY specification. Furthermore, the D-PHY Interface IP is the foundation for
higher layer protocol designs such as MIPI CSI2 and DSI.
Key Features
• Interfaces to MIPI CSI2 and DSI, RX and TX devices
• Supports Unidirectional HS (High Speed) mode
• Supports Bidirectional LP (Low Power) operation modes
• Deserializes and Serializes HS (High Speed) data into byte data packets.
• Provides methods for contention detection and termination switching
MIPI D-PHY Operational Overview
The MIPI D-PHY is a bus which incorporates one clock lane and from one to four data lanes. The clock and data
lanes can switch between two 1.2 V LVCMOS signals or one differential SLVS200 pair. Operating in differential
mode is referred to as HS (High Speed) mode. In HS mode, video data is delivered over a differential pair. For
example, video data being sent from an image sensor is sent in HS mode. The clock is center aligned with the data
in HS mode.
Figure 1. D-PHY Clock to Data Relationship for HS Mode
clock
data
Depending on the application, the HS mode may be utilized at all times or the D-PHY can switch from HS differential lanes to single ended. When the D-PHY is sending single ended data, this is called LP (Low Power) mode. In
Camera and Display applications, LP is entered during the blanking period to reduce power. Additionally, in Display
applications, LP mode is used for configuration of the screen.
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RD1182_1.5
MIPI D-PHY Interface IP
Functional Description
The MIPI D-PHY Interface IP is provided in two Lattice Diamond® projects. Each project instantiates the receiving
or the transmitting D-PHY IP modules individually. For the purpose of this document the RX interface IP refers to
the design which receives HS (High Speed) data and the TX interface IP refers to the design which transmits HS
data. In both designs, LP data can be transferred bi-directionally on any data or clock lane. HS data is deserialized/serialized to and from single data rate byte packets respectively. LP data is provided as a two bit interface for
individual extraction and control of the P and N wire pair. An external resistor network is needed on the interface
pins of the FPGA. This resistor network is different for RX and TX modules. Both modules support bidirectional LP
communication and unidirectional HS communication.
Receiving Interface
The D-PHY RX IP gives users the ability to receive HS data on one clock lane and up to four data lanes. Each
clock and data lane uses a total of four IOs. Two IO pins are used to receive the HS data with the LVDS25 IO
type, which configures them as differential. The LVDS25 IO pair must be used in order to handle the 200 mV
common mode voltage. The other two IOs provide 50 Ohm single ended termination by driving each
LVCMOS12 signal to 0 V while in HS mode. Additionally, the LVCMOS12 signals are configured to transmit and
receive bidirectional CMOS data during LP mode.
Figure 2. Unidirectional Receive HS Mode and Bidirectional LP Mode Interface Implementation
MIPI D-PHY
TX Device
50 Ohm
LPCLK[1]
CLOCK_P
DCK_p
CLOCK_N
LPCLK[0]
DCK_n
LVCMOS12
LVDS25
LVCMOS12
LP0[1]
LVCMOS12
DATA0_P
D0_n
DATA0_N
LP0[0]
LVDS25
LVCMOS12
50 Ohm
50 Ohm
LP3[1]
IO Controller
D0_p
Aligner
50 Ohm
iDDRx4
50 Ohm
LVCMOS12
DATA3_P
D3_p
D3_n
LVDS25
DATA3_N
LP3[0]
LVCMOS12
50 Ohm
In some applications LP mode is not needed. If this is the case only two IO's are needed and a single 100 Ohm
parallel termination resistor can be used. If the Lattice FPGA being used has built in 100 Ohm termination, this can
be used in this case as well. See Figure 3 for this simplified interface.
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MIPI D-PHY Interface IP
Figure 3. Unidirectional Receive HS Mode Only Interface Implementation
MIPI DPHY
TX Device
LATTICE FPGA
CLOCK_P
DPHY RX Module
DCK_p
100 Ohm
DCK_n
LVDS25
D0_n
LVDS25
DATA0_N
DATA3_P
IO Controller
D0_p
100 Ohm
Aligner
DATA0_P
iDDRx4
CLOCK_N
D3_p
100 Ohm
D3_n
LVDS25
DATA3_N
Within the D-PHY RX module HS data is deserialized using iDDR gearbox primitives. The MachXO2™ design uses
the iddrx4 gearbox primitive which derives a divide-by-4 clock and 8-bit byte data directly. LatticeECP3™ FPGA's
use the iddrx2 gearbox primitives with additional down conversion logic to derive this same divide-by-4 clock and 8bit data bus. The number of HS data lanes used can be controlled by `define compiler directives. Options are , 2, 3
or 4 data lanes. The HS clock lane is available at all times.
The MIPI byte clock only runs while in HS mode. The MIPI clock is not continuous unless the user places the transmitting device in "free-running" clock mode. This reference design can run with or without a "free-running" clock.
However, it's important to understand and consider design accommodations that need to take place in order to continue the processing of data when the clock lane is in LP mode.
If a PLL is expected to be used in a particular RX D-PHY design, a continually running clock needs to be obtained
in some way since PLL in the FPGA will take as much as milliseconds to lock. Obtaining a continually running clock
can be achieved in multiple ways. One common practice is to place the transmitting device in free-running clock
mode. This causes the clock lane to never enter LP mode and remain continually operating in HS mode. For both
CSI-2 and DSI, there is a requirement in the specification that all transmitting and receiving devices must have the
capability of operating with a continually running clock. Therefore, running the clock lane in LP mode is a user preference. If it is desired to have the clock lane enter LP mode, then the second common practice is to use a secondary clock source that is either on the same clock domain or very close to the same frequency as the MIPI clock.
The data on the MIPI clock is then converted to the secondary clock domain using a crossing clock domain FIFO.
The third common practice is to use a clock mux with a secondary clock very close to the HS clock and switch
between clocks during LP and HS mode transitions in attempts to keep the PLL locked.
After the data is deserialized the 8-bit data is byte and lane aligned so that MIPI byte data is available on each byte
clock cycle. This alignment is done based on the recognition of the MIPI HS_Sync sequence, which is transmitted
on all data lanes one clock cycle before the packet header. hs_en is used to reset the alignment module. When
hs_en is 'low' the word alignment is reset; when 'high' the word aligner looks for the next HS_Sync sequence seen.
The sync signal will initially be 'low'. The sync signal will go high when the HS_Sync sequence is detected and the
byte data at the output of the aligner are properly aligned.
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MIPI D-PHY Interface IP
The aligner module consists of two subsidiary modules. The first module byte aligns the 8-bit data from the deserializer. The second module aligns each of the data lanes to each other. In some cases lane alignment or lane and
word alignment is not needed. `define compiler directives allow the user to turn on and off the word and lane alignment features.
HS termination is controlled by the term_en signal the IO_Controller module. Although there is no direct contention
detection mechanism with this design, enabling the termination can be done in a number of ways. One way is to
use the HS clock to observe the LP to HS data transition on one of the data lines since the clock lane will enter HS
mode sooner and exit HS mode later than the data lines.
Another option is to initializing the LP signals as inputs at startup and watch for the LP to HS on the individual clock
and data lanes. Once the sequence is detected term_en can be set 'low' by the user enabling the termination.
Once enabled the HS data can be observed for any conditions desired to leave HS mode. Condition examples
would be EoT (End of Transmission Packets), observation of the end of a packet with no consecutive bursting
packet, bad ECC or checksum, timeout if no packet header or HS-Sync sequence is seen after a certain amount of
time, etc.
The IO_Controller module also controls LP signals. Each data lane has a lp*_dir signal which controls the direction
of the LP data between the transmitting device and the FPGA. `define compiler directives allow users to turn on/off
LP IO for each clock and data lane individually. This can be handy if the user only needs LP mode for one or two
MIPI D-PHY data lanes. The LP signals are defined as two bit busses. Although there is no difference between signal 1 and 0 of a bus, signal 1 is typically connected to the P wire side and 0 to the N wire side. This is simply to
keep consistency with the LP transition identification scheme.
Figure 4. D-PHY RX Module Functional Block Diagram
DPHY RX Module
reset_n
byte_clk
D1
D2
byte_D0 [7:0]
byte_D1 [7:0 ]
Aligner
D0
iDDRx4
DCK
data[31:0]
D3
hs_en
term_en
lp0_dir
lp1_dir
lp2_dir
byte_D3 [7:0]
sync
lpclk_out [1:0]
lp0_out [1:0]
lp1_out [ 1:0]
lp2_out [ 1:0]
lp3_out [1:0]
IO_Controller
LPCLK[1:0]
LP0 [1:0]
LP1 [1:0]
LP2 [1:0]
LP3 [1:0]
byte_D2 [7:0]
lpclk_in [1:0]
lp0_in [1:0]
lp1_in [1:0]
lp2_in [1:0]
lp3_in [1:0]
lp3_dir
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MIPI D-PHY Interface IP
Table 1. D-PHY RX Compiler Directives
Directive
Description
`define HS_3
Generates IO for four HS data lanes.
`define HS_2
Generates IO for four HS data lanes.
Overridden if HS_3 is defined.
`define HS_1
Generates IO for four HS data lanes.
Overridden if HS_3 or HS_2 is defined.
`define HS_0
Generates IO for four HS data lanes
Overridden if HS_3, HS_2, or HS_1 is defined.
`define LP_CLK
Generates IO for LP mode on clock lane
`define LP_0
Generates IO for LP mode on data lane 0
`define LP_1
Generates IO for LP mode on data lane 1
`define LP_2
Generates IO for LP mode on data lane 2
`define LP_3
Generates IO for LP mode on data lane 3
Table 2. D-PHY RX Module IO List
Signal
Direction
Description
reset_n
Input
Resets module (Active 'low')
DCK
Input
HS (High Speed) Clock
D0
Input
HS Data lane 0
D1
Input
HS Data lane 1
D2
Input
HS Data lane 2
D3
Input
HS Data lane 3
hs_en
Input
Initializes word aligner to align on next HS-Sync Sequence
byte_clk
Output
Byte Clock = DCK/4
byte_D0 [7:0]
Output
Byte data, data lane 0
byte_D1 [7:0]
Output
Byte data, data lane 1
byte_D2 [7:0]
Output
Byte data, data lane 2
byte_D3 [7:0]
Output
Byte data, data lane 3
sync
Output
Active 'high' when byte data is aligned
LPCLK [1:0]
Bidirectional
LP clock lane; LPCLK[1] = P wire, LPCLK[0] = N wire
LP0 [1:0]
Bidirectional
LP data lane 0; LP0[1] = P wire, LP0[0] = N wire
LP1 [1:0]
Bidirectional
LP data lane 1; LP1[1] = P wire, LP1[0] = N wire
LP2 [1:0]
Bidirectional
LP data lane 2; LP2[1] = P wire, LP2[0] = N wire
LP3 [1:0]
Bidirectional
LP data lane 3; LP3[1] = P wire, LP3[0] = N wire
term_en
Input
Enables termination by setting LP signals at outputs and 'low'
Overrides lp_dir control signal
lpclk_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp0_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp1_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp2_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
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MIPI D-PHY Interface IP
Signal
Direction
Description
lp3_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lpclk_out [1:0]
Output
LP data receive
Available when lp_dir = '0' and term_en = '0'
lp0_out [1:0]
Output
LP data receive
Available when lp_dir = '0' and term_en = '0'
lp1_out [1:0]
Output
LP data receive
Available when lp_dir = '0' and term_en = '0'
lp2_out [1:0]
Output
LP data receive
Available when lp_dir = '0' and term_en = '0'
lp3_out [1:0]
Output
LP data receive
Available when lp_dir = '0' and term_en = '0'
lpclk_in [1:0]
Input
LP data transmit
Available when lp_dir = '1' and term_en = '0'
lp0_in [1:0]
Input
LP data transmit
Available when lp_dir = '1' and term_en = '0'
lp1_in [1:0]
Input
LP data transmit
Available when lp_dir = '1' and term_en = '0'
lp2_in [1:0]
Input
LP data transmit
Available when lp_dir = '1' and term_en = '0'
lp3_in [1:0]
Input
LP data transmit
Available when lp_dir = '1' and term_en = '0'
Transmitting Interface
The transmitting interface gives users the ability to utilize to one clock lane and up to four data lanes. Each lane
uses a total of four IOs. Two IO pins are used to transmit the HS data with the LVDS25E IO type which configures
the output pins as differential pairs. The other two IO's are used to provide a voltage dividing circuit while in HS
mode and to transmit or receive 1.2 V CMOS data in LP mode. See Figure 5. Please note that in some applications
LP mode is not needed. If this is the case only two FPGA IOs are needed instead of four. The 50 Ohm resistors can
be replaced with 70 Ohm resistors tied to the ground, in place of the 1.2 V of the LVCMOS IO connections. See
Figure 6.
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MIPI D-PHY Interface IP
Figure 5. Unidirectional Transmit HS Mode and Bidirectional LP Mode Interface Implementation
Lattice FPGA
MIPI DPHY
RX Device
50 Ohm
DPHY TX
Module
LVCMOS12
iDDRx4
LVCMOS12
LVCMOS12
CLOCK_P
330 Ohm
CLOCK_N
50 Ohm
50 Ohm
330 Ohm
DATA0_P
330 Ohm
DATA0_N
LVDS25E
LVCMOS12
IO Controller
330 Ohm
LVDS25E
50 Ohm
50 Ohm
LVCMOS12
330 Ohm
DATA3_P
330 Ohm
DATA3_N
LVDS25E
LVCMOS12
50 Ohm
Figure 6. Unidirectional Transmit HS Mode Only Implementation
Lattice FPGA
IO Controller
iDDRx4
DPHY TX
Module
MIPI DPHY
RX Device
330 Ohm
70 Ohm
CLOCK_P
330 Ohm
CLOCK_N
70 Ohm
330 Ohm
70 Ohm
DATA_P
330 Ohm
DATA_N
70 Ohm
LVDS25E
LVDS25E
70 Ohm resistors
connected to ground
for HS-only mode.
330 Ohm
70 Ohm
DATA_P
330 Ohm
DATA_N
70 Ohm
LVDS25E
Within the D-PHY TX module HS data is serialized using oddr gearbox primitives. The MachXO2 design uses the
oddrx4 gearbox primitive. LatticeECP3 FPGA's use the oddrx2 gearbox primitives with additional up conversion
logic to serialize the byte data. MIPI D-PHY data is center aligned and therefore a PLL with a 0 and 90 degree
phase shifting is used for the HS data and clock respectively.
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MIPI D-PHY Interface IP
The IO_Controller module controls the HS and LP data traffic. The hs_clk_en and hs_data_en signals place the
clock and data lanes in HS mode when active 'high'. While in HS mode the IO controller sets the CMOS signals low
to create a voltage divider network on the emulated LVDS output signals to achieve a 200 mV common mode voltage. When hs_clk_en or hs_data_en is 'low', the LVDSE IO is set to high impedance so it does not interfere with LP
data transmissions. There is an hs_clk_en control signal and an hs_data_en signal, because the MIPI specification
defines the clock lane going in to and out of HS mode before and after the data lanes. The lp_dir signal controls the
LP mode direction. The lp*_dir control signal is overridden when hs_*_en='1'. The IO_Controller module also controls LP data traffic while in LP mode. lp*_dir signals control the direction of LP data being transmitted or received.
Compiler directives control the IO available for the HS data lanes as well as which lanes will have LP control IO.
The LP signals are defined as two bit busses. Although there is no difference between signal 1 and 0 of a bus, signal 1 is typically connected to the P wire side and 0 to the N wire side. This is simply to keep consistency with the
LP transition identification scheme.
Figure 7. D-PHY TX Module Functional Block Diagram
DPHY TX Module
reset_n
bit_clk
PLLx4
hs_clk
DCK
hs_D0
D0
hs_D1
D1
bit_clk_90
oDDRx4
byte_clk
byte_D0 [7:0]
byte_D1 [7:0]
byte_D2 [7:0]
hs_D2
D2
hs_D3
byte_D3 [7:0]
D3
IO_Controller
hs_en
lpclk_dir
lp0_dir
lp1_dir
lp2_dir
lp3_dir
lpclk_out [1:0]
LPCLK [1:0]
LP0 [1:0]
LP1 [1:0]
lp0_out [1:0]
lp1_out [1:0]
lp2_out [1:0]
lp3_out [1:0]
LP2 [1:0]
LP3 [1:0]
lpclk_in[1:0]
lp0_in [1:0]
lp1_in [1:0]
lp2_in [1:0]
lp3_in [1:0]
Table 3. D-PHY TX Compiler Directives
Directive
Description
`define HS_3
Generates IO for four HS data lanes.
`define HS_2
Generates IO for four HS data lanes.
Overridden if HS_3 is defined.
`define HS_1
Generates IO for four HS data lanes.
Overridden if HS_3 or HS_2 is defined.
`define HS_0
Generates IO for four HS data lanes.
Overridden if HS_3, HS_2, or HS_1 is defined.
`define LP_CLK
Generates IO for LP mode on clock lane
`define LP_0
Generates IO for LP mode on data lane 0
`define LP_1
Generates IO for LP mode on data lane 1
`define LP_2
Generates IO for LP mode on data lane 2
`define LP_3
Generates IO for LP mode on data lane 3
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MIPI D-PHY Interface IP
Table 4. D-PHY TX Module IO List
Signal
Direction
Description
reset_n
Input
Resets module (Active 'low')
DCK
Output
HS (High Speed) Clock
D0
Output
HS Data lane 0
D1
Output
HS Data lane 1
D2
Output
HS Data lane 2
D3
Output
HS Data lane 3
byte_clk
Input
Byte Clock = DCK/4
byte_D0 [7:0]
Input
Byte data, data lane 0
byte_D1 [7:0]
Input
Byte data, data lane 1
byte_D2 [7:0]
Input
Byte data, data lane 2
byte_D3 [7:0]
Input
Byte data, data lane 3
LPCLK [1:0]
Bidirectional
LP clock lane; LPCLK[1] = P wire, LPCLK[0] = N wire
LP0 [1:0]
Bidirectional
LP data lane 0; LP0[1] = P wire, LP0[0] = N wire
LP1 [1:0]
Bidirectional
LP data lane 1; LP1[1] = P wire, LP1[0] = N wire
LP2 [1:0]
Bidirectional
LP data lane 2; LP2[1] = P wire, LP2[0] = N wire
LP3 [1:0]
Bidirectional
LP data lane 3; LP3[1] = P wire, LP3[0] = N wire
hs_clk_en
Input
Enable HS clock on output, Sets LPCLK signals 'low'
Overrides lpclk_dir control signal
hs_data_en
Input
Enable HS clock on output, Sets LP0, LP1, LP2 and LP3 signals 'low'
Overrides lp0_dir - lp3_dir control signals
lpclk_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp0_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp1_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp2_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lp3_dir
Input
Controls the direction of LP data
'0' - LP data receive
'1' - LP data transmit
lpclk_out [1:0]
Input
LP data receive
Available when lp_dir = '0' and hs_en = '0'
lp0_out [1:0]
Input
LP data receive
Available when lp_dir = '0' and hs_en = '0'
lp1_out [1:0]
Input
LP data receive
Available when lp_dir = '0' and hs_en = '0'
lp2_out [1:0]
Input
LP data receive
Available when lp_dir = '0' and hs_en = '0'
lp3_out [1:0]
Input
LP data receive
Available when lp_dir = '0' and hs_en = '0'
lpclk_in [1:0]
Output
LP data transmit
Available when lp_dir = '1' and hs_en = '0'
lp0_in [1:0]
Output
LP data transmit
Available when lp_dir = '1' and hs_en = '0'
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MIPI D-PHY Interface IP
Signal
Direction
Description
lp1_in [1:0]
Output
P data transmit
Available when lp_dir = '1' and hs_en = '0'
lp2_in [1:0]
Output
LP data transmit
Available when lp_dir = '1' and hs_en = '0'
lp3_in [1:0]
Output
LP data transmit
Available when lp_dir = '1' and hs_en = '0'
Packaged Design
Reference IP designs are available for MachXO2, MachXO3L, LatticeECP3 and ECP5™ programmable devices.
The “rd1182_mipi_dphy_interface_ip” package contains designs for all of these devices. The “source” folder contains Verilog source code. Much of the code for LatticeECP3, ECP5, MachXO2 and MachXO3L is shared and utilizes the exact same Verilog source code files. Source code that is device specific is contained within a subfolder
labelled “ecp3”, “ecp5”, “xo2” or “xo3l”. A verilog testbench is provided in the “testbench” folder for RX and TX DPHY designs. The “ecp3”, “ecp5”, “xo2” and “xo3l” folders contain the RX and TX project subfolders for the
LatticeECP3, ECP5, MachXO2 and MachXO3L designs respectively. Each RX and TX design contains a Lattice
Diamond project directory labeled “dphy_rx” and “dphy_tx”. Simulation project directory labeled “simulation” contains VO files for simulation. Please note that is recommended that you access the simulation through Lattice Diamond software. This is described further in the Simulation section of this document.
Figure 8. MIPI D-PHY Interface IP File Directory Structure
Table 5. MIPI D-PHY Interface IP File Directory Summary
Folder
Summary
rd1182_mipi_dphy_interface_ip
Main file directory containing reference IP
docs
Contains RD documents
project
Contains LatticeECP3, ECP5, MachXO2 and MachXO3L projects
simulation
Contains do files and VO files
source
Contains Verilog source code
testbench
Contains Verilog testbench
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MIPI D-PHY Interface IP
Simulation
A simulation project and testbench is available for RX and TX devices. The simulation environment can be
accessed by double clicking on the Simulation.spf script file in Lattice Diamond from the file list. Aldec ActiveHDL
will then open after clicking OK to the pop-up windows. Compile the project and initialize the simulation. Add signals to the waveform viewer that are desired to be viewer and run the simulation.
Figure 9. Simulation Wizard Script File Access
The simulation testbench sends data typical of what would be seen on a MIPI Data transmission. The testbench is
configured for four HS and LP data lanes and an HS and LP clock lane. For the RX D-PHY Interface IP, simulation
serial data is generated in the testbench. It is then decoded by the reference IP. For the TX D-PHY Interface IP, byte
data is generated by the testbench which is then serialized by the reference IP.
Figure 10. RX Simulation
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MIPI D-PHY Interface IP
Figure 11. TX simulation
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MIPI D-PHY Interface IP
IBIS Simulation
IBIS Functional Simulation was used to ensure proper differential and common mode voltage levels for RX and TX
resistor network setups.
The RX resistor network was simulated to ensure proper functionality in various LP and HS modes. The resistor
network for the HS mode was simulated at 375 Mhz using a CSI2 TX IBIS model to drive the waveform.
Figure 12. IBIS RX, HS-Mode Simulation Circuit
U58
1
R89
50.0 Ohms
2 XO2
lvd250f080aaaaaa...
U59.1
0
R88
R69
TL14
0.0 Ohms
R70
49.9 Ohms
460.894 ps
3.000 in
Stackup
TL15
U55
50.0 Ohms
1
2
MIPI TX Drvr
DATA0-
XO2
lvc120f060aaaaaa...
U56.1
0
XO2
lvc120f060aaaaaa...
0.0 Ohms
49.9 Ohms
460.894 ps
3.000 in
Stackup
13
MIPI D-PHY Interface IP
Figure 13. IBIS RX, HS-Mode Simulation Eye Waveform
The TX resistor network was simulated to ensure proper functionality in various LP and HS modes. Most importantly HS mode was simulated based on the recommended TX test setup in the MIPI D-PHY specification under
typical conditions.
Figure 14. IBIS TX, HS-Mode Simulation Circuit
U3.1
R3
C2
0
50.0 Ohms
XO2
lvc120f060aaaaaa...
R1
U2
1
R2
2.0 pF
50.0 Ohms
320.0 Ohms
C3
2
XO2
320.0 Ohms
lvd250f080aaaaaa...
U1.1
R6
R7
R4
2.0 pF
C1
0
50.0 Ohms
XO2
lvc120f060aaaaaa...
2.0 pF
14
50.0 Ohms
MIPI D-PHY Interface IP
Figure 15. IBIS TX, HS-Mode Simulation Eye Waveform
Tested with MachXO2 Drivers at 375 Mhz under typical conditions. The waveform in green represents the simulated differential voltage. The waveform in orange represents the simulated common mode voltage.
15
MIPI D-PHY Interface IP
Hardware Analysis
Hardware Analysis was performed on the RX and TX D-PHY Reference IP using a Snapdragon S4 Plus
APQ8060A Development Platform and a MachXO2-4000 adapter board. The RX and TX Reference IP designs
were connected back to back. MIPI DSI data was received from the APQ8060 to the MachXO2 device. The RX reference IP deserialized, word aligned, and lane aligned the two MIPI D-PHY data lanes. The aligned data was then
sent to the TX Reference IP which serialized and sent the data to output pins. This data was then transmitted from
the MachXO2 to the Wintek DSI display that comes with the development platform. This test verified both LP and
HS communication. The LP data was received and transmitted on one clock lane and two data lanes. Also data
lane 0 configured the panel with MIPI DCS (Display Command Set) commands. The HS data was received and
transmitted on two data lanes and one clock lane.
Figure 16. Hardware Development Platform Setup
Receiving termination options were tested by viewing data transmissions with and without 50 Ohm and 100 Ohm
terminations. When 50 Ohm terminations released by setting CMOS signals to inputs, LP data could be captured
at 1.2 V.
16
MIPI D-PHY Interface IP
Figure 17. Receiving HS Data with No Termination, Internal 100 Ohm Parallel Termination and 50 Ohm
Single Ended Termination
Top - No Termination. Middle - Internal 100 Ohm Parallel Termination.
Bottom - 50 Ohm Single Ended Termination. Captured with 500 Mhz, single ended probe.
The transmission interface was tested to ensure HS and LP data could be delivered at the appropriate voltages. HS
Data was tested to ensure a 200 mV common mode voltage at a +–100 mV differential voltage.
17
MIPI D-PHY Interface IP
Figure 18. Clock and Data Transmission Waveforms from Lattice MachXO2 Device Showing HS and LP
Modes
Captured with 500 Mhz, single ended probe.
HS Clock and Data at ~320 Mbps Transmission Clock eye diagram
Figure 19. Clock and Data Transmission Eye Diagrams from Lattice MachXO2 Device in HS Mode
Captured with 16 Ghz, Differential probe. Clock at ~160 Mhz.
18
MIPI D-PHY Interface IP
Captured with 16 Ghz, Differential probe. Data at ~320 Mbps.
Device Pinout and Bank Voltage Requirements
Choosing a proper pinout to interface with another D-PHY device is essential to meet functional and timing requirements.
The following are rules for choosing a proper pinout on MachXO2 devices:
• Bank 2 should be used for HS inputs (DCK, D0, D1, D2, D3) with the RX D-PHY IP since these pins utilize
iDDRx4 gearbox primitives
• Bank 0 should be used for HS outputs (DCK, D0, D1, D2, D3) with the TX D-PHY IP since these pins utilize
oDDRx4 gearbox primitives
• The VCCIO voltage for banks 0 and 2 should be 2.5 V
• The HS input clock (DCK) for the RX D-PHY IP should use an edge clock on bank 2
• The HS data signals (D0, D1, D2, D3) for the RX and TX D-PHY IP's should only use A/B IO pairs
• LP signals (LPCLK, LP0, LP1, LP2, LP3) for RX and TX D-PHY IP's can use any other bank
• The VCCIO voltage for the bank containing LP signals (LPCLK, LP0, LP1, LP2, LP3) should be 1.2 V
• When in doubt, run the pinout through Lattice Diamond software and check for errors
With the rules mentioned a recommend pinout is provided for the most common packages used for this IP. For the
MachXO2 the cs132bga is the most common package. The pinouts chosen below are pin compatible with
MachXO2-1200, MachXO2-2000 and MachXO2-4000 devices.
19
MIPI D-PHY Interface IP
Table 6. Recommended RX Pinout and Package
Signal
MachXO2
1200/2000/4000
cs132bga Package
MachXO3L 2100C
caBGA256 Package
LatticeECP3-150EA
fpBGA1156
ECP5 LFE5U-45F8MG285C
DCK_p
Bank 2
Bank 2
Bank 2
Bank 3
DCK_n
N6
P6
T7
R8
U26
U27
H4
G4
D0_p
M11
P8
L26
M3
D0_n
P12
T8
M25
L3
D1_p
P8
R7
L32
K3
D1_n
M8
P7
L31
K1
D2_p
P2
T5
L34
K2
D2_n
N2
R6
L33
L1
D3_p
N3
P4
K29
M2
D3_n
P4
T4
K30
N2
LPCLK [1]
Bank 1
J13
Bank 1
P16
Bank 7
P5
N8
Bank 2
A2
LPCLK [0]
K12
N15
A3
LP0 [1]
K13
L15
N1
B7
LP0 [0]
K14
M14
N10
C7
LP1 [1]
L14
M16
N2
B2
LP1 [0]
M13
M15
M10
D6
LP2 [1]
M12
P15
N3
D1
LP2 [0]
M14
N14
N5
C1
LP3 [1]
N13
R16
N4
D2
LP3 [0]
N14
N16
M5
B1
20
MIPI D-PHY Interface IP
Table 7. Recommended TX Pinout and Package
Signal
MachXO2
1200/2000/4000
cs132bga Package
MachXO3L 2100C
caBGA256 Package
LatticeECP3-150EA
fpBGA1156
ECP5 LFE5U-85F6MG285CES
DCK_p
Bank 0
Bank 0
Bank 6
Bank 6
DCK_n
A7
A4
AJ4
L15
B7
C5
AK4
L16
D0_p
B5
D10
AP5
K17
D0_n
C6
E10
AP6
L18
D1_p
A2
B11
AL4
K16
D1_n
B3
A12
AM4
K15
D2_p
A10
C8
AL5
J18
D2_n
C11
A8
AM5
K18
D3_p
C12
D6
AJ5
J17
D3_n
A12
E7
AJ6
H18
LPCLK [1]
Bank 1
LPCLK [0]
E12
Bank 1
E14
C16
Bank 7
E14
M2
Bank 7
B18
M7
B17
LP0 [1]
E13
N14
M3
A16
LP0 [0]
F12
R16
M9
C16
LP1 [1]
F13
P16
M4
A12
LP1 [0]
F14
N15
N9
C13
LP2 [1]
G12
N16
L4
C12
LP2 [0]
G14
P15
K5
B12
LP3 [1]
G13
M15
L5
C17
LP3 [0]
H12
C16
K6
A17
The IO timing analysis shows the setup and hold time window for the HS data paths. Setup and hold timing is
based on HS clock (DCK) and HS data (D0, D1, D2 and D3) IO.
Table 8. RX IO Timing
Device Family
Speed Grade - 4
MachXO2
Setup (ps)
Hold (ps)
Speed Grade - 5
Setup (ps)
Hold (ps)
Setup (ps)
Speed Grade - 6
Hold (ps)
222
337
222
254
222
183
Device Family
Speed Grade - 5
MachXO3L
Setup (ps)
Hold (ps)
Speed Grade - 6
Setup (ps)
Hold (ps)
254
214
254
203
Device Family
Speed Grade - 6
LatticeECP3
Setup (ps)
Hold (ps)
Speed Grade - 7
Setup (ps)
Hold (ps)
Setup (ps)
Speed Grade - 8
Hold (ps)
535
332
425
332
335
332
Device Family
Speed Grade - 6
ECP5
Setup (ps)
Hold (ps)
Speed Grade - 7
Setup (ps)
Hold (ps)
Setup (ps)
Hold (ps)
237
60
155
60
62
60
21
Speed Grade - 8
MIPI D-PHY Interface IP
Table 9. RX Design Timing
Device Family
Speed Grade - 4
Speed Grade - 5
MachXO2 (LSE)
byte_clk (Mhz)
byte_clk (Mhz)
byte_clk (Mhz)
93.374
101.286
112.08
byte_clk (Mhz)
byte_clk (Mhz)
byte_clk (Mhz)
93.519
102.564
105.208
Device Family
Speed Grade - 5
Speed Grade - 6
MachXO3L
byte_clk (Mhz)
byte_clk (Mhz)
71.291 (LSE)
82.912 (LSE)
89.526 (Synplify)
101.554 (Synplify)
MachXO2 (Syn)
Speed Grade - 6
Device Family
Speed Grade - 6
Speed Grade - 7
Speed Grade - 7
LatticeECP3
byte_clk (Mhz) div2clk (Mhz)
byte_clk (Mhz) div2clk (Mhz)
byte_clk (Mhz) div2clk (Mhz)
153.516
164.826
182.315
282.008
305.998
339.905
Device Family
Speed Grade - 6
Speed Grade - 7
Speed Grade - 8
ECP5
byte_clk (Mhz) div2clk (Mhz)
byte_clk (Mhz) div2clk (Mhz)
byte_clk (Mhz) div2clk (Mhz)
81.679 (LSE)
104.264 (LSE)
122.56 (LSE)
206.398 (LSE)
286.123 (LSE)
341.413 (LSE)
75.890 (Synplify) 195.88 (Synplify) 89.59 (Synplify) 225.93 (Synplify) 117.028 (Synplify) 250.62 (Synplify)
Table 10. TX IO Timing
Device Family
Speed Grade - 4
MachXO2
Setup (ps)
Hold (ps)
Speed Grade - 5
Setup (ps)
Hold (ps)
Speed Grade - 6
Setup (ps)
Hold (ps)
749
298
668
222
508
222
Device Family
Speed Grade - 4
MachXO3L
Setup (ps)
Hold (ps)
Speed Grade - 5
Setup (ps)
Hold (ps)
570
570
455
455
Device Family
Speed Grade - 6
Speed Grade - 7
Speed Grade - 8
LatticeECP3
Setup (ps)
Hold (ps)
Setup (ps)
Hold (ps)
Setup (ps)
Hold (ps)
432
432
370
370
285
285
Device Family
Speed Grade - 6
ECP5
Setup (ps)
Hold (ps)
Speed Grade - 7
Setup (ps)
Hold (ps)
Setup (ps)
Hold (ps)
676 (Synplify)
676 (Synplify)
560 (Synplify)
560 (Synplify)
442 (Synplify)
442 (Synplify)
22
Speed Grade - 8
MIPI D-PHY Interface IP
Table 11. TX Design Timing
Device Family
Speed Grade - 4
Speed Grade - 5
Speed Grade - 6
byte_clk
(Mhz)
bit_clk
(Mhz)
byte_clk
bit_clk_90 (Mhz)
bit_clk
(Mhz)
byte_clk
bit_clk_90 (Mhz)
bit_clk
(Mhz)
bit_clk_90
MachXO2 (LSE)
345.662
262.605
262.605
388
315.060
315.060
436.681
378.215
378.215
MachXO2 (Syn)
345.662
262.605
262.605
388
315.060
315.060
436.681
378.215
378.215
Device Family
Speed Grade - 5
Speed Grade - 5
Speed Grade - 6
bit_clk (Mhz)
bit_clk_90
bit_clk (Mhz)
bit_clk_90
bit_clk (Mhz)
bit_clk_90
MachXO3L (LSE)
262.605
262.605
317.259
317.259
400.0
400.0
MachXO3L (Syn)
262.60
262.60
317.259
317.259
400.0
400.0
Device Family
Speed Grade -6
LatticeECP3
byte_clk div2clk
(Mhz)
(Mhz)
Speed Grade -7
bit_clk
(Mhz)
176.678 183.419 375
Device Family
byte_clk div2clk
bit_clk_90 (Mhz)
(Mhz)
375
Speed Grade -8
bit_clk
(Mhz)
208.333 188.608 420
byte_clk div2clk
bit_clk_90 (Mhz)
(Mhz)
420
bit_clk
(Mhz)
230.309 197.511 500
Speed Grade - 6
Speed Grade - 7
Speed Grade - 8
byte_clk
(Mhz)
byte_clk
(Mhz)
byte_clk
(Mhz)
clkdiv4
bit_clk_90 (Mhz)
ECP5 (LSE)
220.99
312.50
ECP5 (Syn)
235.10
312.0
189.21
clkdiv4
bit_clk_90 (Mhz)
250.627
350.877
252.972
350.877
208.247
bit_clk_90
500
clkdiv4
bit_clk_90 (Mhz)
253.485
400
274.424
400
246.853
Resource Utilization
The resource utilization tables below represent the device usage in various configurations of the D-PHY IP.
Resource utilization was performed on the IP in configurations of 1, 2 and 4 data lanes. For each of these configurations LP mode on the data lanes used was turned on. In addition, HS and LP clock signals were available for
each configuration. For the RX D-PHY reference IP, word alignment and lane alignment was turned on except
where stated otherwise. The alignment module consumes the majority of the resources in the design. If alignment
is unneeded, the number of registers and LUTs used will be significantly reduced
Table 12. RX Resource Utilization
Device Family
Synthesis
Engine
Configuration
MachXO2 1
LSE
1 Data Lanes (LP+HS)
71
94
0
0
1
1
2 Data Lanes (LP+HS)
353
476
0
0
2
1
4 Data Lanes (LP+HS)
697
962
0
0
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
272
348
0
0
4
1
4 Data Lanes (LP+HS),
No Alignment
4
18
0
0
4
1
1 Data Lanes (LP+HS)
71
68
0
0
1
1
2 Data Lanes (LP+HS)
465
422
0
0
2
1
4 Data Lanes (LP+HS)
617
557
0
0
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
272
254
0
0
4
1
4 Data Lanes (LP+HS),
No Alignment
4
18
0
0
4
1
Synplify Pro
Register LUT
23
EBR
Clock
Gearbox Divider
PLL
MIPI D-PHY Interface IP
Device Family
Synthesis
Engine
Configuration
MachXO3L 2
LSE
1 Data Lanes (LP+HS)
71
97
0
0
1
1
2 Data Lanes (LP+HS)
353
491
0
0
2
1
4 Data Lanes (LP+HS)
697
964
0
0
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
272
346
0
0
4
1
4 Data Lanes (LP+HS),
No Alignment
4
18
0
0
4
1
Synplify Pro
LatticeECP3 3
ECP5 4
LSE
Synplify Pro
Register LUT
EBR
Clock
Gearbox Divider
PLL
1 Data Lanes (LP+HS)
71
68
0
0
1
1
2 Data Lanes (LP+HS)
465
422
0
0
2
1
4 Data Lanes (LP+HS)
617
557
0
0
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
272
254
0
0
4
1
4 Data Lanes (LP+HS),
No Alignment
4
18
0
0
4
1
1 Data Lanes (LP+HS)
111
116
2
0
1
1
2 Data Lanes (LP+HS)
337
307
4
0
2
1
4 Data Lanes (LP+HS)
625
555
6
0
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
312
294
2
0
4
1
4 Data Lanes (LP+HS), 
No Alignment
44
65
2
0
4
1
1 Data Lanes (LP+HS)
144
196
1
1
1
1
2 Data Lanes (LP+HS)
490
535
3
1
2
1
4 Data Lanes (LP+HS)
742
672
5
1
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
345
446
1
1
4
1
4 Data Lanes (LP+HS),
No Alignment
77
114
1
1
4
1
1 Data Lanes (LP+HS)
143
166
1
1
1
1
2 Data Lanes (LP+HS)
489
463
3
1
2
1
4 Data Lanes (LP+HS)
741
667
5
1
4
1
4 Data Lanes (LP+HS),
Word Alignment Only
361
385
1
1
4
1
4 Data Lanes (LP+HS),
No Alignment
76
109
1
1
4
1
1. Performance and utilization characteristics are generated using LCMXO2 -1200HC-4MG132C with Lattice Diamond 3.3 design software.
When using this design in a different device, density, speed, or grade, performance and utilization may vary.
2. Performance and utilization characteristics are generated using LCMXO3l -2100C-5BG256C with Lattice Diamond 3.3 design software.
When using this design in a different device, density, speed, or grade, performance and utilization may vary.
3. Performance and utilization characteristics are generated using LFE3-70EA -8FN484C with Lattice Diamond 3.3 design software. When
using this design in a different device, density, speed, or grade, performance and utilization may vary.
4. Performance and utilization characteristics are generated using LFE5U-45F -8MG285C with Lattice Diamond 3.3 design software. When
using this design in a different device, density, speed, or grade, performance and utilization may vary.
24
MIPI D-PHY Interface IP
Table 13. TX Resource Utilization
Device Family
MachXO2 1
Configuration
LSE
Synplify Pro
MachXO3L
2
LSE
Synplify Pro
LatticeECP3
ECP5 4
3
LSE
Synplify Pro
Register
LUT
EBR
PLL
Gearbox
Clock
Divider
1 Data Lanes (LP+HS)
4
9
0
1
2
1
2 Data Lanes (LP+HS)
4
12
0
1
3
1
4 Data Lanes (LP+HS)
4
18
0
1
5
1
1 Data Lanes (LP+HS)
4
9
0
1
2
1
2 Data Lanes (LP+HS)
4
12
0
1
3
1
4 Data Lanes (LP+HS)
4
18
0
1
5
1
1 Data Lanes (LP+HS)
4
9
0
1
2
1
2 Data Lanes (LP+HS)
4
12
0
1
3
1
4 Data Lanes (LP+HS)
4
18
0
1
5
1
1 Data Lanes (LP+HS)
4
9
0
1
2
1
2 Data Lanes (LP+HS)
4
12
0
1
3
1
4 Data Lanes (LP+HS)
4
18
0
1
5
1
1 Data Lanes (LP+HS)
46
57
1
1
2
1
2 Data Lanes (LP+HS)
46
60
1
1
3
1
4 Data Lanes (LP+HS)
46
66
1
1
5
1
1 Data Lanes (LP+HS)
87
113
1
1
2
1
2 Data Lanes (LP+HS)
87
116
1
1
3
1
4 Data Lanes (LP+HS)
87
122
1
1
5
1
1 Data Lanes (LP+HS)
86
105
1
1
2
1
2 Data Lanes (LP+HS)
86
108
1
1
3
1
4 Data Lanes (LP+HS)
86
114
1
1
5
1
1. Performance and utilization characteristics are generated using LCMXO2 -1200HC-4MG132C with Lattice Diamond 3.3 design software.
When using this design in a different device, density, speed, or grade, performance and utilization may vary.
2. Performance and utilization characteristics are generated using LCMXO3l -2100C-5BG256C with Lattice Diamond 3.3 design software.
When using this design in a different device, density, speed, or grade, performance and utilization may vary.
3. Performance and utilization characteristics are generated using LFE3-17EA-8FN484C with Lattice Diamond 3.3 design software. When
using this design in a different device, density, speed, or grade, performance and utilization may vary.
4. Performance and utilization characteristics are generated using LFE5U-85F-6MG285CES with Lattice Diamond 3.3 design software. When
using this design in a different device, density, speed, or grade, performance and utilization may vary.
References
• MIPI Alliance Specification for Camera Serial Interface 2 (CSI2) V1.01
• MIPI Alliance Specification for D-PHY V1.1
Technical Support Assistance
e-mail:
[email protected]
Internet: www.latticesemi.com
25
MIPI D-PHY Interface IP
Revision History
Date
Version
January 2015
1.5
Change Summary
Added support for MachXO3L and ECP5.
Updated Packaged Design section. General update.
Updated Simulation section. Updated Figure 9, Simulation Wizard
Script File Access
Updated Device Pinout and Bank Voltage Requirements section. General update.
Updated the following tables to add support for MachXO3L and ECP5:
— Table 8, RX IO Timing
— Table 9, RX Design Timing
— Table 10, TX IO Timing
— Table 11, TX Design Timing.
Updated Resource Utilization section. Updated the following tables to
add support for MachXO3L and ECP5:
— Table 12, RX Resource Utilization
— Table 13, TX Resource Utilization.
March 2014
01.4
Updated Transmitting Interface section introduction,
Updated Figure 6, Unidirectional Transmit HS Mode Only Implementation. Indicated 70 Ohm resistors.
January 2014
01.3
Updated Figure 5, Unidirectional Transmit HS Mode and Bidirectional
LP Mode Interface Implementation. Changed the 320 Ohm resistor to
330 Ohm.
Updated Figure 6, Unidirectional Transmit HS Mode Only Implementation. Changed the 320 Ohm resistor to 330 Ohm.
August 2013
July 2013
01.1
Updated Table 10, TX IO Timing.
01.2
Updated the Figure 2, Unidirectional Receive HS Mode and Bidirectional LP Mode Interface Implementation.
01.0
Initial release.
26