ECP5™ Family Data Sheet Preliminary DS1044 Version 1.3, August 2015 ECP5 Family Data Sheet Introduction August 2015 Preliminary Data Sheet DS1044 Features Higher Logic Density for Increased System Integration Programmable sysI/O™ Buffer Supports Wide Range of Interfaces • 24K to 84K LUTs • 197 to 365 user programmable I/Os • • • • • • Embedded SERDES • 270 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes • Data Rates 270 Mbps to 3.2 Gbps per channel for all other protocols • Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI. Flexible Device Configuration • • • • • sysDSP™ • Fully cascadable slice architecture • 12 to 160 slices for high performance multiply and accumulate • Powerful 54-bit ALU operations • Time Division Multiplexing MAC Sharing • Rounding and truncation • Each slice supports — Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers — Advanced 18 x 36 MAC and 18 x 18 Multiply- Multiply-Accumulate (MMAC) operations Flexible Memory Resources On-chip termination LVTTL and LVCMOS 33/25/18/15/12 SSTL 18/15 I, II HSUL12 LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS subLVDS and SLVS, MIPI D-PHY input interfaces Shared bank for configuration I/Os SPI boot flash interface Dual-boot images supported Slave SPI TransFR™ I/O for simple field updates Single Event Upset (SEU) Mitigation Support • Soft Error Detect – Embedded hard macro • Soft Error Correction – Without stopping user operation • Soft Error Injection – Emulate SEU event to debug system error handling System Level Support • Up to 3.744 Mbits sysMEM™ Embedded Block RAM (EBR) • 194K to 669K bits distributed RAM • IEEE 1149.1 and IEEE 1532 compliant • Reveal Logic Analyzer • On-chip oscillator for initialization and general use • 1.1 V core power supply sysCLOCK Analog PLLs and DLLs • Four DLLs and four PLLs in LFE5-45 and LFE585; two DLLs and two PLLs in LFE5-25 Pre-Engineered Source Synchronous I/O • • • • DDR registers in I/O cells Dedicated read/write levelling functionality Dedicated gearing logic Source synchronous standards support — ADC/DAC, 7:1 LVDS, XGMII — High Speed ADC/DAC devices • Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mbps data-rate © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1044 Introduction_01.2 Introduction ECP5 Family Data Sheet Table 1-1. ECP5 Family Selection Guide LFE5UM-25 LFE5UM-45 LFE5UM-85 LFE5U-25 LFE5U-45 LUTs (K) Device 24 44 84 24 44 LFE5U-85 84 sysMEM Blocks (18 Kbits) 56 108 208 56 108 208 Embedded Memory (Kbits) 1,008 1944 3744 1,008 1944 3744 Distributed RAM Bits (Kbits) 194 351 669 194 351 669 18 X 18 Multipliers 28 72 156 28 72 156 SERDES (Dual/Channels) 1/2 2/4 2/4 0 0 0 PLLs/DLLs 2/2 4/4 4/4 2/2 4/4 4/4 Packages and SERDES Channels / I/O Combinations 285 csfBGA (10 x 10 mm2, 0.5 mm) 2/118 2/118 2/118 0/118 0/118 0/118 381 caBGA (17 x 17 mm2) 2/197 4/203 4/205 0/197 0/203 0/205 2 554 caBGA (23 x 23 mm ) 4/245 4/259 756 caBGA (27 x 27 mm2) 4/365 0/245 0/259 0/365 Introduction The ECP5 family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40nm technology making the devices suitable for high-volume, high-speed, low-cost applications. The ECP5 device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/Os. The ECP5 device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards. The ECP5 FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous logic implemented in the ECP5 device family supports a broad range of interface standards, including DDR2/3, LPDDR2/3, XGMII and 7:1 LVDS. The ECP5 device family also features high speed SERDES with dedicated PCS functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with pre- and post- cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media. The ECP5 devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bitstream encryption, and TransFR field upgrade features. The Lattice Diamond™ design software allows large complex designs to be efficiently implemented using the ECP5 FPGA family. Synthesis library support for ECP5 devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the ECP5 device. The tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules for the ECP5 family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 ECP5 Family Data Sheet Architecture August 2015 Preliminary Data Sheet DS1044 Architecture Overview Each ECP5 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™ Digital Signal Processing slices, as shown in Figure 2-1. The LFE5-85 devices have three rows of DSP slices, the LFE5-45 devices have two rows and LFE5-25 devices have one. In addition, the LFE5UM devices contain SERDES Duals on the bottom of the device. The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. The ECP5 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18 Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In addition, ECP5 devices contain up to three rows of DSP slices. Each DSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. The ECP5 devices feature up to 4 embedded 3.2 Gbps SERDES (Serializer / Deserializer) channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of two SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a dual DCU (Dual Channel Unit). The functionality of the SERDES/PCS duals can be controlled by SRAM cell settings during device configuration or by registers that are addressable during device operation. The registers in every dual can be programmed via the SERDES Client Interface (SCI). These DCUs (up to two) are located at the bottom of the devices. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the ECP5 devices are arranged in seven banks (eight banks for LFE5-85 devices in caBGA756 and caBGA554 packages), allowing the implementation of a wide variety of I/O standards. One of these banks (Bank 8) is shared with the programming interfaces. 50% of the PIO pairs on the left and right edges of the device can be configured as LVDS transmit pairs, and all pairs on left and right can be configured as LVDS receive pairs. The PIC logic in the left and right banks also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3 and LPDDR3. The ECP5 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the device entering to a known state for predictable system function. Other blocks provided include PLLs, DLLs and configuration functions. The ECP5 architecture provides up to four Delay Locked Loops (DLLs) and up to four Phase Locked Loops (PLLs). The PLL and DLL blocks are located at the corners of each device. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located at the bottom of each device, to the left of the SERDES blocks. Every device in the ECP5 family supports a sysCONFIG™ ports located in that same corner, powered by Vccio8, allowing for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The ECP5 devices use 1.1 V as their core voltage. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1044 Architecture_01.2 Architecture ECP5 Family Data Sheet Figure 2-1. Simplified Block Diagram, LFE5UM-85 Device (Top Level) DLL PLL PLL sysIO Bank 2 sysIO Bank 3 sysMEM Block RAM: 18 kbit EBRs DLL sysIO Bank 1 sysIO Bank 7 Enhanced DSP Slices: Multiply, Accumulate, and ALU sysIO Bank 0 sysIO Bank 6 sysCLOCK PLLs: Frequency synthesis and balanced PCLK tress sysCLOCK DLLs: Accurate phase alignments Pre-engineered Source Synchronous Support: DDR3, LPDDR3 – 800 Mbps Generic – Up to 800 Mbps Flexible sysIO (Bank 4 is on LFE5-85 only): LVCMOS, SSTL, HSUL, LVDS Flexible Routing: Optimized for speed, power and routability Programmable Functional Units: Up to 84K LUTs SERDES DCU0 PLL DLL SERDES DCU1 sysConfig, JTAG & On-Chip Oscillator sysIO Bank 8 DCU0 DCU0 Channel 0 Channel 1 DCU1 DCU1 Channel 0 Channel 1 PLL sysIO Bank 4 3.2 Gbps SERDES Dual Function sysIO Pins: Shared I/Os for sysConfig Note: There is no Bank 4 in LFE5-25 and LFE5-45. There are no PLL and DLL on the top corners in LFE5-25. 2-2 DLL Architecture ECP5 Family Data Sheet PFU Blocks The core of the ECP5 device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2-2. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM functions. Table 2-1 shows the functions each slice can perform in either mode. Figure 2-2. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 LUT4 & CARRY Slice 1 D FF LUT4 & CARRY D FF D FF LUT4 & CARRY LUT4 & CARRY Slice 3 Slice 2 D D FF FF LUT4 & CARRY D FF D FF D FF To Routing Slice Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 through Slice 2 are configured as distributed memory, and Slice 3 is used as Logic or ROM. Table 2-1 shows the capability of the slices along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select and wider RAM/ROM functions. Table 2-1. Resources and Modes Available per Slice PFU (Used in Distributed SRAM) PFU (Not used as Distributed SRAM) Slice Resources Modes Resources Modes Slice 0 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 1 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 2 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 3 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. Each slice has 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/ PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7 and LUT8. Table 2-2 and Figure 2-3 list the signals associated with all the slices. Figure 2-4 shows the connectivity of the inter-slice/PFU signals that support LUT5, LUT6, LUT7 and LUT8. 2-3 Architecture ECP5 Family Data Sheet Figure 2-3. Slice Diagram FCO FXA FXB M1 M0 A1 B1 C1 D1 LUT4 & CARRY* F1 F1 FF Q1 A0 B0 C0 D0 LUT4 & CARRY* F0 F0 FF Q0 CE CLK LSR FCI From Different Slice/PFU Notes: For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 WAD [A:D] is a 4-bit address from slice 2 LUT input 2-4 Architecture ECP5 Family Data Sheet Figure 2-4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 Q1 F0 LUT5 Q0 F1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA LUT6 Q1 F0 LUT5 Q0 Q0 F1 LUT7 Q1 F0 LUT5 Q0 F1 LUT6 Q1 F0 LUT5 Q0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA 3 SLICE Q1 F0 LUT5 Q0 LUT7 Output From Previous PFU LUT6 2 F1 SLICE 3 SLICE 2 F0 LUT5 LUT8 Q1 F0 LUT5 Q0 F1 LUT7 1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA LUT7 1 F1 Q1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F1 SLICE Q0 LUT6 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 F0 LUT5 Q0 F1 LUT6 0 F0 LUT5 F1 SLICE SLICE Q1 F0 LUT5 1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA LUT6 2 F1 Q1 Q0 SLICE Q0 LUT8 0 3 SLICE F0 LUT5 PFU Col(n+1) F1 SLICE A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA Q1 SLICE A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA F1 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA LUT8 0 A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA PFU Col(n) SLICE LUT7 Output To Next PFU A1 B1 C1 D1 A0 B0 C0 D0 FXB FXA SLICE PFU Col(n-1) Q1 F0 LUT5 Q0 Table 2-2. Slice Signal Descriptions Function Type Signal Names Data signal A0, B0, C0, D0 Input Data signal A1, B1, C1, D1 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Description Inputs to LUT4 Inputs to LUT4 Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry-in1 Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT82 Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT82 Data signals F0, F1 Output Data signals Q0, Q1 Output Inter-PFU signal FCO Output LUT4 output register bypass signals Register outputs Fast carry chain output1 1. See Figure 2-3 for connection details. 2. Requires two adjacent PFUs. 2-5 Architecture ECP5 Family Data Sheet Modes of Operation Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 is not needed for RAM mode, it can be used in Logic, Ripple, or ROM modes. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note that LUT8 requires more than four slices. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: • Addition 2-bit • Subtraction 2-bit • Add/Subtract 2-bit using dynamic control • Up counter 2-bit • Down counter 2-bit • Up/Down counter with asynchronous clear • Up/Down counter with preload (sync) • Ripple mode multiplier building block • Multiplier support • Comparator functions of A and B inputs — A greater-than-or-equal-to B — A not-equal-to B — A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 x 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. A 16 x 2-bit pseudo dual port RAM (PDPR) memory is created in one PFU by using one Slice as the read-write port and the other companion slice as the read-only port. The slice with the read-write port updates the SRAM data contents in both slices at the same write cycle. ECP5 devices support distributed memory initialization. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in ECP5 devices, please see TN1264, ECP5 Memory Usage Guide. 2-6 Architecture ECP5 Family Data Sheet Table 2-3. Number of Slices Required to Implement Distributed RAM Number of slices SPR 16 X 4 PDPR 16 X 4 3 6 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. For more information, please refer to TN1264, ECP5 Memory Usage Guide. Routing There are many resources provided in the ECP5 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The ECP5 family has an enhanced routing architecture that produces a compact design. The Diamond design software tool suites take the output of the synthesis tool and places and routes the design. CLOCKING STRUCTURE ECP5 clocking structure consists of clock synthesis blocks, sysCLOCK PLL; balanced clock tress networks, PCLK and ECLK trees; and efficient clock logic modules, CLOCK DIVIDER and Dynamic Clock Select (DCS), Dynamic Clock Control (DCC), and DLL. Each of these functions is described as follow. sysCLOCK PLL The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the ECP5 family support two to four full-featured General Purpose PLLs. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The architecture of the PLL is shown in Figure 2-5. A description of the PLL functionality follows. CLKI is the reference frequency input to the PLL and its source can come from two different external CLK inputs or from internal routing. A non-glitchless 2-to-1 input multiplexor is provided to dynamically select between two different external reference clock sources. The CLKI input feeds into the input Clock Divider block. CLKFB is the feedback signal to the PLL which can come from internal feedback path, routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. The PLL has four clock outputs CLKOP, CLKOS, CLKOS2 and CLKOS3. Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the primary clock network. Only CLKOP and CLKOS outputs can go to the edge clock network. The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically using the PHASESEL, PHASEDIR, PHASESTEP, and PHASELOADREG ports. The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. 2-7 Architecture ECP5 Family Data Sheet Figure 2-5. General Purpose PLL Diagram PHASESEL[1: 0] PHASEDIR PHASESTEP PHASELOADREG PLLREFCS Dynamic Phase Adjust SEL CLKOP Divider (1-128) CLKOP CLKOS Divider (1-128) CLKOS VCO CLKOS2 Divider (1-128) CLKOS2 VCO CLKOS3 Divider (1-128) CLKOS3 VCO Refclk CLK0 PLLCSOUT CLKI CLKI2 Refclk Divider M CLKI CLK1 Phase Detector, VCO, and Loop Filter VCO FBKSEL CLKFB Feedback Clock Divider Internal Feedback CLKOP, CLKOS, CLKOS2, CLKOS3 ENCLKOP ENCLKOS ENCLKOS2 ENCLKOS3 RST STDBY Lock Detect LOCK Table 2-4 provides a description of the signals in the PLL blocks. Table 2-4. PLL Blocks Signal Descriptions Signal I/O Description CLKI I Clock Input to PLL from external pin or routing CLKI2 I Muxed clock input to PLL SEL I Input Clock select, selecting from CLKI and CLKI2 inputs CLKFB I PLL Feedback Clock Select which output to be adjusted on Phase by PHASEDIR, PHASESTEP, PHASELODREG PHASESEL[1:0] I PHASEDIR I Dynamic Phase adjustment direction. PHASESTEP I Dynamic Phase adjustment step. PHASELOADREG I Load dynamic phase adjustment values into PLL. CLKOP O Primary PLL output clock (with phase shift adjustment) CLKOS O Secondary PLL output clock (with phase shift adjust) CLKOS2 O Secondary PLL output clock2 (with phase shift adjust) CLKOS3 O Secondary PLL output clock3 (with phase shift adjust) LOCK O PLL LOCK to CLKI, Asynchronous signal. Active high indicates PLL lock STDBY I Standby signal to power down the PLL RST I Resets the PLL ENCLKOP I Enable PLL output CLKOP ENCLKOS I Enable PLL output CLKOS ENCLKOS2 I Enable PLL output CLKOS2 ENCLKOS3 I Enable PLL output CLKOS3 For more details on the PLL you can refer to the TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide. 2-8 Architecture ECP5 Family Data Sheet Clock Distribution Network There are two main clock distribution networks for any member of the ECP5 product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks have the clock sources come from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, SERDES/PCS clocks and some on chip generated clock signal. There are clock dividers (CLKDIV) blocks to provide the slower clock from these clock sources. ECP5 also supports glitch-less dynamic enable function (DCC) for the PCLK Clock to save dynamic power. There are also some logics to allow dynamic glitch-less selection between two clocks for the PCLK network (DCS). Overview of Clocking Network is shown in Figure 2-6, for LFE5UM-85 device. Figure 2-6. LFE5UM-85 Clocking PIO Edge Clocks Quadrant TL Primary Clocks 12 Primary Sources 16 Fabric Entry 14 14 DCC Center MUX 16 Quadrant BL PLL Primary Clocks Quadrant BR 16 DCC PLL Mid MUX Bank 8 PCSCLKDIV PCSCLKDIV SERDES DCU0 SERDES DCU1 CLK DIV CLK DIV Edge Clocks 16 Primary Sources Mid MUX Bank 3 Fabric Entry 14 PIO Fabric Entry Primary Clocks DLL Quadrant TR 14 Primary Sources 14 Primary Sources 14 DCC PIO Mid MUX 16 Fabric Entry Primary Clocks PIO PIO PIO Bank 7 PLL 12 DCC PIO PIO DLL PIO Bank 6 Bank 1 PLL 16 Edge Clocks PIO Bank 2 CLK DIV PIO Mid MUX Edge Clocks CLK DIV PIO Bank 0 DLL DLL Bank 4 Primary Clocks The ECP5 device family provides low-skew, high fanout clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. The primary clock network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL), Top Right (TR), and Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric in the quadrant. The Lattice Diamond software can automatically route each clock to one of the four quadrants up to a maximum of 16 clocks per quadrant. The user can change how the clocks are routed by specifying a preference in the Lattice Diamond software to locate the clock to specific. The ECP5 device provides the user with a maximum of 64 unique clock input sources that can be routed to the primary Clock network. Primary clock sources are: • Dedicated clock input pins • PLL outputs • CLKDIV outputs • Internal FPGA fabric entries (with minimum general routing) • SERDES/PCS/PCSDIV clocks • OSC clock 2-9 Architecture ECP5 Family Data Sheet These sources are routed to one of four clock switches called a Mid Mux. The outputs of the Mid MUX are routed to the center of the FPGA where another clock switch, called the Center MUX, is used to route the primary clock sources to primary clock distribution to the ECP5 fabric. These routing muxes are shown in Figure 2-6. Since there is a maximum of 60 unique clock input sources to the clocking quadrants, there are potentially 64 unique clock domains that can be used in the ECP5 Device. For more information about the primary clock tree and connections, please see TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide. Dynamic Clock Control (DCC) The DCC (Quadrant Clock Enable/Disable) feature allows internal logic control of the quadrant primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by that clock will not toggle, reducing the overall power consumption of the device. The disable function will not create glitch and increase the clock latency to the primary clock network. This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the quadrant clock network. For more information about the DCC, please see TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide. Dynamic Clock Select (DCS) The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources. Depending on the operation modes, it switches between two (2) independent input clock sources either with or without any glitches. This is achieved regardless of when the select signal is toggled. Both input clocks must be running to achieve functioning glitch-less DCS output clock, but it is not required running clocks when used as non-glitch-less normal clock multiplexer. There are two DCS blocks per device that are fed to all quadrants. The inputs to the DCS block come from all the output of MIDMUXs and Clock from CIB located at the center of the PLC array core. The output of the DCS is connected to one of the inputs of Primary Clock Center MUX. See Figure 2-7 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, please see TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide. Figure 2-7. DCS Waveforms CLK0 CLK1 SEL CLKO 2-10 Architecture ECP5 Family Data Sheet Edge Clock ECP5 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are two ECLK networks per bank IO on the Left and Right sides of the devices. Each Edge Clock can be sourced from the following: • Dedicated Clock input pins (PCLK) • DLLDEL output (Clock delayed by 90o) • PLL outputs (CLKOP and CLKOS) • ECLKBRIDGE • Internal Nodes Figure 2-8. Edge Clock Sources Per Bank From ECLK of other bank on same side Top Left / Right PCLK Pin Top Left / Right DLLDEL Output Top Right / Left PLL CLKOP From ECLKBRIDGE Top Right / Left PLL CLKOS ECLK Tree ECLKSYNC Bottom Right / Left PLL CLKOP Bottom Right / Left PLL CLKOS Bottom Left / Right PCLK Pin To ECLK of other bank on same side Bottom Left / Right DLLDEL Output To ECLKBRIDGE to go to other side From Routing The edge clocks have low injection delay and low skew. They are used for DDR Memory or Generic DDR interfaces. For detailed information on Edge Clock connections, please see TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide. Clock Dividers ECP5 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The clock dividers can be fed from selected PLL outputs, external primary clock pins multiplexed with the DDRDEL Slave Delay or from routing. The clock divider outputs serve as primary clock sources and feed into the clock distribution network. The Reset (RST) control signal resets input and asynchronously forces all outputs to low. The SLIP signal slips the outputs one cycle relative to the input clock. For further information on clock dividers, please see TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide. Figure 2-9 shows the clock divider connections. 2-11 Architecture ECP5 Family Data Sheet Figure 2-9. ECP5 Clock Divider Sources Primary Clock Pin OR DLLDEL output clock PLL clock output (CLKOP/CLKOS) CLKDIV (/2 or /3.5) Primary Clock Tree OR Routing To Primary Clock Tree OR Routing RST SLIP DDRDLL Every DDRDLL (master DLL block) can generate phase shift code representing the amount of delay in a delay block that corresponding to 90 degree phase of the reference clock input. The reference clock can be either from PLL, or input pin. This code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave DLL). There are 2 DDRDLLs that supply two sets of codes (for two different reference clock frequencies) to each side of the I/Os (at each of the corners). The DQSBUF uses this code to controls the DQS input of the DDR memory to 90 degree shift to clock DQs at the center of the data eye for DDR memory interface. The code is also sent to another slave DLL, DLLDEL, that takes a clock input, and generates a 90 degree shift clock output to drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90 degree clocking needs to be created. Figure 2-10 shows DDRDLL functional diagram. Figure 2-10. DDRDLL Functional Diagram CLK DDRDEL RST LOCK DDRDLL DCNTL [7:0] UDDCNTLN FREEZE Table 2-5. DDRDLL Ports List Port Name I/O Description CLK I Reference clock input to the DDRDLL. Should run at the same frequency as the clock to the delayed. RST I Reset Input to the DDRDLL UDDCNTLN I Update Control to update the delay code. When low the delay code out the DDRDLL is updated. Should not be active during a read or a write cycle FREEZE I FREEZE goes high and, without a glitch, turns off the DLL internal clock and the ring oscillator output clock. When FREEZE goes low, it turns them back on. DDRDEL O The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL LOCK O Lock output to indicate the DDRDLL has valid delay output DCNTL [7:0] O The delay codes from the DDRDLL available for the user IP. There are four identical DDRDLLs, one in each of the four corners in LFE5-85 and LFE5-45 devices, and two DDRDLLs in LFE5-25 devices in the upper two corners. Each DDRDLL can generate delay code based on the reference frequency. The slave DLL (DQSBUF and DLLDEL) use the code to delay the signal, to create the phase shifted signal used for either DDR memory, or creating 90 degree shift clock. Figure 2-11 shows the DDRDLL and the slave DLLs on the top level view. 2-12 Architecture ECP5 Family Data Sheet Figure 2-11. ECP5 DLL Top Level View (For LFE-45 and LFE-85) ASICIO Buffer ASICIO Buffer DDRDLL DDRDLL PIC PIC PIC PIC PIC PIC PIC PIC DLLDEL sysIO Buffer DLLDEL sysIO Buffer DLLDEL DQSBUF PIC DQSBUF DQSBUF sysIO Buffer PIC DLLDEL LFE5 Device DQSBUF sysIO Buffer DLLDEL DLLDEL PIC PIC PIC PIC PIC PIC Config IO DDRDLL SERDES Block DDRDLL sysMEM Memory ECP5 devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-Kbit RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and FIFO buffers (via external PFUs). sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by implementing support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more information, please see TN1264, ECP5 Memory Usage Guide. 2-13 Architecture ECP5 Family Data Sheet Table 2-6. sysMEM Block Configurations Memory Mode Configurations 16,384 x 1 8,192 x 2 4,096 x 4 Single Port 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 4,096 x 4 True Dual Port 2,048 x 9 1,024 x 18 16,384 x 1 8,192 x 2 4,096 x 4 Pseudo Dual Port 2,048 x 9 1,024 x 18 512 x 36 Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. EBR memory supports the following forms of write behavior for single port or dual port operation: • Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. • Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. • Read-Before-Write – When new data is written, the old content of the address appears at the output. This mode is supported for x9, x18, and x36 data widths. 2-14 Architecture ECP5 Family Data Sheet Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in Figure 2-12. Figure 2-12. Memory Core Reset Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information on the sysMEM EBR block, please see the list of technical documentation at the end of this data sheet. sysDSP™ Slice The ECP5 family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks such as multiplyadders and multiply-accumulators. sysDSP Slice Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the ECP5 device family, there are many DSP slices that can be used to support different data widths. This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2-13 compares the fully serial implementation to the mixed parallel and serial implementation. 2-15 Architecture ECP5 Family Data Sheet Figure 2-13. Comparison of General DSP and ECP5 Approaches Operand A Operand A Operand B Operand A Single Multiplier Operand A Operand B Operand B Operand B x M loops x Multiplier 0 x x Multiplier 1 m/k loops Multiplier k Accumulator (k adds) Function Implemented in General Purpose DSP + m/k accumulate Output Function Implemented in ECP5 ECP5 sysDSP Slice Architecture Features The ECP5 sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization. The ECP5 sysDSP Slice supports many functions that include the following: • Fully double data rate support - Higher operation frequency (throughput of up to 370 Mbps) is achieved by double input and output interfaces that enable twice the fabric operation throughput for most of the operation modes. • Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x. — Odd mode – Filter with Odd number of taps — Even mode – Filter with Even number of taps — Two dimensional (2D) symmetry mode – supports 2D filters for mainly video applications • Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture • Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters. • Multiply (one 18x36, two 18x18 or four 9x9 Multiplies per Slice) • Multiply (36x36 by cascading across two sysDSP slices) • Multiply Accumulate (supports one 18x36 multiplier result accumulation or two 18x18 multiplier result accumulation) • Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18x18 Multiplies feed into an accumulator that can accumulate up to 52 bits) • Pipeline registers 2-16 Architecture ECP5 Family Data Sheet • 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics. — Odd mode – Filter with Odd number of taps — Even mode – Filter with Even number of taps • 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics. — 3*3 and 3*5 – Internal DSP Slice support — 5*5 and larger size 2D blocks – Semi internal DSP Slice support • Flexible saturation and rounding options to satisfy a diverse set of applications situations • Flexible cascading across DSP slices — Minimizes fabric use for common DSP and ALU functions — Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only — Provides matching pipeline registers — Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains • Flexible and Powerful Arithmetic Logic Unit (ALU) Supports: — Dynamically selectable ALU OPCODE — Ternary arithmetic (addition/subtraction of three inputs) — Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR) — Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such as, overflow, underflow and convergent rounding, etc. — Flexible cascading across slices to get larger functions • RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users • Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require processor-like flexibility that enables different functions for each clock cycle For most cases, as shown in Figure 2-14, the ECP5 sysDSP slice is backwards-compatible with the LatticeECP2™ and LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to the ECP5 sysDSP slice. Figure 2-14 shows the Diagram of the sysDSP, and Figure 2-15 shows the detailed diagram. 2-17 Architecture ECP5 Family Data Sheet Figure 2-14. Simplified sysDSP Slice Block Diagram ALU24 ALU24 PR0 (36) PR1 (36) PR2 (36) PR3 (36) 9x9 9x9 Mult18-1 9x9 Mult18-2 9x9 9x9 Mult18-1 36x36 (Mult36) In Reg B 1 9+/-9 9+/-9 In Reg A 1 In Reg B 0 In Reg B 1 9+/-9 18+/-18 MUA1[17:0] MUB0[17:0] MUA0[17:0] 18+/-18 9+/-9 In Reg A 0 9+/-9 9+/-9 18+/-18 MUA2[17:0] 9+/-9 Casc A0 2-18 Casc A1 9+/-9 18+/-18 MUB3[17:0] In Reg A 1 In Reg B 0 MUA3[17:0] In Reg A 0 MUB1[17:0] 18 COUT[53:0] (hardwired cascade to right DSP) Flags[7:0] SIGNEDA[3:0] SIGNEDB[3:0] SOURCEA[3:0] SOURCEB[3:0] GSR MUB2[17:0] 18 18 18 One of these Mult18-0 9x9 C0[53:0] 9x9 One of these ALU24 One of these OutB3 (18) OutA3 (18) MUP3[17:0] MUP2[35:18] OutB2 (18) OutA2 (18) MUP2[17:0] MUP1[35:18] OutA1 (18) OutB1 (18) Accumulator/ALU (54) ALU24 9x9 C0[53:0] SRIA[17:0] SRIB[17:0] Hardwired from DSP Block on Left MUP1[17:0] MUP0[35:18] Accumulator/ALU (54) CLK[3:0] CE[3:0] RST[3:0] DYNOP0[10:0], DYNOP1[10:0] OutB0 (18) MUP0[17:0] OutA0 (18) CIN[53:0] (hardwired cascade from left DSP) MUP3[35:18] SLICE 1 SLICE 0 SROA[17:0] SROB[17:0] To DSP Block on Right and to CIB Outputs Architecture ECP5 Family Data Sheet Figure 2-15. Detailed sysDSP Slice Diagram MUIA0 MUIB0 INT_A OPCODE_PA MUIA1 MUIB1 INT_B IR INT_B SRIBK_PA IR IR IR IR +/= DSP PreAdder Logic +/- OPA0 C INT_A DYNOP OPA1 SROA SRIA IR IR IR IR SRIB IR MULTA SROB MULTB IR IR PR PR PR B ALU A ALU 0 0 Shift 18L AMUX R= A ± B ± C R = Logic (B, C) CMUX C_ALU CIN BMUX COUT ALU == OR OR FR OR DSP Core Logic MUOP0 R FLAGS MUOP1 DSP SLICE In Figure 2-15, note that A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB, BA BB and C inputs. For further information, please refer to TN1267, ECP5 sysDSP Usage Guide. The ECP5 sysDSP block supports the following basic elements. • MULT (Multiply) • MAC (Multiply, Accumulate) • MULTADDSUB (Multiply, Addition/Subtraction) • MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation) Table 2-7 shows the capabilities of each of the ECP5 slices versus the above functions. 2-19 Architecture ECP5 Family Data Sheet Table 2-7. Maximum Number of Elements in a Slice Width of Multiply x9 x18 x36 MULT 4 2 1/2 MAC 1 1 — MULTADDSUB 2 1 — MULTADDSUBSUM 11 1/2 — 1. One slice can implement 1/2 9x9 m9x9addsubsum and two m9x9addsubsum with two slices. Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following operations are possible: • In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle. • The loading of operands can switch between parallel and serial operations. For further information, please refer to TN1267, ECP5 sysDSP Usage Guide. Programmable I/O Cells (PIC) The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysIO buffers and pads. On the ECP5 devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. On all the ECP5 devices, two adjacent PIOs can be combined to provide a complementary output driver pair. All PIO pairs can implement differential receivers. Half of the PIO pairs on the left and right edges of these devices can be configured as true LVDS transmit pairs. 2-20 Architecture ECP5 Family Data Sheet Figure 2-16. Group of Four Programmable I/O Cells on Left/Right Sides 1 PIC PIO A Input Register Block Output and Tristate Register Block Pin A PIO B Input Register Block Input Gearbox Output Gearbox Core Logic / Routing Output and Tristate Register Block Pin B PIO C Input Register Block Output and Tristate Register Block Pin C PIO D Input Register Block Output and Tristate Register Block 2-21 Pin D Architecture ECP5 Family Data Sheet PIO The PIO contains three blocks: an input register block, output register block and tristate register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Input Register Block The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition the input register blocks for the PIOs on the left and right edges include built-in FIFO logic to interface to DDR and LPDDR memory. The Input register block on the right and left sides includes gearing logic and registers to implement IDDRX1, IDDRX2 functions. With two PICs sharing the DDR register path, it can also implement IDDRX71 function used for 7:1 LVDS interfaces. It uses three sets of registers -- shift, update, and transfer to implement gearing and the clock domain transfer. The first stage registers samples the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. The Top side of the device will support IDDRX1 gearing function. For more information on gearing function, refer to TN1265, ECP5 High-Speed I/O Interface. Figure 2-17 shows the input register block for the PIOs on the top edge. Figure 2-17. Input Register Block for PIO on Top Side of the Device D INCK INFF Programmable Delay Cell Q INFF IDDRX1 SCLK RST Q[1:0] Figure 2-18 shows the input register block for the PIOs located on the left and right edges. Figure 2-18. Input Register Block for PIO on Left and Right Side of the Device D INCK INFF Programmable Delay Cell Q INFF FIFO Delayed DQS ECLK Generic IDDRX1 IDDRX2 IDDRX71* Memory IDDRX2 ECLK SCLK RST ALIGNWD *For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D). 2-22 Q[1:0]/ Q[3:0]/ Q[6:0]* Architecture ECP5 Family Data Sheet Input FIFO The ECP5 PIO has dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write side of the FIFO, it is clocked by DQS clock which is the delayed version of the DQS Strobe signal from DDR memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high speed clock with identical frequency as DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointer to every PIC in same DQS group. DQS Grouping and DQS Control Block is described in DDR memory Support section below. Table 2-8. Input Block Port Description Name D Type Input Q[1:0]/Q[3:0]/Q[6:0] RST Output Input Description High Speed Data Input Low Speed Data to the device core Reset to the Output Block SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQS Input Clock from DQS control Block used to clock DDR memory data ALIGNWD Input Data Alignment signal from device core. Output Register Block The output register block registers signals from the core of the device before they are passed to the sysIO buffers. ECP5 output data path has output programmable flip flops and output gearing logic. On the left and right sides the output register block can support 1x, 2x and 7:1 gearing enabling high speed DDR interfaces and DDR memory interfaces. On the top side, the banks will support 1x gearing. ECP5 output data path diagram is shown in Figure 219. The programmable delay cells are also available in the output data path. For detailed description of the output register block modes and usage, you can refer to TN1265, ECP5 High-Speed I/O Interface. Figure 2-19. Output Register Block on Top Side Programmable Delay Cell D OUTFF RST SCLK D[1:0] Generic ODDRX1 2-23 Q Architecture ECP5 Family Data Sheet Figure 2-20. Output Register Block on Left and Right Sides Programmable Delay Cell D OUTFF RST SCLK Q Generic ODDRX1/ ODDRX2/ ODDR71* ECLK DQSW DQSW270 Memory ODDRX2 OSHX2 D[1:0]/ D[3:0]/ D[6:0]* *For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B. Table 2-9. Output Block Port Description Name Type Description Q Output D Input High Speed Data Output Data from core to output SDR register D[1:0]/D[3:0]/ D[6:0] Input Low Speed Data from device core to output DDR register RST Input Reset to the Output Block SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQSW Input Clock from DQS control Block used to generate DDR memory DQS output DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output Tristate Register Block The tristate register block registers tristate control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. In DDR operation used mainly for DDR memory interface can be implemented on the left and right sides of the device. Here 2 inputs feed the tristate registers clocked by both ECLK and SCLK. Figure 2-20 and Figure 2-21 show the Tristate Register Block functions on the device. For detailed description of the tristate register block modes and usage, you can refer to TN1265, ECP5 High-Speed I/O Interface. Figure 2-21. Tristate Register Block on Top Side TQ TD RST SCLK TSFF 2-24 Architecture ECP5 Family Data Sheet Figure 2-22. Tristate Register Block on Left and Right Sides TQ TD TSFF RST SCLK ECLK DQSW THSX2 DQSW270 T[1:0] Table 2-10. Tristate Block Port Description Name Type Description TD Input Tristate Input to Tristate SDR Register RST Input Reset to the Tristate Block TD[1:0] Input Tristate input to TSHX2 function SCLK Input Slow Speed System Clock ECLK Input High Speed Edge Clock DQSW Input Clock from DQS control Block used to generate DDR memory DQS output DQSW270 TQ Input Output Clock from DQS control Block used to generate DDR memory DQ output Output of the Tristate block DDR Memory Support DQS Grouping for DDR Memory Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR2, DDR3, LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below. The left and right sides of the PIC have fully functional elements supporting DDR2, DDR3, LPDDR2 or LPDDR3 memory interfaces. Every 16 PIOs on the left and right sides are grouped into one DQS group, as shown in Figure 2-23. Within each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as "virtual" VCCIO, by driving these pins to HIGH, with the user connecting these pins to VCCIO power supply. These connections create "soft" connections to VCCIO thru these output pins, and make better connections on VCCIO to help to reduce SSO noise. For more details, please refer to TN1265, ECP5 High-Speed I/O Interface. 2-25 Architecture ECP5 Family Data Sheet Figure 2-23. DQS Grouping on the Left and Right Edges DQS PIO A sysIO Buffer Pad A (T) PIO B sysIO Buffer Pad B (C) PIO C sysIO Buffer Pad C PIO D sysIO Buffer Pad D PIO A sysIO Buffer Pad A (T) PIO B sysIO Buffer Pad B (C) PIO C sysIO Buffer Pad C PIO D sysIO Buffer Pad D DQSBUF Delay PIO A sysIO Buffer Pad A (T) PIO B sysIO Buffer Pad B (C) PIO C sysIO Buffer Pad C PIO D sysIO Buffer Pad D PIO A sysIO Buffer Pad A (T) PIO B sysIO Buffer Pad B (C) PIO C sysIO Buffer Pad C PIO D sysIO Buffer Pad D DLL Calibrated DQS Delay and Control Block (DQSBUF) To support DDR memory interfaces (DDR2/3, LPDDR2/3), the DQS strobe signal from the memory must be used to capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shifted is achieved by using DQSDEL programmable delay line in the DQS Delay Block (DQS read circuit). The DQSDEL is implemented as a slave delay line and works in conjunction with a master DDRDLL. This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling feature for DDR write if needed. Each of the read and write side delays can be dynamically shifted using margin control signals that can be controlled by the core logic. FIFO Control Block include here generates the Read and Write Pointers for the FIFO block inside the Input Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module. 2-26 Architecture ECP5 Family Data Sheet Figure 2-24. DQS Control and Delay Block (DQSBUF) DQS BURSTDET Preamble/Postamble Management & Burst Detect READ[1:0] DATAVALID READCLKSEL[1:0] ECLK RDPNTR[2:0] FIFO Control & Datavalid Generation SCLK DQSDEL (90 Deg. Delay Code from DDRDLL) WRPNTR[2:0] Read Side Slave Delay with Dynamic Margin Control RDLOADN, RDMOVE, RDDIRECTION DQSR90 (Read Side) (Read Side Dynamic Margin Control) DQSW (Write Side) WRLOADN, WRMOVE, WRDIRECTION DQSW270 (Write Side) Write Side Slave Delay with Dynamic Margin Control (Write Side Dynamic Margin Control) RDCFLAG WRCFLAG PAUSE DYNDELAY[7:0] Write Leveling (Write Leveling delay) Table 2-11. DQSBUF Port list description Name DQS Type Input Description DDR memory DQS strobe READ[1:0] Input Read Input from DDR Controller READCLKSEL[1:0] Input Read pulse selection SCLK Input Slow System Clock ECLK Input High Speed Edge Clock (same frequency as DDR memory) DQSDEL Input 90 Deg Delay Code from DDRDLL RDLOADN, RDMOVE, RDDIRECTION Input Dynamic Margin Control ports for Read delay WRLOADN, WRMOVE, WRDIRECTION Input Dynamic Margin Control ports for Write delay PAUSE Input Used by DDR Controller to Pause write side signals during DDRDLL Code update or Write Leveling DYNDELAY[7:0] Input Dynamic Write Leveling Delay Control DQSR90 Output 90 delay DQS used for Read DQSW270 Output 90 delay clock used for DQ Write DQSW Output Clock used for DQS Write RDPNTR[2:0] Output Read Pointer for IFIFO module WRPNTR[2:0] Output Write Pointer for IFIFO module DATAVALID Output Signal indicating start of valid data BURSTDET Output Burst Detect indicator RDFLAG Output Read Dynamic Margin Control output to indicate max value WRFLAG Output Write Dynamic Margin Control output to indicate max value 2-27 Architecture ECP5 Family Data Sheet sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today’s systems including LVDS, HSUL, BLVDS, SSTL Class I and II, LVCMOS, LVTTL, LVPECL, and MIPI. sysI/O Buffer Banks ECP5 devices have seven sysI/O buffer banks, two banks per side at Top, Left and Right, plus one at the bottom left side. The bottom left side bank (Bank 8) is a shared I/O bank. The I/Os in that bank contains both dedicated and shared I/O for sysConfig function. When a shared pin is not used for configuration, It is available as a user I/O. For LFE5-85 devices, there is an additional I/O bank (Bank 4) that is not available in other device in the family. In ECP5 devices, the Left and Right sides are tailored to support high performance interfaces, such as DDR2, DDR3, LPDDR2, LPDDR3 and other high speed source synchronous standards. The banks on the Left and Right sides of the devices feature LVDS input and output buffers, data-width gearing, and DQSBUF block to support DDR2/3 and LPDDR2/3 interfaces. The I/Os on the top and bottom banks do not have LVDS input and output buffer, and gearing logic, but can use LVCMOS to emulate most of differential output signaling. Each sysIO bank has its own I/O supply voltage (VCCIO). In addition, the banks on the Left and Right sides of the device, have voltage reference input (shared I/O pin), VREF1 per bank, which allow it to be completely independent of each other. The VREF voltage is used to set the threshold for the referenced input buffers, such as SSTL. Figure 2-25 shows the seven banks and their associated supplies. In ECP5 devices, single-ended output buffers and ratioed input buffers (LVTTL, and LVCMOS) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs independent of VCCIO. 2-28 Architecture ECP5 Family Data Sheet Figure 2-25. ECP5 Device Family Banks TOP VREF1(1)V VCCIO1 GND VREF1(0)V VCCIO0 GND Bank 0 Bank 1 VREF1(7) Bank 7 Bank 2 VCCIO7 GND VREF1(6) GND Bank 6 GND Bank 3 VCCIO6 VREF1(2) RIGHT LEFT GND VCCIO2 Bank 8 CONFIG BANK VCCIO3 VREF1(3) Bank 41 SERDES GND VCCIO4 GND VCCIO8 1. Only 85K device has this bank. BOTTOM ECP5 devices contain two types of sysI/O buffer pairs. • Top (Bank 0 and Bank 1) and Bottom (Bank 8 and Bank 4) sysIO Buffer Pairs (Single-Ended Only) The sysI/O buffers in the Banks at top and bottom of the device consist of ratioed single-ended output drivers and single-ended input buffers. The I/Os in these banks are not usually used as a pair, except when used as emulated differential output pair. They are used as individual I/Os and be configured as different I/O modes, as long as they are compatible with the VCCIO voltage in the bank. When used as emulated differential outputs, the pair can be used together. The top and bottom side IOs also support hot socketing. They support IO standards from 3.3 V to 1.2 V. They are ideal for general purpose I/Os, or as ADDR/CMD bus for DDR2/DDR3 applications, or for used as emulated differential signaling. 2-29 Architecture ECP5 Family Data Sheet Bank 4 I/O only exists in the LFE5-85 device. Bank 8 is a bottom bank that shares with sysConfig I/Os. During configuration, these I/Os are used for programming the device. Once the configuration is completed, these I/Os can be released and user can use these I/Os for functional signals in his design. The top and bottom side pads can be identified by the Lattice Diamond tool. • Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Outputs) The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two single-ended input buffers (both ratioed and referenced) and half of the sysI/O buffer pairs (PIOA/B pairs) also has a high-speed differential output driver. One of the referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O pins located on the left and right side of the device as the PCI clamp is always enabled on these pins. LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks. Typical sysI/O I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in ECP5 devices, see the list of technical documentation at the end of this data sheet. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Supported sysI/O Standards The ECP5 sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V, 1.5V, 1.8 V, 2.5 V and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, slew rates, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSUL. Differential standards supported include LVDS, differential SSTL and differential HSUL. For further information on utilizing the sysI/O buffer to support a variety of standards, please see TN1262, ECP5 sysIO Usage Guide. 2-30 Architecture ECP5 Family Data Sheet On-Chip Programmable Termination The ECP5 devices support a variety of programmable on-chip terminations options, including: • Dynamically switchable Single-Ended Termination with programmable resistor values of 50, 75, or 150 Ohms. • Common mode termination of 100 Ohms for differential inputs Figure 2-26. On-Chip Termination Zo = 50 VCCIO Zo = 50, 75, or 150 Ohms to VCCIO /2 TERM control Zo Zo + 2Zo Zo + - VREF OFF-chip - Zo OFF-chip ON-chip ON-chip Differential Input Parallel Single-Ended Input See Table 2-12 for termination options for input modes. Table 2-12. On-Chip Termination Options for Input Modes TERMINATE to VCCIO/21 DIFFERENTIAL TERMINATION RESISTOR1 LVDS25 — 100 BLVDS25 — 100 MLVDS — 100 LVPECL33 — 100 subLVDS — 100 IO_TYPE SLVS HSUL12 HSUL12D SSTL135_I / II SSTL135D_I / II SSTL15_I / II SSTL15D_I / II SSTL18_I / II SSTL18D_I / II — 100 50, 75, 150 — — 100 50, 75, 150 — — 100 50, 75, 150 — — 100 50, 75, 150 — — 100 1. TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only left and right banks have this feature. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance +/- 20%. Please see TN1262, ECP5 sysIO Usage Guide for on-chip termination usage and value ranges. Hot Socketing ECP5 devices have been carefully designed to ensure predictable behavior during power-up and power- down. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. Please refer to the Hot Socketing Specifications in the DC and Switching Characteristics in this data sheet. 2-31 Architecture ECP5 Family Data Sheet SERDES and PCS (Physical Coding Sublayer) LFE5UM devices feature up to 4 channels of embedded SERDES/PCS arranged in dual-channel blocks at the bottom of the devices. Each channel supports up to 3.2 Gbps data rate. Figure 2-27 shows the position of the dual blocks for the LFE5-85. Table 2-13 shows the location of available SERDES Duals for all devices. The LFE5UM SERDES/PCS supports a range of popular serial protocols, including: • PCI Express Gen1 and Gen2 (2.5 Gbps) • Ethernet (XAUI, GbE - 1000 Base CS/SX/LX and SGMII) • SMPTE SDI (3G-SDI, HD-SDI, SD-SDI) • CPRI (E.6.LV: 614.4 Mbps, E.12.LV: 1228.8 Mbps, E.24.V: 2457.6 Mbps, E.30.LV: 3072 Mbps) • JESD204A/B – ADC and DAC converter interface: 312.5 Mbps to 3.125 Gbps Each dual contains two dedicated SERDES for high speed, full duplex serial data transfer. Each dual also has a PCS block that interfaces to the SERDES channels and contains protocol specific digital logic to support the standards listed above. The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated protocol support can also be bypassed to allow raw 8-bit or 10-bit interfaces to the FPGA fabric. Even though the SERDES/PCS blocks are arranged in duals, multiple baud rates can be supported within a dual with the use of dedicated, per channel /1, /2 and /11 rate dividers. Additionally, two duals can be arranged together to form x4 channel link. When a SERDES Dual in a 2-Dual device is not used, the power VCCA power supply for that Dual should be connected. It is advised to connect the VCCA of unused channel to core if the user knows he will not use the Dual at all, or it should be connected to a different regulated 1.1 V supply, if that Dual maybe used in the future. For an unused channel in a Dual, it is advised to connect the VCCHTX to VCCA, and user can leave VCCHRX unconnected. For information on how to use the SERDES/PCS blocks to support specific protocols, as well on how to combine multiple protocols and baud rates within a device, please refer to TN1261, ECP5 SERDES/PCS Usage Guide. 2-32 Architecture ECP5 Family Data Sheet Figure 2-27. SERDES/PCS Duals (LFE5UM-85) sysIO Bank 3 sysIO Bank 6 sysIO Bank 2 sysIO Bank 1 sysIO Bank 7 sysIO Bank 0 CH1 CH0 sysIO Bank 8 SERDES/PCS Dual 1 CH1 CH0 SERDES/PCS Dual 0 sysIO Bank 4 Table 2-13. LFE5UM SERDES Standard Support Standard PCI Express 1.1 and 2.0 Data Rate (Mbps) Number of General/Link Width Encoding Style 2500 x1, x2, x4 8b10b Gigabit Ethernet 1250 x1 8b10b SGMII 1250 x1 8b10b XAUI 3125 x4 8b10b 614.4 1228.8 2457.6 3072.0 x1 8b10b 270 x1 NRZI/Scrambled HD-SDI (292M) 1483.5 1485 x1 NRZI/Scrambled 3G-SDI (424M) 2967, 2970 x1 NRZI/Scrambled JESD204A/B 3125 x1 8b/10b CPRI-1 CPRI-2 CPRI-3 CPRI-4 SD-SDI (259M, 344M)1 1. For slower rates, the SERDES are bypassed and CML signals are directly connected to the FPGA routing. 2-33 Architecture ECP5 Family Data Sheet Table 2-14. Available SERDES Duals per LFE5UM Devices Package LFE5UM-25 LFE5UM-45 LFE5UM-85 285 csfBGA 1 1 1 381 caBGA 1 2 2 554 caBGA — 2 2 756 caBGA — — 2 SERDES Block A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream through the differential drivers. Figure 2-28 shows a single-channel SERDES/PCS block. Each SERDES channel provides a recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic. Each transmit channel, receiver channel, and SERDES PLL shares the same power supply (VCCA). The output and input buffers of each channel have their own independent power supplies (VCCHTX and VCCHRX). Figure 2-28. Simplified Channel Block Diagram for SERDES/PCS Block SERDES PCS FPGA Core Recovered Clock* RX_REFCLK HDINP Equalizer HDINN Recovered Clock Clock/Data Recovery Receiver TX REFCLK CTC FIFO Word Alignment 8b1/0b Decoder Downsample FIFO Bypass Bypass Receive Data Receive Clock TX PLL (Per Dual) SERDES Tx Clock Serializer 8:1/10:1 HDOUTN Polarity Adjust Bypass De-emphasis Tx Driver HDOUTP Deserializer 1:8/1:10 Polarity Adjust 8b/10b Encoder Upsample FIFO Bypass Bypass Transmit Data Transmit Clock * 1/8 or 1/10 line rate PCS As shown in Figure 2-28, the PCS receives the parallel digital data from the deserializer and selects the polarity, performs word alignment, decodes (8b/10b), provides Clock Tolerance Compensation and transfers the clock domain from the recovered clock to the FPGA clock via the Down Sample FIFO. For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b, selects the polarity and passes the 8/10 bit data to the transmit SERDES channel. The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. The PCS interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Some of the enhancements in LFE5UM SERDES/PCS include: • Higher clock/channel granularity: Dual channel architecture provides more clock resource per channel. • Enhanced Tx de-emphasis: Programmable pre- and post- cursors improves Tx output signaling • Bit-slip function in PCS: Improves logic needed to perform Word Alignment function 2-34 Architecture ECP5 Family Data Sheet Please refer to TN1261, ECP5 SERDES/PCS Usage Guide for more information. SCI (SERDES Client Interface) Bus The SERDES Client Interface (SCI) is an IP interface that allows the user to change the configuration thru this interface. This is useful when the user needs to fine-tune some settings, such as input and output buffer that need to be optimized based on the channel characteristics. It is a simple register configuration interface that allows SERDES/PCS configuration without power cycling the device. The Diamond design tools support all modes of the PCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow users to define their own operation. With these tools, the user can define the mode for each dual in a design. Popular standards such as 10Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP (available through Lattice), with two duals (Four SERDES channels and PCS) and some additional logic from the core. The LFE5UM devices support a wide range of protocols. Within the same dual, the LFE5UM devices support mixed protocols with semi-independent clocking as long as the required clock frequencies are integer x1, x2, or x11 multiples of each other. Table 2-15 lists the allowable combination of primary and secondary protocol combinations. Flexible Dual SERDES Architecture The LFE5UM SERDES architecture is a dual channel-based architecture. For most SERDES settings and standards, the whole dual (consisting of two SERDES channels) is treated as a unit. This helps in silicon area savings, better utilization, higher granularity on clock/SERDES channel and overall lower cost. However, for some specific standards, the LFE5UM dual-channel architecture provides flexibility; more than one standard can be supported within the same dual. Table 2-15 shows the standards that can be mixed and matched within the same dual. In general, the SERDES standards whose nominal data rates are either the same or a defined subset of each other, can be supported within the same dual. In Table 2-15, the two Protocol columns define the different combinations of protocols that can be implemented together within a Dual. Table 2-15. LFE5UM Mixed Protocol Support Protocol PCI Express 1.1 Protocol with SGMII PCI Express 1.1 with Gigabit Ethernet CPRI-3 with CPRI-2 and CPRI-1 3G-SDI with HD-SDI and SD-SDI There are some restrictions to be aware of when using spread spectrum clocking. When a dual shares a PCI Express x1 channel with a non-PCI Express channel, ensure that the reference clock for the dual is compatible with all protocols within the dual. For example, a PCI Express spread spectrum reference clock is not compatible with most Gigabit Ethernet applications because of tight CTC ppm requirements. While the LFE5UM architecture will allow the mixing of a PCI Express channel and a Gigabit Ethernet, or SGMII channel within the same dual, using a PCI Express spread spectrum clocking as the transmit reference clock will cause a violation of the Gigabit Ethernet, and SGMII transmit jitter specifications. For further information on SERDES, please see TN1261, ECP5 SERDES/PCS Usage Guide. 2-35 Architecture ECP5 Family Data Sheet IEEE 1149.1-Compliant Boundary Scan Testability All ECP5 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port uses VCCIO8 for power supply. For more information, please see TN1260, ECP5 sysCONFIG Usage Guide. Device Configuration All ECP5 devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In- System Configuration specification. There are 11 dedicated pins for TAP and sysConfig supports (TDI, TDO, TCK, TMS, CFG[2:0], PROGRAMN, DONE, INITN and CCLK). The remaining sysCONFIG pins are used as dual function pins. See TN1260, ECP5 sysCONFIG Usage Guide for more information about using the dual-use pins as general purpose I/Os. There are various ways to configure a ECP5 device: • JTAG • Standard Serial Peripheral Interface (SPI) - interface to boot PROM Support x1, x2, x4 wide SPI memory interfaces. • System microprocessor to drive a x8 CPU port SPCM mode • System microprocessor to drive a serial slave SPI port (SSPI mode) • Slave Serial model (SCM) On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. ECP5 devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device (slave mode) with the SPI port of the FPGA to perform read-write operations. Enhanced Configuration Options ECP5 devices have enhanced configuration features such as: decryption support, decompression support, TransFR™ I/O and dual-boot and multi-boot image support. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology for details. Dual-Boot and Multi-Boot Image Support Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the ECP5 devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the ECP5 device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, please see TN1260, ECP5 sysCONFIG Usage Guide. 2-36 Architecture ECP5 Family Data Sheet Single Event Upset (SEU) Support ECP5 devices support SEU mitigation with three supporting functions: • SED – Soft Error Detect • SEC – Soft Error Correction • SEI – Soft Error Injection ECP5 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, the ECP5 device can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM. The SED operation can be run in the background during user mode. If a soft error occurs, during user mode (normal operation) the device can be programmed to generate an error signal. When an error is detected, and the user's error handling software determines the error did not create any risk to the system operation, the SEC tool allows the device to be re-configured in the background to correct the affected bit. This operation allows the user functions to continue to operate without stopping the system function. Additional SEI tool is also available in the Diamond Software, by creating a frame of data to be programmed into the device in the background with one bit changed, without stopping the user functions on the device. This emulates an SEU situation, allowing the user to test and monitor its error handling software. For further information on SED support, please see TN1184, LatticeECP3 and ECP5 Soft Error Detection (SED)/ Correction (SEC) Usage Guide. On-Chip Oscillator Every ECP5 device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for configuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is completed. The software default value of the MCLK is nominally 2.4 MHz. Table 2-16 lists all the available MCLK frequencies. When a different Master Clock is selected during the design process, the following sequence takes place: 1. Device powers up with a nominal Master Clock frequency of 2.4 MHz. 2. During configuration, users select a different master clock frequency. 3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received. 4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.4 MHz. This internal oscillator is available to the user by routing it as an input clock to the clock tree. For further information on the use of this oscillator for configuration or user mode, please see TN1260, ECP5 sysCONFIG Usage Guide. Table 2-16. Selectable Master Clock (MCLK) Frequencies During Configuration (Nominal) MCLK Frequency (MHz) 2.4 4.8 9.7 19.4 38.8 62 2-37 Architecture ECP5 Family Data Sheet Density Shifting The ECP5 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likelihood of success in each case. An example is that some user I/Os may become No Connects in smaller devices in the same package. Refer to the ECP5 Pin Migration Tables and Diamond software for specific restrictions and limitations. 2-38 ECP5 Family Data Sheet DC and Switching Characteristics August 2015 Preliminary Data Sheet DS1044 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC, VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.21 V Supply Voltage VCCAUX, VCCAUXA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.75 V Supply Voltage VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.63 V Input or I/O Transient Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.63 V SERDES RX/TX Buffer Supply Voltages VCCHRX, VCCHTX . . . . . . . . . . . . . . . . . . –0.5 V to 1.32 V Voltage Applied on Serdes Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.7 V Storage Temperature (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 150 °C Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125 °C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. Recommended Operating Conditions1 Symbol Min. Max. Units Core Supply Voltage 1.045 1.155 V VCCAUX Auxiliary Supply Voltage 2.375 2.625 V VCCIO2, 3 I/O Driver Supply Voltage 1.14 3.465 V VREF1 Input Reference Voltage 0.5 1.0 V tJCOM Junction Temperature, Commercial Operation 0 85 °C tJIND Junction Temperature, Industrial Operation –40 100 °C VCC 2 2, 4 Parameter 5 SERDES External Power Supply VCCA SERDES Analog Power Supply 1.045 1.155 V VCCAUXA SERDES Auxiliary Supply Voltage 2.374 2.625 V VCCHRX6 SERDES Input Buffer Power Supply 0.30 1.155 V VCCHTX SERDES Output Buffer Power Supply 1.045 1.155 V 1. 2. 3. 4. 5. 6. For correct operation, all supplies except VREF must be held in their valid operation range. This is true independent of feature usage. All supplies with same voltage, except Serdes Power Supplies, should be connected together. See recommended voltages by I/O standard in subsequent table. VCCAUX ramp rate must not exceed 30 mV/µs during power-up when transitioning between 0 V and 3 V. See TN1261, ECP5 SERDES/PCS Usage Guide for information on board considerations for SERDES power supplies. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin input voltage level requirements specified in the Rx section of this Data Sheet. Power Supply Ramp Rates1 Symbol tRAMP Parameter Min Typ. Max. Units Power Supply ramp rates for all supplies 0.01 — 10 V/ms 1. Assumes monotonic ramp rates. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1044 DC and Switching_01.2 DC and Switching Characteristics ECP5 Family Data Sheet Power-On-Reset Voltage Levels1, 2, 3 Symbol VPORUP VPORDN Parameter All Devices All Devices Min Typ. Max. Units Power-On-Reset ramp-up VCC trip point (Monitoring VCC, V CCAUX VCCAUX, and VCCIO8) VCCIO8 0.90 — 1.00 V 2.00 — 2.20 V 0.95 — 1.06 V Power-On-Reset rampdown trip point (Monitoring VCC, and VCCAUX VCC 0.77 — 0.87 V VCCAUX 1.80 — 2.00 V 1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 2. Only VCCIO8 has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection. 3. VCCIO8 does not have a Power-On-Reset ramp down detection. VCCIO8 must remain within the Recommended Operating Conditions to ensure proper operation. Power Up Sequence POR (Power-On-Reset puts the ECP5 device in a reset state. POR is released when VCC, VCCAUX, and VCCIO8 are ramped above the VPORUP voltage, as specified above. VCCIO8 controls the voltage on the configuration I/O pins. If the ECP5 device is using Master SPI mode to download configuration data from external SPI Flash, it is required to ramp VCCIO8 above VIH of the external SPI Flash, before at least one of the other two supplies (VCC and/or VCCAUX) is ramped to VPORUP voltage level. If the system cannot meet this Power Up Sequence requirement, and requires the VCCIO8 to be ramped last, then the system must keep either PROGRAMN or INITN pin LOW during power up, until VCCIO8 reaches VIH of the external SPI Flash. This ensures the signals driven out on the configuration pins to the external SPI Flash meet the VIH voltage requirement of the SPI Flash. For LFE5UM devices, it is required to power up VCCAUXA, before the VCCA/VCCHRX/VCCHTX are powered up. Hot Socketing Specifications1, 2, 3, 4 Symbol Parameter Condition IDK_HS Input or I/O Leakage Current for Top and Bottom Banks Only IDK Input or I/O Leakage Current 0 VIN < VCCIO for Left and Right Banks Only VCCIO VIN VCCIO + 0.5V 1. 2. 3. 4. 0 VIN VIH (Max.) Min. Typ. Max. Units — — +/–1 mA — — +/–1 mA — 18 — mA VCC, VCCAUX and VCCIO should rise/fall monotonically. IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only. Hot socket specification defines when the hot socketed device's junction temperature is at 85 oC or below. When the hot socketed device's junction temperature is above 85 oC, the IDK current can exceed +/–1 mA. 3-2 DC and Switching Characteristics ECP5 Family Data Sheet Hot Socketing Requirements Description Min. Typ. Max. Units Input current per SERDES I/O pin when device is powered down and inputs driven. — — 8 mA Input current per HDIN pin when device power supply is off, inputs driven 1, 2 — — 15 mA — — 50 mA — — 30 mA Current per HDIN pin when device power ramps up, input driven 3 Current per HDOUT pin when device power supply is off, outputs pulled up 4 1. Device is powered down with all supplies grounded, both HDINP and HDINN inputs driven by a CML driver with maximum allowed output (VCCHTX = 1.155 V)), 8b/10b data, no external AC coupling. 2. Each P and N input must have less than the specified maximum input current during hot plug. For a device with 2 DCU, the total input current would be 15 mA * 4 channels * 2 input pins per channel = 120 mA. 3. Device power supplies are ramping up (VCCA and VCCAUX), both HDINP and HDINN inputs are driven by a CML driver with maximum allowed output (VCCHTX=1.155 V), 8b/10b data, internal AC coupling. 4. Device is powered down with all supplies grounded. Both HDOUTP and HDOUN outputs are pulled up to 1.26 V by the far end receiver termination of 50 Ω single ended. ESD Performance Please refer to the ECP5 Product Family Qualification Summary for complete qualification data, including ESD performance. DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter IIL, IIH1, 4 Input or I/O Low Leakage Condition 0 VIN VCCIO Input or I/O High Leakage VCCIO < VIN VIH(MAX) IPU I/O Active Pull-up Current 0 VIN 0.7 VCCIO IPD I/O Active Pull-down Current C1 IIH 1, 3 Min. Typ. Max. Units — — 10 µA — — 100 µA –30 — –150 µA VIL (MAX) VIN VCCIO 30 — 150 µA I/O Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH (MAX) — 5 8 pf C2 Dedicated Input Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = 1.2 V, VIO = 0 to VIH (MAX) — 5 7 pf VHYST Hysteresis for Single-Ended Inputs VCCIO = 3.3 V — 300 — mV VCCIO = 2.5 V — 250 — mV 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25 oC, f = 1.0 MHz. 3. Applicable to general purpose I/Os in top and bottom banks. 4. When used as VREF, maximum leakage= 25 µA. 3-3 DC and Switching Characteristics ECP5 Family Data Sheet ECP5 Supply Current (Standby)1, 2, 3, 4, 5, 6 Over Recommended Operating Conditions Symbol ICC ICCAUX ICCIO ICCA 1. 2. 3. 4. 5. 6. Parameter Core Power Supply Current Auxiliary Power Supply Current Bank Power Supply Current (Per Bank) SERDES Power Supply Current (Per Dual) Device Typical Units LFE5-25 80 mA LFE5-45 110 mA LFE5-85 200 mA LFE5-25 13 mA LFE5-45 15 mA LFE5-85 20 mA LFE5-25 0.5 mA LFE5-45 0.5 mA LFE5-85 0.5 mA LFE5-25 8 mA LFE5-45 8 mA LFE5-85 8 mA For further information on supply current, please see the list of technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0 Hz. Pattern represents a “blank” configuration data file. TJ = 85 °C, power supplies at nominal voltage. To determine the ECP5 peak start-up current, please use the Power Calculator tool in the Lattice Diamond Design Software. 3-4 DC and Switching Characteristics ECP5 Family Data Sheet SERDES Power Supply Requirements1, 2, 3 Over Recommended Operating Conditions Symbol Description Typ. Max. Units Standby (Power Down) ICCA-SB VCCA Power Supply Current (Per Channel) 4 10 mA ICCHRX-SB4 VCCHRX, Input Buffer Current (Per Channel) — 0.1 mA ICCHTX-SB VCCHTX, Output Buffer Current (Per Channel) — 0.9 mA Operating (Data Rate = 3.2 Gbps) ICCA-OP VCCA Power Supply Current (Per Channel) 48 54 mA ICCHRX-OP5 VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) 10 13 mA VCCA Power Supply Current (Per Channel) 42 47 mA ICCHRX-OP VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) 10 13 mA mA Operating (Data Rate = 2.5 Gbps) ICCA-OP 5 Operating (Data Rate = 1.25 Gbps) ICCA-OP VCCA Power Supply Current (Per Channel) 34 37 ICCHRX-OP5 VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) 10 13 mA Operating (Data Rate = 270 Mbps) ICCA-OP VCCA Power Supply Current (Per Channel) 27 29 mA ICCHRX-OP5 VCCHRX, Input Buffer Current (Per Channel) 0.4 0.5 mA ICCHTX-OP VCCHTX, Output Buffer Current (Per Channel) 8 10 mA 1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled 2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on current will be higher. 3. To calculate with Tx De-emphasis enabled, please refer to the Diamond Power Calculator tool. 4. For ICCHRX-SB, during Standby, input termination on Rx are disabled. 5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is based on current pulled down by external driver when the input is driven to LOW. 3-5 DC and Switching Characteristics ECP5 Family Data Sheet sysI/O Recommended Operating Conditions4 Standard VCCIO VREF (V) Min. Typ. Max. Min. Typ. Max. LVCMOS33 3.135 3.3 3.465 — — — LVCMOS33D3 Output 3.135 3.3 3.465 — — — LVCMOS25 2.375 2.5 2.625 — — — LVCMOS18 1.71 1.8 1.89 — — — 1.425 1.5 1.575 — — — 1 1 LVCMOS15 1 LVCMOS12 1.14 1.2 1.26 — — — LVTTL331 3.135 3.3 3.465 — — — 1.43 1.5 1.57 0.68 0.75 0.9 1.89 0.833 0.9 0.969 SSTL15_I, _II 2 SSTL18_I, _II 2 1.71 1.8 SSTL135_I, _II2 1.28 1.35 1.42 0.6 0.675 0.75 HSUL122 1.14 1.2 1.26 0.588 0.6 0.612 MIPI D-PHY LP Input3 1.425 1.5 1.575 — — — LVDS251, 3 Output 2.375 2.5 2.625 — — — — — — — — — SLVS (Input only) — — — — — — LVDS25E3 Output 2.375 2.5 2.625 — — — MLVDS3 Output 2.375 2.5 2.625 — — — subLVS3 (Input only) 3 LVPECL331, 3 Output 3.135 3.3 3.465 — — — BLVDS251, 3 Output 2.375 2.5 2.625 — — — HSULD12D2, 3 1.14 1.2 1.26 — — — SSTL135D_I, II 2, 3 1.28 1.35 1.42 — — — SSTL15D_I, II2, 3 1.43 1.5 1.57 — — — SSTL18D_I1, 2, 3, II1, 2, 3 1.71 1.8 1.89 — — — 1. 2. 3. 4. For input voltage compatibility, see TN1262, ECP5 sysIO Usage Guide. VREF is required when using Differential SSTL and HSUL to interface to DDR/LPDDR memories. These differential inputs use LVDS input comparator, which uses VCCAUX power All differential inputs and LVDS25 output are supported in the Left and Right banks only. Please refer to TN1262, ECP5 sysIO Usage Guide for details. 3-6 DC and Switching Characteristics ECP5 Family Data Sheet sysI/O Single-Ended DC Electrical Characteristics1, 2 Input/Output Standard VIH VIL Min. (V) Max. (V) Min. (V) Max. (V) VOL Max. (V) LVCMOS33 –0.3 0.8 2.0 3.465 0.4 LVCMOS25 LVCMOS12 –0.3 –0.3 –0.3 –0.3 LVTTL33 –0.3 SSTL18_I (DDR2 Memory) –0.3 SSTL18_II –0.3 SSTL15 _I (DDR3 Memory) –0.3 VREF – 0.1 SSTL15_II (DDR3 Memory) –0.3 SSTL135_I (DDR3L Memory) VOH Min. (V) VCCIO – 0.4 IOL1 (mA) IOH1 (mA) –16, –12, –8, –4 12, 8, 4 –12, –8, –4 12, 8, 4 –12, –8, –4 8, 4 –8, –4 8, 4 –8, –4 –16, –12, 16, 12, 8, 4 –8, –4 16, 12, 8, 4 0.7 1.7 3.465 0.4 VCCIO – 0.4 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 0.35 VCCIO 0.65 VCCIO 3.465 0.4 VCCIO – 0.4 0.8 2.0 3.465 0.4 VCCIO – 0.4 VREF – 0.125 VREF + 0.125 3.465 0.4 VCCIO – 0.4 6.7 –6.7 VREF – 0.125 VREF + 0.125 3.465 0.28 VCCIO – 0.28 13.4 –13.4 VREF + 0.1 3.465 0.31 VCCIO – 0.31 7.5 –7.5 VREF – 0.1 VREF + 0.1 3.465 0.31 VCCIO – 0.31 8.8 –8.8 –0.3 VREF – 0.09 VREF + 0.09 3.465 0.27 VCCIO – 0.27 7 –7 SSTL135_II (DDR3L Memory) –0.3 VREF – 0.09 VREF + 0.09 3.465 0.27 VCCIO – 0.27 8 –8 MIPI D-PHY (LP) –0.3 0.55 0.88 3.465 — — — — HSUL12 (LPDDR2/3 Memory) –0.3 VREF – 0.1 VREF + 0.1 3.465 0.3 4 –4 LVCMOS18 LVCMOS15 VCCIO – 0.3 1. For electromigration, the average DC current drawn by the I/O pads within a bank of I/Os shall not exceed 10 mA per I/O (All I/Os used in the same VCCIO). 2. Not all IO types are supported in all banks. Please refer to TN1262, ECP5 sysIO Usage Guide for details. 3-7 DC and Switching Characteristics ECP5 Family Data Sheet sysI/O Differential Electrical Characteristics LVDS1 Over Recommended Operating Conditions Parameter Description Test Conditions VINP , VINM Input Voltage VCM Input Common Mode Voltage VTHD Differential Input Threshold Difference Between the Two Inputs IIN Input Current Power On or Power Off VOH Output High Voltage for VOP or VOM RT = 100 Ohm VOL Half the Sum of the Two Inputs Output Low Voltage for VOP or VOM RT = 100 Ohm VOD Output Voltage Differential (VOP - VOM), RT = 100 Ohm VOD Change in VOD Between High and Low VOS Output Voltage Offset VOS Change in VOS Between H and L ISAB Output Short Circuit Current (VOP + VOM)/2, RT = 100 Ohm VOD = 0 V Driver Outputs Shorted to Each Other Min. Typ. Max. Units 0 — 2.4 V 0.05 — 2.35 V +/–100 — — mV — — +/–10 µA — 1.38 1.60 V 0.9 V 1.03 — V 250 350 450 mV — — 50 mV 1.125 1.20 1.375 V — — 50 mV — — 12 mA 1, On the left and right sides of the device, this specification is valid only for VCCIO = 2.5 V or 3.3 V. SSTLD All differential SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. LVCMOS33D All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3 V VCCIO. The default drive current for LVCMOS33D output is 12 mA with the option to change the device strength to 4 mA, 8 mA, 12 mA or 16 mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. 3-8 DC and Switching Characteristics ECP5 Family Data Sheet LVDS25E The top and bottom sides of ECP5 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5 V (±5%)` RS=158 Ohms (±1%) 8 mA VCCIO = 2.5 V (±5%) RS=158 Ohms (±1%) RP = 140 Ohms (±1%) + – RT = 100 Ohms (±1%) 8 mA Transmission line, Zo = 100 Ohm differential OFF-chip ON-chip ON-chip OFF-chip Table 3-1. LVDS25E DC Conditions Parameter Description Typical Units 2.50 V Driver Impedance 20 Driver Series Resistor (+/–1%) 158 VCCIO Output Driver Supply (+/–5%) ZOUT RS RP Driver Parallel Resistor (+/–1%) 140 RT Receiver Termination (+/–1%) 100 VOH Output High Voltage 1.43 V VOL Output Low Voltage 1.07 V VOD Output Differential Voltage 0.35 V VCM Output Common Mode Voltage 1.25 V ZBACK Back Impedance 100.5 IDC DC Output Current 6.03 mA 3-9 DC and Switching Characteristics ECP5 Family Data Sheet BLVDS25 The ECP5 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multidrop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS25 Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 Ohms differential 2.5 V RS = 90 Ohms RS = 90 Ohms 16 mA 2.5 V 16 mA 45-90 Ohms 45-90 Ohms RTL RTR 2.5 V 2.5 V 16 mA 16 mA RS = 90 Ohms RS = 90 Ohms 2.5 V 16 mA + + – 2.5 V RS = 90 Ohms ... – 16 mA RS = 90 Ohms + – 2.5 V + RS = 90 Ohms RS = 90 Ohms 2.5 V 16 mA – 16 mA Table 3-2. BLVDS25 DC Conditions1 Over Recommended Operating Conditions Typical Parameter Description Zo = 45 Zo = 90 Units VCCIO Output Driver Supply (+/– 5%) 2.50 2.50 V ZOUT Driver Impedance 10.00 10.00 RS Driver Series Resistor (+/– 1%) 90.00 90.00 RTL Driver Parallel Resistor (+/– 1%) 45.00 90.00 RTR Receiver Termination (+/– 1%) 45.00 90.00 VOH Output High Voltage 1.38 1.48 V VOL Output Low Voltage 1.12 1.02 V VOD Output Differential Voltage 0.25 0.46 V VCM Output Common Mode Voltage 1.25 1.25 V IDC DC Output Current 11.24 10.20 mA 1. For input buffer, see LVDS table. 3-10 DC and Switching Characteristics ECP5 Family Data Sheet LVPECL33 The ECP5 devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for pointto-point signals. Figure 3-3. Differential LVPECL33 VCCIO = 3.3 V (+/–5%) RS = 93.1 Ohms (+/–1%) 16 mA VCCIO = 3.3 V (+/–5%) RP = 196 Ohms (+/–1%) RS = 93.1 Ohms (+/–1%) 16 mA On-chip + RT = 100 Ohms (+/–1%) – Transmission line, Zo = 100 Ohm differential Off-chip Off-chip On-chip Table 3-3. LVPECL33 DC Conditions1 Over Recommended Operating Conditions Parameter Description VCCIO Output Driver Supply (+/–5%) ZOUT Driver Impedance Typical Units 3.30 V 10 RS Driver Series Resistor (+/–1%) 93 RP Driver Parallel Resistor (+/–1%) 196 RT Receiver Termination (+/–1%) 100 VOH Output High Voltage 2.05 V VOL Output Low Voltage 1.25 V VOD Output Differential Voltage 0.80 V VCM Output Common Mode Voltage 1.65 V ZBACK Back Impedance 100.5 IDC DC Output Current 12.11 mA 1. For input buffer, see LVDS table. 3-11 DC and Switching Characteristics ECP5 Family Data Sheet MLVDS25 The ECP5 devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for MLVDS standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. MLVDS25 (Multipoint Low Voltage Differential Signaling) Heavily loaded backplace, effective Zo~50 to 70 Ohms differential 2.5 V RS = 35 Ohms RS = 35 Ohms 2.5 V 16 mA 16 mA OE 50 to 70 Ohms +/–1% RTL 50 to 70 Ohms +/–1% OE RTR 2.5 V 2.5 V 16 mA OE RS = 35 Ohms RS = 35 Ohms 16 mA RS = 35 Ohms RS = 35 Ohms RS = 35 Ohms OE RS = 35 Ohms + –- OE 2.5 V OE OE 2.5 V 16 mA 16 mA 16 mA – 2.5 V 16 mA + OE + 2.5 V – + – Table 3-4. MLVDS25 DC Conditions1 Typical Parameter Description Zo=50 Zo=70 Units VCCIO Output Driver Supply (+/–5%) 2.50 2.50 V ZOUT Driver Impedance 10.00 10.00 RS Driver Series Resistor (+/–1%) 35.00 35.00 RTL Driver Parallel Resistor (+/–1%) 50.00 70.00 RTR Receiver Termination (+/–1%) 50.00 70.00 VOH Output High Voltage 1.52 1.60 V VOL Output Low Voltage 0.98 0.90 V VOD Output Differential Voltage 0.54 0.70 V VCM Output Common Mode Voltage 1.25 1.25 V IDC DC Output Current 21.74 20.00 mA 1. For input buffer, see LVDS table. 3-12 DC and Switching Characteristics ECP5 Family Data Sheet SLVS Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard and relies on the advantage of its use of smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power. The ECP5 devices can receive differential input up to 800 Mbps with its LVDS input buffer. This LVDS input buffer is used to meet the SLVS input standard specified by the JEDEC standard. The SLVS output parameters are compared to ECP5 LVDS input parameters, as listed in Table 3-5: Table 3-5. Input to SLVS Parameter ECP5 LVDS Input SLVS Output Units Vcm (min) 50 150 mV Vcm (max) 2350 250 mV Differential Voltage (min) 100 140 mV Differential Voltage (max) — 270 mV ECP5 does not support SLVS output. However, SLVS output can be created using ECP5 LVDS outputs by level shift to meet the low Vcm/Vod levels required by SLVS. Figure 3-5 shows how the LVDS output can be shifted external to meet SLVS levels. Figure 3-5. SLVS Interface 2.5 V Typical R1=220 R2=47 LVDS + - R3=15 100-Ohm Diff Z0=50 SLVDS + – R2=47 R1=220 ECP5 2.5 V Typical On Chip LVDS + – - Z0=50 3-13 R3=15 SLVDS Peer On Chip + -– DC and Switching Characteristics ECP5 Family Data Sheet Typical Building Block Function Performance Pin-to-Pin Performance1, 2, 3 –8 Timing Function Units Basic Functions 16-Bit Decoder ns 32-Bit Decoder ns 64-Bit Decoder ns 4:1 Mux ns 8:1 Mux ns 16:1 Mux ns 32:1 Mux ns 1. I/Os are configured with LVCMOS25 with VCCIO=2.5, 12 mA Drive. 2. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 3. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond design software tool. 3-14 DC and Switching Characteristics ECP5 Family Data Sheet Register-to-Register Performance1, 2 –8 Timing Function Units Basic Functions 16-Bit Decoder MHz 32-Bit Decoder MHz 64-Bit Decoder MHz 4:1 Mux MHz 8:1 Mux MHz 16:1 Mux MHz 32:1 Mux MHz 8-Bit Adder MHz 16-Bit Adder MHz 64-Bit Adder MHz 16-Bit Counter MHz 32-Bit Counter MHz 64-Bit Counter MHz 64-Bit Accumulator MHz Embedded Memory Functions 1024x18 True-Dual Port RAM (Write Through or Normal), with EBR Output Registers MHz 1024x18 True-Dual Port RAM (Read-Before-Write), with EBR Output Registers MHz Distributed Memory Functions 16 x 2 Pseudo-Dual Port or 16 x 4 Single Port RAM (One PFU) MHz 16 x 4 Pseudo-Dual Port (Two PFUs) MHz DSP Functions 9 x 9 Multiplier (All Registers) MHz 18 x 18 Multiplier (All Registers) MHz 36 x 36 Multiplier (All Registers) MHz 18 x 18 Multiply-Add/Sub (All Registers) MHz 18 x 18 Multiply/Accumulate (Input and Output Registers) MHz 1. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 2. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond design software tool. Derating Timing Tables Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular temperature and voltage. 3-15 DC and Switching Characteristics ECP5 Family Data Sheet ECP5 Maximum I/O Buffer Speed1, 2, 3, 4, 5, 6 Over Recommended Operating Conditions Buffer Description Max. Units Maximum Input Frequency LVDS25 LVDS, VCCIO = 2.5 V 400 MHz MLVDS25 MLVDS, Emulated, VCCIO = 2.5 V 400 MHz BLVDS25 BLVDS, Emulated, VCCIO = 2.5 V 400 MHz MIPI D-PHY (HS Mode) MIPI Video 400 MHz SLVS SLVS similar to MIPI 400 MHz Mini LVDS Mini LVDS 400 MHz LVPECL33 LVPECL, Emulated, VCCIO = 3.3 V 400 MHz SSTL18 (all supported classes) SSTL_18 class I, II, VCCIO = 1.8 V 400 MHz SSTL15 (all supported classes) SSTL_15 class I, II, VCCIO = 1.5 V 400 MHz SSTL135 (all supported classes) SSTL_135 class I, II, VCCIO = 1.35 V 400 MHz HSUL12 (all supported classes) HSUL_12 class I, II, VCCIO = 1.2 V 400 MHz LVTTL33 LVTTL, VCCIO = 3.3 V 200 MHz LVCMOS33 LVCMOS, VCCIO = 3.3 V 200 MHz LVCMOS25 LVCMOS, VCCIO = 2.5 V 200 MHz LVCMOS18 LVCMOS, VCCIO = 1.8 V 200 MHz LVCMOS15 LVCMOS 1.5, VCCIO = 1.5 V 200 MHz LVCMOS12 LVCMOS 1.2, VCCIO = 1.2 V 200 MHz Maximum Output Frequency LVDS25E LVDS, Emulated, VCCIO = 2.5 V 300 MHz LVDS25 LVDS, VCCIO = 2.5 V 400 MHz MLVDS25 MLVDS, Emulated, VCCIO = 2.5 V 300 MHz BLVDS25 BLVDS, Emulated, VCCIO = 2.5 V 300 MHz LVPECL33 LVPECL, Emulated, VCCIO = 3.3 V 300 MHz SSTL18 (all supported classes) SSTL_18 class I, II, VCCIO = 1.8 V 400 MHz SSTL15 (all supported classes) SSTL_15 class I, II, VCCIO = 1.5 V 400 MHz SSTL135 (all supported classes) SSTL_135 class I, II, VCCIO = 1.35 V 400 MHz HSUL12 (all supported classes) HSUL12 class I, II, VCCIO = 1.2 V 400 MHz LVTTL33 LVTTL, VCCIO = 3.3 V 150 MHz LVCMOS33 (For all drives) LVCMOS, 3.3 V 150 MHz LVCMOS25 (For all drives) LVCMOS, 2.5 V 150 MHz LVCMOS18 (For all drives) LVCMOS, 1.8 V 150 MHz LVCMOS15 (For all drives) LVCMOS, 1.5 V 150 MHz LVCMOS12 (For all drives) LVCMOS, 1.2 V 150 MHz 1. 2. 3. 4. 5. 6. These maximum speeds are characterized but not tested on every device. Maximum I/O speed for differential output standards emulated with resistors depends on the layout. LVCMOS timing is measured with the load specified in the Switching Test Conditions table of this document. All speeds are measured at fast slew. Actual system operation may vary depending on user logic implementation. Maximum data rate equals 2 times the clock rate when utilizing DDR. 3-16 DC and Switching Characteristics ECP5 Family Data Sheet ECP5 External Switching Characteristics 1, 2, 3, 4, 5 Over Recommended Commercial Operating Conditions –8 Parameter Description Device –7 Min. Max. –6 Min. Max. Min. Max. Units Clocks Primary Clock fMAX_PRI Frequency for Primary Clock Tree — 370 — 303 — 257 MHz tW_PRI Clock Pulse Width for Primary Clock 0.8 — 0.9 - 1.0 — ns tSKEW_PRI Primary Clock Skew Within a Device — 420 — 462 — 505 ps Edge Clock fMAX_EDGE Frequency for Edge Clock Tree tW_EDGE Clock Pulse Width for Edge Clock tSKEW_EDGE Edge Clock Skew Within a Bank — 400 — 350 — 312 MHz 1.175 — 1.344 — 1.50 — ns — 160 — 180 — 200 ps Generic SDR Input General I/O Pin Parameters Using Dedicated Primary Clock Input Without PLL tCO Clock to Output - PIO Output Register LFE5-45 — 5.4 — 6.1 — 6.8 ns tSU Clock to Data Setup - PIO Input Register LFE5-45 0 — 0 — 0 — ns tH Clock to Data Hold - PIO Input Register LFE5-45 2.7 — 3 — 3.3 — ns tSU_DEL Clock to Data Setup - PIO Input Register with Data Input Delay LFE5-45 1.2 — 1.33 — 1.46 — ns tH_DEL Clock to Data Hold - PIO Input Register with Data Input Delay LFE5-45 0 — 0 — 0 — ns fMAX_IO Clock Frequency of I/O and PFU Register LFE5-45 — 400 — 350 — 312 MHz tCO Clock to Output - PIO Output Register Other Devices — tSU Clock to Data Setup - PIO Input Register Other Devices 0 tH Clock to Data Hold - PIO Input Register Other Devices — tSU_DEL Clock to Data Setup - PIO Input Register with Data Input Delay Other Devices — tH_DEL Clock to Data Hold - PIO Input Register with Data Input Delay Other Devices 0 — 0 — fMAX_IO Clock Frequency of I/O and PFU Register Other Devices — 400 — — — 0 — — 0 ns — ns — — ns — — ns 0 — ns 350 — 312 MHz General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL tCOPLL Clock to Output - PIO Output Register LFE5-45 — 3.5 — 3.8 — 4.1 ns tSUPLL Clock to Data Setup - PIO Input Register LFE5-45 0.7 — 0.78 — 0.85 — ns tHPLL Clock to Data Hold - PIO Input Register LFE5-45 0.8 — 0.89 — 0.98 — ns tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay LFE5-45 1.6 — 1.78 — 1.95 — ns tH_DELPLL Clock to Data Hold - PIO Input Register with Data Input Delay LFE5-45 0 — 0 — 0 — ns — tCOPLL Clock to Output - PIO Output Register Other Devices tSUPLL Clock to Data Setup - PIO Input Register Other Devices — — — ns tHPLL Clock to Data Hold - PIO Input Register Other Devices — — — ns tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay Other Devices — — — ns tH_DELPLL Clock to Data Hold - PIO Input Register with Data Input Delay Other Devices — ns 3-17 0 — — 0 — — 0 ns DC and Switching Characteristics ECP5 Family Data Sheet ECP5 External Switching Characteristics (Continued)1, 2, 3, 4, 5 Over Recommended Commercial Operating Conditions –8 Parameter Description Device Min. –7 Max. Min. –6 Max. Min. Max. Units Generic DDR Input Generic DDRX1 Inputs With Clock and Data Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Clock Input - Figure 3-6 tSU_GDDRX1_centered Data Setup Before CLK Input All Devices 0.52 — 0.52 tHD_GDDRX1_centered Data Hold After CLK Input All Devices fDATA_GDDRX1_centered GDDRX1 Data Rate All Devices fMAX_GDDRX1_centered GDDRX1 CLK Frequency (SCLK) All Devices — 0.52 0.52 — — 500 — 250 — ns 0.52 — 0.52 — ns — 500 — 500 Mbps — 250 — 250 MHz Generic DDRX1 Inputs With Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Clock Input - Figure 3-7 tSU_GDDRX1_aligned Data Setup from CLK Input All Devices — –0.55 — –0.55 — –0.55 ns + 1/2 UI tHD_GDDRX1_aligned Data Hold from CLK Input All Devices 0.55 — 0.55 — 0.55 — ns + 1/2 UI fDATA_GDDRX1_aligned GDDRX1 Data Rate All Devices — 500 — 500 — 500 Mbps fMAX_GDDRX1_aligned GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz Generic DDRX2 Inputs With Clock and Data Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Clock Input, Left and Right sides Only - Figure 3-6 tSU_GDDRX2_centered Data Setup Before CLK Input All Devices 0.321 — 0.403 — 0.471 — tHD_GDDRX2_centered Data Hold After CLK Input All Devices 0.321 — 0.403 — 0.471 — ns ns fDATA_GDDRX2_centered GDDRX2 Data Rate All Devices — 800 — 700 — 624 Mbps fMAX_GDDRX2_centered GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Generic DDRX2 Inputs With Clock and Data Aligned at Pin (GDDRX2_RX.ECLK.Aligned) Using PCLK Clock Input, Left and Right sides Only - Figure 3-7 tSU_GDDRX2_aligned Data Setup from CLK Input All Devices — –0.344 — –0.42 — –0.495 ns + 1/2 UI tHD_GDDRX2_aligned Data Hold from CLK Input All Devices 0.344 — 0.42 — 0.495 — ns + 1/2 UI fDATA_GDDRX2_aligned GDDRX2 Data Rate All Devices — 800 — 700 — 624 Mbps fMAX_GDDRX2_aligned GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Video DDRX71 Inputs With Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) Using PLL Clock Input, Left and Right sides Only Figure 3-13 tSU_LVDS71_i Data Setup from CLK Input (bit i) All Devices — –0.271 — –0.39 — –0.41 ns + (1/ 2+i) UI tHD_LVDS71_i Data Hold from CLK Input (bit i) All Devices 0.271 — 0.39 — 0.41 — ns + (1/ 2+i) UI fDATA_LVDS71 DDR71 Data Rate All Devices — 756 — 620 — 525 Mbps fMAX_LVDS71 DDR71 CLK Frequency (ECLK) All Devices — 378 — 310 — 262.5 MHz 3-18 DC and Switching Characteristics ECP5 Family Data Sheet ECP5 External Switching Characteristics (Continued)1, 2, 3, 4, 5 Over Recommended Commercial Operating Conditions –8 Parameter Description Device Min. –7 Max. Min. –6 Max. Min. Max. Units Generic DDR Output Generic DDRX1 Outputs With Clock and Data Centered at Pin (GDDRX1_TX.SCLK.Centered) Using PCLK Clock Input - Figure 3-10 tDVB_GDDRX1_centered Data Output Valid Before CLK Output All Devices –0.67 — –0.67 — –0.67 — ns + 1/2 UI tDVA_GDDRX1_centered Data Output Valid After CLK Output All Devices –0.67 — –0.67 — –0.67 — ns + 1/2 UI fDATA_GDDRX1_centered GDDRX1 Data Rate All Devices — 500 — 500 — 500 Mbps fMAX_GDDRX1_centered GDDRX1 CLK Frequency (SCLK) All Devices — 250 — 250 — 250 MHz Generic DDRX1 Outputs With Clock and Data Aligned at Pin (GDDRX1_TX.SCLK.Aligned) Using PCLK Clock Input - Figure 3-9 tDIB_GDDRX1_aligned Data Output Invalid Before CLK Output All Devices –0.3 — –0.3 tDIA_GDDRX1_aligned Data Output Invalid After CLK Output All Devices fDATA_GDDRX1_aligned GDDRX1 Data Rate All Devices fMAX_GDDRX1_aligned GDDRX1 CLK Frequency (SCLK) All Devices — –0.3 — 0.3 — 500 — 250 — ns — 0.3 — 0.3 ns — 500 — 500 Mbps — 250 — 250 MHz Generic DDRX2 Outputs With Clock and Data Centered at Pin (GDDRX2_TX.ECLK.Centered) Using PCLK Clock Input, Left and Right sides Only - Figure 3-10 tDVB_GDDRX2_centered Data Output Valid Before CLK Output All Devices –0.442 — –0.56 — –0.676 — ns + 1/2 UI tDVA_GDDRX2_centered Data Output Valid After CLK Output All Devices — 0.442 — 0.56 — 0.676 ns + 1/2 UI fDATA_GDDRX2_centered GDDRX2 Data Rate All Devices — 800 — 700 — 624 Mbps fMAX_GDDRX2_centered GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Generic DDRX2 Outputs With Clock and Data Aligned at Pin (GDDRX2_TX.ECLK.Aligned) Using PCLK Clock Input, Left and Right sides Only - Figure 3-9 tDIB_GDDRX2_aligned Data Output Invalid Before CLK Output All Devices –0.16 — –0.18 — –0.2 — ns tDIA_GDDRX2_aligned Data Output Invalid After CLK Output All Devices — 0.16 — 0.18 — 0.2 ns fDATA_GDDRX2_aligned GDDRX2 Data Rate All Devices — 800 — 700 — 624 Mbps fMAX_GDDRX2_aligned GDDRX2 CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz Video DDRX71 Outputs With Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) Using PLL Clock Input, Left and Right sides Only Figure 3-11 tDIB_LVDS71_i Data Output Invalid Before CLK Output All Devices –0.16 — –0.18 — –0.2 — ns + (i) UI tDIA_LVDS71_i Data Output Invalid After CLK Output All Devices — 0.16 — 0.18 fDATA_LVDS71 DDR71 Data Rate All Devices — 756 — 620 — 0.2 ns + (i) UI — 525 fMAX_LVDS71 DDR71 CLK Frequency (ECLK) All Devices — 378 — Mbps 310 — 262.5 MHz –0.374 ns + 1/2 UI Memory Interface DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 READ (DQ Input Data are Aligned to DQS) - Figure 3-7 tDVBDQ_DDR2 tDVBDQ_DDR3 tDVBDQ_DDR3L tDVBDQ_LPDDR2 tDVBDQ_LPDDR3 Data Output Valid Before DQS Input All Devices — –0.26 — –0.317 — tDVADQ_DDR2 tDVADQ_DDR3 tDVADQ_DDR3L tDVADQ_LPDDR2 tDVADQ_LPDDR3 Data Output Valid After DQS Input All Devices 0.26 — 0.317 — 0.374 — ns + 1/2 UI fDATA_DDR2 fDATA_DDR3 fDATA_DDR3L fDATA_LPDDR2 fDATA_LPDDR3 DDR Memory Data Rate All Devices — 800 — 700 — 624 Mbps 3-19 DC and Switching Characteristics ECP5 Family Data Sheet ECP5 External Switching Characteristics (Continued)1, 2, 3, 4, 5 Over Recommended Commercial Operating Conditions –8 Parameter fMAX_DDR2 fMAX_DDR3 fMAX_DDR3L fMAX_LPDDR2 fMAX_LPDDR3 –7 –6 Description Device Min. Max. Min. Max. Min. Max. Units DDR Memory CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 WRITE (DQ Output Data are Centered to DQS) - Figure 3-10 tDQVBS_DDR2 tDQVBS_DDR3 tDQVBS_DDR3L tDQVBS_LPDDR2 tDQVBS_LPDDR3 Data Output Valid Before DQS Output All Devices — –0.25 — –0.25 — -0.25 UI tDQVAS_DDR2 tDQVAS_DDR3 tDQVAS_DDR3L tDQVAS_LPDDR2 tDQVAS_LPDDR3 Data Output Valid After DQS Output All Devices 0.25 — 0.25 — 0.25 — UI fDATA_DDR2 fDATA_DDR3 fDATA_DDR3L fDATA_LPDDR2 fDATA_LPDDR3 DDR Memory Data Rate All Devices — 800 — 700 — 624 Mbps fMAX_DDR2 fMAX_DDR3 fMAX_DDR3L fMAX_LPDDR2 fMAX_LPDDR3 DDR Memory CLK Frequency (ECLK) All Devices — 400 — 350 — 312 MHz 1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond software. 2. General I/O timing numbers are based on LVCMOS 2.5, 12 mA, Fast Slew Rate, 0pf load. Generic DDR timing are numbers based on LVDS I/O. DDR2 timing numbers are based on SSTL18. DDR3 timing numbers are based on SSTL15. LPDDR2 and LPDDR3 timing numbers are based on HSUL12 3. Uses LVDS I/O standard for measurements. 4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 5. All numbers are generated with the Diamond software. 3-20 DC and Switching Characteristics ECP5 Family Data Sheet Figure 3-6. Receiver RX.CLK.Centered Waveforms Rx CLK (in) Rx DATA (in) tSU/tDVBDQ tSU/tDVBDQ tHD/tDVADQ tHD/tDVADQ Figure 3-7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms 1/2 UI 1/2 UI 1 UI Rx CLK (in) or DQS Input Rx DATA (in) or DQ Input tSU tSU tHD tHD Figure 3-8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms 1/2 UI 1/2 UI 1/2 UI 1/2 UI Tx CLK (out) or DQS Output Tx DATA (out) or DQ Output tDVB/tDQVBS tDVB/tDQVBS tDVA/tDQVAS tDVA/tDQVA 3-21 DC and Switching Characteristics ECP5 Family Data Sheet Figure 3-9. Transmit TX.CLK.Aligned Waveforms 1 UI Tx CLK (out) Tx DATA (out) tDIB tDIB tDIA tDIA Figure 3-10. DDRX71 Video Timing Waveforms 756 Mbps Clock In 108 MHz Data Out 756 Mbps Clock Out 108 MHz 3-22 DC and Switching Characteristics ECP5 Family Data Sheet Figure 3-11. Receiver DDRX71_RX Waveforms Bit 0 1/2 UI Bit i 1/2 UI Bit 1 1 UI CLK (in) DATA (in) tSU_0 tHD_0 tSU_i tHD_i Figure 3-12. Transmitter DDRX71_TX Waveforms Bit 0 Bit i Bit 1 1 UI CLK (out) DATA (out) tDIB_0 tDIA_0 tDIB_i tDIA_i 3-23 DC and Switching Characteristics ECP5 Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter Descriptions fIN Input Clock Frequency (CLKI, CLKFB) fOUT Output Clock Frequency (CLKOP, CLKOS, fVCO PLL VCO Frequency fPFD3 Phase Detector Input Frequency Conditions Min. Max. Units 8 400 MHz 3.125 400 MHz 400 800 MHz 10 400 MHz AC Characteristics tDT Output Clock Duty Cycle 45 55 % tPH4 Output Phase Accuracy –5 5 % 1 tOPJIT Output Clock Period Jitter Output Clock Cycle-to-Cycle Jitter Output Clock Phase Jitter fOUT >=100 MHz — 100 ps p-p fOUT < 100 MHz — 0.025 UIPP fOUT >=100 MHz — 200 ps p-p fOUT < 100 MHz — 0.050 UIPP fPFD > 100 MHz — 200 ps p-p fPFD < 100 MHz — 0.011 UIPP tSPO Static Phase Offset Divider ratio = integer — 400 ps p-p tW Output Clock Pulse Width At 90% or 10% 0.9 — ns 2 tLOCK PLL Lock-in Time — 15 ms tUNLOCK PLL Unlock Time — 50 ns tIPJIT Input Clock Period Jitter fPFD 20 MHz — 1,000 ps p-p fPFD < 20 MHz — 0.02 UIPP tHI Input Clock High Time 90% to 90% 0.5 — ns tLO Input Clock Low Time 10% to 10% 0.5 — ns tRST RST/ Pulse Width 1 — ms tRSTREC RST Recovery Time 1 — ns tLOAD_REG Min Pulse for CIB_LOAD_REG 10 — ns tROTATE-SETUP Min time for CIB dynamic phase controls to be stable fore CIB_ROTATE 5 — ns tROTATE-WD Min pulse width for CIB_ROTATE to maintain “0” or “1” 4 — VCO cycles 1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not be met in certain conditions. 3-24 DC and Switching Characteristics ECP5 Family Data Sheet SERDES High-Speed Data Transmitter1 Table 3-6. Serial Output Timing and Levels Symbol Description Min. 1, 2 Typ. Units 25% mV, pp — mV, pp VTX-DIFF-PP Peak-Peak Differential voltage on selected amplitude VTX-CM-DC Output common mode voltage TTX-R Rise time (20% to 80%) 50 — — ps TTX-F Fall time (80% to 20%) 50 — — ps TTX-CM-AC-P RMS AC peak common-mode output voltage — — 20 mV ZTX_SE Single ended output impedance for 50/75 Ohms –20% 50/75 20% Ohms Single ended output impedance for 6K Ohms –25% 6K 25% Ohms RLTX_DIFF Differential return loss (with package included) 3 — — –10 dB — — –6 dB RLTX_COM –25% Max. — Common mode return loss (with package included) 3 VCCHTX / 2 1. Measured with 50-Ohm Tx Driver impedance at VCCHTX=1.1 V+/–5%. 2. See TN1261, ECP5 SERDES/PCS Usage Guide for settings of Tx amplitude. 3. Return los = -10 dB (differential), –6 dB (common mode) for 100 MHz <= f <= 1.6 GHz with 50-Ohm output impedance configuration. This includes degradation due to package effects. Table 3-7. Channel Output Jitter Description Deterministic Frequency 3.125 Gbps Min. Typ. Max. Units — — 0.17 UI, p-p Random 3.125 Gbps — — 0.25 UI, p-p Total 3.125 Gbps — — 0.35 UI, p-p Deterministic 2.5 Gbps — — 0.17 UI, p-p Random 2.5 Gbps — — 0.20 UI, p-p Total 2.5 Gbps — — 0.35 UI, p-p Deterministic 1.25 Gbps — — 0.10 UI, p-p Random 1.25 Gbps — — 0.22 UI, p-p Total 1.25 Gbps — — 0.24 UI, p-p 7 Note: Values are measured with PRBS 2 -1, all channels operating, FPGA logic active, I/Os around SERDES pins quiet, reference clock @ 10X mode. 3-25 DC and Switching Characteristics ECP5 Family Data Sheet SERDES/PCS Block Latency Table 3-8 describes the latency of each functional block in the transmitter and receiver. Latency is given in parallel clock cycles. Figure 3-13 shows the location of each block. Table 3-8. SERDES/PCS Latency Breakdown Item Description Avg. Max. Fixed FPGA Bridge - Gearing disabled with same clocks 3 — 4 — 1 byte clk FPGA Bridge - Gearing enabled 5 — 7 — — word clk Transmit Data Latency T1 Bypass Units3 Min. 1 T2 8b10b Encoder — — — 2 1 byte clk T3 SERDES Bridge transmit — — — 2 1 byte clk T4 T5 Serializer: 8-bit mode — — — 15 + 1 — UI + ps Serializer: 10-bit mode — — — 18 + 1 — UI + ps Pre-emphasis ON — — — 1 + 2 — UI + ps Pre-emphasis OFF — — — 0 + 3 — UI + ps Equalization ON — — — 1 — UI + ps Equalization OFF — — — 2 — UI + ps Deserializer: 8-bit mode — — — 10 + 3 — UI + ps 2 Receive Data Latency R1 R2 Deserializer: 10-bit mode — — — 12 + 3 — UI + ps SERDES Bridge receive — — — 2 — byte clk R4 Word alignment 3.1 — 4 — 1 byte clk R5 8b10b decoder — — — 1 0 byte clk R3 R6 R7 Clock Tolerance Compensation 7 15 23 — 1 byte clk FPGA Bridge - Gearing disabled with same clocks 4 — 5 — 1 byte clk FPGA Bridge - Gearing enabled 7 — 9 — — word clk 1. 1 = –245 ps, 2 = +88 ps, 3 = +112 ps. 2. 1 = +118 ps, 2 = +132 ps, 3 = +700 ps. 3. byte clk = 8UIs (8-bit mode), or 10 UIs (10-bit mode); word clk = 16UIs (8-bit mode), or 20 UIs (10-bit mode). Figure 3-13. Transmitter and Receiver Latency Block Diagram SERDES SERDES Bridge R2 R1 HDINPi PCS Deserializer 1:8/1:10 CDR HDINNi DEC Polarity Adjust BYPASS R6 Elastic Buffer FIFO BYPASS R7 Down Sample FIFO Receive Data BYPASS BYPASS Receiver REFCLK R5 R4 R3 FPGA Core FPGA EBRD Clock WA EQ FPGA Bridge Recovered Clock REFCLK FPGA Receive Clock Transmit Clock TX PLL T2 T1 FPGA Transmit Clock T3 T5 HDOUTPi T4 Serializer 8:1/10:1 HDOUTNi Transmitter Encoder Polarity Adjust Up Sample FIFO BYPASS BYPASS BYPASS 3-26 Transmit Data DC and Switching Characteristics ECP5 Family Data Sheet SERDES High-Speed Data Receiver Table 3-9. Serial Input Data Specifications Symbol VRX-DIFF-S Description Differential input sensitivity Min. Typ. Max. 150 — 1760 Units mV, p-p 2 VRX-IN Input levels 0 — VCCA +0.5 V VRX-CM-DCCM Input common mode range (internal DC coupled mode) 0.6 — VCCA V VRX-CM-ACCM Input common mode range (internal AC coupled mode)2 0.1 — VCCA +0.2 V TRX-RELOCK SCDR re-lock time1 — 1000 — Bits ZRX-TERM Input termination 50/75 Ohm/High Z –20% 50/75/5 K +20% Ohms RLRX-RL Return loss (without package) — — –10 dB 1. This is the typical number of bit times to re-lock to a new phase or frequency within +/– 300 ppm, assuming 8b10b encoded data. 2. Up to 1.65 V. Input Data Jitter Tolerance A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface standards have recognized the dependency on jitter type and have specifications to indicate tolerance levels for different jitter types as they relate to specific protocols. Sinusoidal jitter is considered to be a worst case jitter type. Table 3-10. Receiver Total Jitter Tolerance Specification1 Description Frequency Min. Typ. Max. 400 mV differential eye — — 0.37 UI, p-p 400 mV differential eye — — 0.18 UI, p-p Total 400 mV differential eye — — 0.65 UI, p-p Deterministic 400 mV differential eye — — 0.37 UI, p-p Deterministic Random Random 3.125 Gbps 2.5 Gbps Total Deterministic Random Total 1.25 Gbps Condition Units 400 mV differential eye — — 0.18 UI, p-p 400 mV differential eye — — 0.65 UI, p-p 400 mV differential eye — — 0.37 UI, p-p 400 mV differential eye — — 0.18 UI, p-p 400 mV differential eye — — 0.65 UI, p-p 1. Jitter tolerance measurements are done with protocol compliance tests: 3.125 Gbps - XAUI Standard, 2.5 Gbps - PCIe Standard, 1.25 Gbps - SGMII Standard. 3-27 DC and Switching Characteristics ECP5 Family Data Sheet SERDES External Reference Clock The external reference clock selection and its interface are a critical part of system applications for this product. Table 3-11 specifies reference clock requirements, over the full range of operating conditions. Table 3-11. External Reference Clock Specification (refclkp/refclkn) Symbol FREF Description Min. Typ. Max. Units 50 — 320 MHz Frequency range 1 FREF-PPM Frequency tolerance –1000 — 1000 ppm VREF-IN-SE Input swing, single-ended clock2, 4 200 — VCCAUXA mV, p-p VREF-IN-DIFF Input swing, differential clock 200 — 2*VCCAUXA mV, p-p differential VREF-IN Input levels 0 — VCCAUXA + 0.4 V DREF Duty cycle3 40 — 60 % TREF-R Rise time (20% to 80%) 200 500 1000 ps TREF-F Fall time (80% to 20%) 200 500 1000 ps –30% 100/HiZ +30% Ohms — — 7 pF ZREF-IN-TERM-DIFF Differential input termination CREF-IN-CAP Input capacitance 1. Depending on the application, the PLL_LOL_SET and CDR_LOL_SET control registers may be adjusted for other tolerance values as described in TN1261, ECP5 SERDES/PCS Usage Guide. 2. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain at the input receiver. With single-ended clock, a reference voltage needs to be externally connected to CLKREFN pin, and the input voltage needs to be swung around this reference voltage. 3. Measured at 50% amplitude. 4. Single-ended clocking is achieved by applying a reference voltage VREF on REFCLKN input, with the clock applied to REFCLKP input pin. VREF should be set to mid-point of the REFCLKP voltage swing. Figure 3-14. SERDES External Reference Clock Waveforms V+ P VREF-IN MAX < 1.56 V N 0V VREF_IN_DIFF Min=200 mV Max=2xVCCA V+ VREF_IN_DIFF= IVp-VnI V+ VREF-IN MAX < 1.56 V VREF_IN_SE Min=200 mV 0V Max=VCCA 3-28 DC and Switching Characteristics ECP5 Family Data Sheet PCI Express Electrical and Timing Characteristics AC and DC Characteristics Over Recommended Operating Conditions Symbol Description Test Conditions Min Typ Max Units 399.88 400 400.12 ps 1 Transmit UI Unit interval VTX-DIFF_P-P Differential peak-to-peak output voltage 0.8 1.0 1.2 V VTX-DE-RATIO De-emphasis differential output voltage ratio –3 –3.5 –4 dB VTX-CM-AC_P RMS AC peak common-mode output voltage — — 20 mV VTX-RCV-DETECT Amount of voltage change allowed during receiver detection — — 600 mV VTX-CM-DC Tx DC common mode voltage 0 — VCCHTX + 5% V ITX-SHORT Output short circuit current — — 90 mA VTX-D+=0.0 V VTX-D-=0.0 V ZTX-DIFF-DC Differential output impedance 80 100 120 Ohms RLTX-DIFF Differential return loss 10 — — dB RLTX-CM Common mode return loss 6.0 — — dB TTX-RISE Tx output rise time 20% to 80% 0.125 — — UI TTX-FALL Tx output fall time 20% to 80% 0.125 — — UI LTX-SKEW Lane-to-lane static output skew for all lanes in port/link — — 1.3 ns TTX-EYE Transmitter eye width 0.75 — — UI TTX-EYE-MEDIAN-TO-MAX-JITTER Maximum time between jitter median and maximum deviation from median — — 0.125 UI 400 400.12 ps Receive1, 2 UI Unit Interval 399.88 3 VRX-DIFF_P-P Differential peak-to-peak input voltage 0.34 — 1.2 V VRX-IDLE-DET-DIFF_P-P Idle detect threshold voltage 65 — 3403 mV VRX-CM-AC_P RMS AC peak common-mode input voltage — — 150 mV ZRX-DIFF-DC DC differential input impedance 80 100 120 Ohms ZRX-DC DC input impedance 40 50 60 Ohms ZRX-HIGH-IMP-DC Power-down DC input impedance 200K — — Ohms RLRX-DIFF Differential return loss 10 — — dB RLRX-CM Common mode return loss 6.0 — — dB 1. Values are measured at 2.5 Gbps. 2. Measured with external AC-coupling on the receiver. 3. Not in compliance with PCI Express 1.1 standard. 3-29 DC and Switching Characteristics ECP5 Family Data Sheet XAUI/CPRI LV E.30 Electrical and Timing Characteristics AC and DC Characteristics Table 3-12. Transmit Over Recommended Operating Conditions Symbol Description Test Conditions Min. Typ. Max. Units 20% to 80% — 80 — ps Differential impedance 80 100 120 Ohms Output data deterministic jitter — — 0.17 UI Total output data jitter — — 0.35 UI TRF Differential rise/fall time ZTX_DIFF_DC JTX_DDJ2, 3 JTX_TJ 1, 2, 3 1. Total jitter includes both deterministic jitter and random jitter. 2. Jitter values are measured with each CML output AC coupled into a 50-Ohm impedance (100-Ohm differential impedance). 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Table 3-13. Receive and Jitter Tolerance Over Recommended Operating Conditions Symbol Description Test Conditions Min. Typ. Max. Units 10 — — dB 6 — — dB RLRX_DIFF Differential return loss From 100 MHz to 3.125 GHz RLRX_CM Common mode return loss From 100 MHz to 3.125 GHz ZRX_DIFF Differential termination resistance 80 100 120 Ohms JRX_DJ Deterministic jitter tolerance (peak-to-peak) — — 0.37 UI JRX_RJ1, 2, 3 Random jitter tolerance (peak-to-peak) — — 0.18 UI JRX_SJ Sinusoidal jitter tolerance (peak-to-peak) — — 0.10 UI JRX_TJ1, 2, 3 Total jitter tolerance (peak-to-peak) — — 0.65 UI TRX_EYE Receiver eye opening 0.35 — — UI 1, 2, 3 1, 2, 3 1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 2. Jitter values are measured with each high-speed input AC coupled into a 50-Ohm impedance. 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 3-30 DC and Switching Characteristics ECP5 Family Data Sheet CPRI LV E.24 Electrical and Timing Characteristics AC and DC Characteristics Table 3-14. Transmit Symbol Description Test Conditions Min. Typ. Max. Units 20% to 80% — 80 — ps Differential impedance 80 100 120 Ohm Output data deterministic jitter — — 0.17 UI Total output data jitter — — 0.35 UI TRF1 Differential rise/fall time ZTX_DIFF_DC JTX_DDJ3, 4 JTX_TJ 1. 2. 3. 4. 2, 3, 4 Rise and Fall times measured with board trace, connector and approximately 2.5 pf load. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter. Jitter values are measured with each CML output AC coupled into a 50-Ohm impedance (100-Ohm differential impedance). Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Table 3-15. Receive and Jitter Tolerance Test Conditions Min. Typ. Max. Units RLRX_DIFF Symbol Differential return loss From 100 MHz to 2.5 GHz 10 — — dB RLRX_CM Common mode return loss From 100 MHz to 2.5 GHz 6 — — dB ZRX_DIFF Differential termination resistance 80 100 120 Ohm JRX_DJ2, 3, 4 Deterministic jitter tolerance (peak-to-peak) — — 0.37 UI JRX_RJ2, 3, 4 Random jitter tolerance (peak-to-peak) — — 0.18 UI JRX_SJ Sinusoidal jitter tolerance (peak-to-peak) — — 0.10 UI JRX_TJ1, 2, 3, 4 Total jitter tolerance (peak-to-peak) — — 0.65 UI TRX_EYE Receiver eye opening 0.35 — — UI 2, 3, 4 1. 2. 3. 4. Description Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. Jitter values are measured with each high-speed input AC coupled into a 50-Ohm impedance. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 3-31 DC and Switching Characteristics ECP5 Family Data Sheet Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics AC and DC Characteristics Table 3-16. Transmit Symbol Description Test Conditions Min. Typ. Max. Units 20% to 80% — 80 — ps Differential impedance 80 100 120 Ohms Output data deterministic jitter — — 0.10 UI Total output data jitter — — 0.24 UI TRF Differential rise/fall time ZTX_DIFF_DC JTX_DDJ2, 3 JTX_TJ 1, 2, 3 1. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter. 2. Jitter values are measured with each CML output AC coupled into a 50-Ohm impedance (100-Ohm differential impedance). 3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Table 3-17. Receive and Jitter Tolerance Symbol Description Test Conditions Min. Typ. Max. Units RLRX_DIFF Differential return loss From 100 MHz to 1.25 GHz 10 — — dB RLRX_CM Common mode return loss From 100 MHz to 1.25 GHz 6 — — dB ZRX_DIFF Differential termination resistance 80 100 120 Ohms JRX_DJ1, 2, 3, 4 Deterministic jitter tolerance (peak-to-peak) — — 0.34 UI JRX_RJ Random jitter tolerance (peak-to-peak) — — 0.26 UI JRX_SJ1, 2, 3, 4 Sinusoidal jitter tolerance (peak-to-peak) — — 0.11 UI — — 0.71 UI 0.29 — — UI 1, 2, 3, 4 JRX_TJ 1, 2, 3, 4 TRX_EYE 1. 2. 3. 4. Total jitter tolerance (peak-to-peak) Receiver eye opening Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. Jitter values are measured with each high-speed input AC coupled into a 50-Ohm impedance. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 3-32 DC and Switching Characteristics ECP5 Family Data Sheet SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics3, 4, 5 AC and DC Characteristics Table 3-18. Transmit Symbol Description Test Conditions Min. Typ. Max. Units BRSDO Serial data rate 270 — 2975 Mbps TJALIGNMENT 2 Serial output jitter, alignment 270 Mbps6 — — TBD UI 2 Serial output jitter, alignment 1485 Mbps — — TBD UI Serial output jitter, alignment 2970 Mbps — — TBD UI TJALIGNMENT TJALIGNMENT1, 2 6 TJTIMING Serial output jitter, timing 270 Mbps — — TBD UI TJTIMING Serial output jitter, timing 1485 Mbps — — TBD UI TJTIMING Serial output jitter, timing 2970 Mbps — — TBD UI 1. Timing jitter is measured in accordance with SMPTE serial data transmission standards. 2. Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter. 3. All Tx jitter are measured at the output of an industry standard cable driver, with the Lattice SERDES device configured to 50-Ohm output impedance connecting to the external cable driver with differential signaling. 4. The cable driver drives: RL=75 Ohm, AC-coupled at 270, 1485, or 2970 Mbps. 5. All LFE5UM devices are compliant with all SMPTE compliance tests, except 3G-SDI Level-A pathological compliance pattern test. 6. 270 Mbps is supported with Rate Divider only. Table 3-19. Receive Symbol BRSDI Description Test Conditions Serial input data rate Min. Typ. Max. Units 270 — 2970 Mbps Table 3-20. Reference Clock1 Symbol Description Test Conditions Min. Typ. Max. Units FVCLK Video output clock frequency 54 — 148.5 MHz DCV Duty cycle, video clock 45 50 55 % 1. SD-SDI (270 Mbps) is supported with Rate Divider only. For Single Rate: Reference Clock = 54 MHz and Rate Divider = /2. For Tri-Rate: Reference Clock = 148.5 MHz and Rate Divider = /11. 3-33 DC and Switching Characteristics ECP5 Family Data Sheet ECP5 sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Symbol Parameter Min. Max. Units POR, Configuration Initialization, and Wakeup tICFG Time from the Application of VCC, VCCAUX or VCCIO8 (whichever is the last) to the rising edge of INITN — 33 ms tVMC Time from tICFG to the valid Master CCLK us CCLK from Active to High-Z — — 5 tCZ 300 ns Master CCLK Frequency All selected frequencies –20 20 % Duty Cycle All selected frequencies 40 60 % All Configuration Modes tPRGM PROGRAMN LOW pulse accepted 110 — ns tPRGMRJ PROGRAMN LOW pulse rejected 50 ns tINITL INITN LOW time 55 ns tDPPINT PROGRAMN LOW to INITN LOW 70 ns tDPPDONE PROGRAMN LOW to DONE LOW 80 ns tIODISS PROGRAMN LOW to I/O Disabled — — — — — 150 ns fCCLK CCLK input clock frequency — 60 MHz 6 — — — — ns Slave SPI tCCLKH CCLK input clock pulsewidth HIGH tCCLKL CCLK input clock pulsewidth LOW 6 tSTSU CCLK setup time 1 tSTH CCLK hold time 1 tSTCO CCLK falling edge to valid output 10 ns tSTOZ CCLK falling edge to valid disable 10 ns tSTOV CCLK falling edge to valid enable — — — 10 ns tSCS Chip Select HIGH time 25 ns tSCSS Chip Select setup tim 3 tSCSH Chip Select hold time 3 — — — fCCLK Max selected CCLK output frequency — 62 MHz ns ns ns ns ns ns Master SPI tCCLKH CCLK output clock pulse width HIGH 3.5 tCCLKL CCLK output clock pulse width LOW 3.5 tSTSU CCLK setup time tSTH CCLK hold time 1 — — — — tCSSPI INITN HIGH to Chip Select LOW 100 200 ns tCFGX INITN HIGH to first CCLK edge — 150 ns 5 66 MHz — — — — ns 5 ns ns ns Slave Serial fCCLK CCLK input clock frequency tSSCH CCLK input clock pulse width HIGH tSSCL CCLK input clock pulse width LOW tSUSCDI CCLK setup time 0.5 tHSCDI CCLK hold time 1.5 5 3-34 ns ns ns DC and Switching Characteristics ECP5 Family Data Sheet ECP5 sysCONFIG Port Timing Specifications (Continued) Over Recommended Operating Conditions Slave Parallel fCCLK CCLK input clock frequency — 50 MHz tBSCH CCLK input clock pulsewidth HIGH 6 ns tBSCL CCLK input clock pulsewidth LOW 6 — — tCORD CCLK to DOUT for Read Data — 12 ns tSUCBDI Data Setup Time to CCLK 1.5 ns tHCBDI Data Hold Time to CCLK 1.5 tSUCS CSN, CSN1 Setup Time to CCLK 2.5 tHCS CSN, CSN1 Hold Time to CCLK 1.5 tSUWD WRITEN Setup Time to CCLK 45 tHCWD WRITEN Hold Time to CCLK 2 — — — — — — tDCB CCLK to BUSY Delay Time — 12 ns Figure 3-15. sysCONFIG Parallel Port Read Cycle tBSCL tBSCYC tBSCH CCLK t SUCS tHCS tSUWD t HWD CS1N CSN WRITEN tDCB BUSY t CORD D[0:7] Byte 0 Byte 1 *n = last byte of read cycle. 3-35 Byte 2 Byte n* ns ns ns ns ns ns DC and Switching Characteristics ECP5 Family Data Sheet Figure 3-16. sysCONFIG Parallel Port Write Cycle tBSCYC tBSCL tBSCH CCLK 1 t SUCS tHCS CS1N CSN t SUWD t HWD WRITEN tDCB BUSY t HCBDI tSUCBDI D[0:7] Byte 0 Byte 1 Byte 2 Byte n 1. In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK. Figure 3-17. sysCONFIG Slave Serial Port Timing tSSCL tSSCH CCLK (input) tHSCDI t SUSCDI DIN t CODO DOUT Figure 3-18. Power-On-Reset (POR) Timing VCC / VCCAUX / VCCIO81 tICFG INITN DONE t VMC CCLK 2 CFG[2:0] 3 Valid 1. Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point. 2. Device is in a Master Mode (SPI, SPIm). 3. The CFG pins are normally static (hard wired). 3-36 DC and Switching Characteristics ECP5 Family Data Sheet Figure 3-19. sysCONFIG Port Timing Wake Up Clocks tICFG tSSCH tVMC VCC tSSCL tPRGM tPRGMRJ CCLK PROGRAMN tDPPINIT INITN tHSCDI (tHMCDI) tSUSCDI (tSUMCDI) DONE tCODO tDPPDONE DI GOE Release DOUT tIOENSS sysIO tIODISS Figure 3-20. Configuration from PROGRAMN Timing tPRGMRJ PROGRAMN INITN tDPPINIT DONE t DINITD CCLK CFG[2:0] 1 Valid t IODISS USER I/O 1. The CFG pins are normally static (hard wired) 3-37 DC and Switching Characteristics ECP5 Family Data Sheet Figure 3-21. Wake-Up Timing PROGRAMN INITN DONE Wake-Up tMWC CCLK tIOENSS USER I/O Figure 3-22. Master SPI Configuration Waveforms Capture CR0 Capture CFGx VCC PROGRAMN DONE INITN CSSPIN 0 1 2 3 … 7 8 9 10 … 31 32 33 34 … 127 128 CCLK SISPI Opcode Address Ignore SOSPI 3-38 Valid Bitstream DC and Switching Characteristics ECP5 Family Data Sheet JTAG Port Timing Specifications Over Recommended Operating Conditions Min Max Units fMAX Symbol TCK clock frequency Parameter — 25 MHz tBTCPH TCK [BSCAN] clock pulse width high 20 — ns tBTCPL TCK [BSCAN] clock pulse width low 20 — ns tBTS TCK [BSCAN] setup time 10 — ns tBTH TCK [BSCAN] hold time 8 — ns tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns tBTCO TAP controller falling edge of clock to valid output — 10 ns tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns tBTCRS BSCAN test capture register setup time 8 — ns tBTCRH BSCAN test capture register hold time 25 — ns tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns Figure 3-23. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH tBTH tBTCP tBTCPL TCK tBTCO tBTCOEN TDO Valid Data tBTCRS Data to be captured from I/O tBTCODIS Valid Data tBTCRH Data Captured tBTUPOEN tBUTCO Data to be driven out to I/O Valid Data 3-39 tBTUODIS Valid Data DC and Switching Characteristics ECP5 Family Data Sheet Switching Test Conditions Figure 3-24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-21. Figure 3-24. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT Test Poi nt R2 CL* *CL Includes Test Fixture and Probe Capacitance Table 3-21. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> H, H -> L) R1 R2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) 1M LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 100 1M CL 0pF 0pF VT LVCMOS 3.3 = 1.5 V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — VCCIO/2 — VCCIO 0pF VCCIO/2 100 0pF — VOH – 0.10 0pF VOL + 0.10 VCCIO Note: Output test conditions for all other interfaces are determined by the respective standards. 3-40 Timing Ref. ECP5 Family Data Sheet Pinout Information August 2015 Preliminary Data Sheet DS1044 Signal Descriptions Signal Name I/O Description P[L/R] [Group Number]_[A/B/C/D] I/O [L/R] indicates the L (Left), or R (Right) edge of the device. [Group Number] indicates the PIO [A/B/C/D] group. [A/B/C/D] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pins, when not used as special purpose pins, can be programmed as I/ Os for user logic. During configuration the user-programmable I/Os are tristated with an internal pull-down resistor enabled. If any pin is not used (or not bonded to a package pin), it is tristated and default to have pull-down enabled after configuration. PIO A and B are grouped as a pair, and PIO C and D are group as a pair. Each pair supports true LVDS differential input buffer. Only PIO A and B pair supports true LVDS differential output buffer. Each A/B and C/D pair supports programmable on/off differential input termination of 100 Ohms. P[T/B][Group Number]_[A/B] I/O [T/B] indicates the T (top) or B (bottom) edge of the device. [Group Number] indicates the PIO [A/B] group. [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with sysConfig pins. These pins, when not used as configuration pins, can be programmed as I/Os for user logic. During configuration, the pins not used in configuration are tristated with an internal pull-down resistor enabled. If any pin is not used (or not bonded to a package pin), it is tristated and default to have pull-down enabled after configuration. PIOs on top and bottom do not support differential input signaling or true LVDS output signaling, but it can support emulated differential output buffer. PIO A/B forms a pair of emulated differential output buffer. General Purpose GSRN NC I — Global RESET signal (active low). Any I/O pin can be GSRN. No connect. RESERVED — This pin is reserved and should not be connected to anything on the board. GND — Ground. Dedicated pins. VCC — Power supply pins for core logic. Dedicated pins. VCC = 1.1 V VCCAUX — Auxiliary power supply pin. This dedicated pin powers all the differential and referenced input buffers. VCCAUX = 2.5 V. VCCIOx — Dedicated power supply pins for I/O bank x. VCCIO8 is used for configuration and JTAG. VREF1_x — Reference supply pins for I/O bank x. Pre-determined shared pin in each bank are assigned as VREF1 input. When not used, they may be used as I/O pins. I General Purpose PLL (GPLL) input pads: [LOC] = ULC, LLC, URC and LRC, T = true and C = complement. These pins are shared I/O pins. When not configured as GPLL input pads, they can be used as general purpose I/O pins. PLL, DLL and Clock Functions [LOC][_GPLL[T, C]_IN © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1044 Pinout Information_01.2 Pinout Information ECP5 Family Data Sheet Signal Name I/O Description I General Routing Signals in Banks 0, 1, 2, 3, 4, 6 and 7. There are 2 in each bank ([num] = 0, 1). Please refer to ECP5 sysCLOCK Usage Guide. These pins are shared I/O pins. When not configured as GR pins, they can be used as general purpose I/O pins. PCLK[T/C][Bank]_[num] I/O General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1, 2, 3, 6 and 7). There are 2 in each bank ([num] = 0, 1). These are shared I/ O pins. When not configured as PCLK pins, they can be used as general purpose I/O pins. [L/R]DQS[group_num] I/O DQS input/output pads: T (top), R (right), group_ num = ball number associated with DQS[T] pin. [T/R]]DQ[group_num] I/O DQ input/output pads: T (top), R (right), group_ num = ball number associated with DQS[T] pin. GR_PCLK[Bank][num] Test and Programming (Dedicated Pins) TMS I Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. This is a dedicated input pin. TCK I Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. This is a dedicated input pin. TDI I Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. This is a dedicated input pin. TDO O Output pin. Test Data Out pin used to shift data out of a device using 1149.1. This is a dedicated output pin. Configuration Pads (Used During sysCONFIG) CFG[2:0] INITN PROGRAMN I Mode pins used to specify configuration mode values latched on rising edge of INITN. During configuration, a pull-up is enabled. These are dedicated pins. I/O Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. This is a dedicated pin. I Initiates configuration sequence when asserted low. This pin always has an active pull-up. This is a dedicated pin. DONE I/O Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. This is a dedicated pin. CCLK I/O Input Configuration Clock for configuring an FPGA in Slave SPI, Serial, and CPU modes. Output Configuration Clock for configuring an FPGA in Master configuration modes (Master SPI, Master Serial). This is a dedicated pin. HOLDN/DI/BUSY/CSSPIN/CEN I/O Parallel configuration mode busy indicator. SPI/SPIm mode data output. This is a shared I/O pin. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. CSN/SN I/O Parallel configuration mode active-low chip select. Slave SPI chip select. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. CS1N I Parallel configuration mode active-low chip select. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. WRITEN I Write enable for parallel configuration modes. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. 4-2 Pinout Information ECP5 Family Data Sheet I/O Description DOUT/CSON Signal Name O Serial data output. Chip select output. SPI/SPIm mode chip select. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D0/MOSI/IO0 I/O Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an output in Master mode, and input in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D1/MISO/IO1 I/O Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an input in Master mode, and output in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D2/IO2 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D3/IO3 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D4/IO4 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/ O pin. When not in configuration, it can be used as general purpose I/O pin. D5/IO5 I/O Parallel configuration I/O. Open drain during configuration. This is a shared I/ O pin. When not in configuration, it can be used as general purpose I/O pin. D6/IO6 I/O Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an output in Master mode, and input in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin. D7/IO7 I/O Parallel configuration I/O. Open drain during configuration. When in SPI modes, it is an output in Master mode, and input in Slave mode. This is a shared I/O pin. When not in configuration, it can be used as general purpose I/O pin VCCAx — SERDES, transmit, receive, PLL and reference clock buffer power supply for SERDES Dual x. All VCCA supply pins must always be powered to the recommended operating voltage range. If no SERDES channels are used, connect VCCA to VCC. VCCAx = 1.1 V. VCCAUXAx — SERDES Aux Power Supply pin for SERDES Dual x. VCCAUXAx = 2.5 V. SERDES Function HDRX[P/ N]_D[dual_num]CH[chan_num] I High-speed SERDES inputs, P = Positive, N = Negative, dual_num = [0, 1], chan_num = [0, 1]. These are dedicated SERDES input pins. HDTX[P/ N]_D[dual_num]CH[chan_num] O High-speed SERDES outputs, P = Positive, N = Negative, dual_num = [0, 1], chan_num = [0, 1]. These are dedicated SERDES output pins. REFCLK[P/N]_D[dual_num] I SERDES Reference Clock inputs, P = Positive, N = Negative, dual_num = [0, 1]. These are dedicated SERDES input pins. VCCHRX_D[dual_num]CH[chan_num] — SERDES High-Speed Inputs Termination Voltage Supplies, dual_num = [0, 1], chan_num = [0, 1]. These can be powered to 1.1 V. It is recommended to connect it to VCCAx. VCCHTX_D[dual_num]CH[chan_num] — SERDES High-Speed Outputs Buffer Voltage Supplies, dual_num = [0, 1], chan_num = [0, 1]. These can be powered to 1.1 V. 1. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given. 2. These pins are dedicated inputs or can be used as general purpose I/O. 3. m defines the associated channel in the quad. 4-3 Pinout Information ECP5 Family Data Sheet PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe PIO Within PIC DDR Strobe (DQS) and Data (DQ) Pins For Left and Right Edges of the Device Only P[L/R] [n-6] P[L/R] [n-3] P[L/R] [n] P[L/R] [n+3] A DQ B DQ C DQ D DQ A DQ B DQ C DQ D DQ A DQS (P) B DQS (N) C DQ D DQ A DQ B DQ C DQ D DQ Note: “n” is a row PIC number. 4-4 Pinout Information ECP5 Family Data Sheet Pin Information Summary LFE5UM Pin Information Summary LFE5UM-45 LFE5UM-85 285 csfBGA 381 caBGA 285 csfBGA 381 caBGA 554 caBGA 285 csfBGA 381 caBGA 554 caBGA 756 caBGA 6 24 6 27 32 6 27 32 56 Bank 1 6 32 6 33 40 6 33 40 48 Bank 2 21 32 21 32 32 21 34 32 48 Bank 3 28 32 28 33 48 28 33 48 64 Bank 4 0 0 0 0 0 0 0 14 24 Bank 6 26 32 26 33 48 26 33 48 64 Bank 7 18 32 18 32 32 18 32 32 48 Pin Type Bank 0 General Purpose Inputs/Outputs per Bank LFE5UM-25 13 13 13 13 13 13 13 13 13 Total Single-Ended User I/O Bank 8 118 197 118 203 245 118 205 259 365 VCC 13 20 13 20 24 13 20 24 36 VCCAUX (Core) 3 4 3 4 9 3 4 9 8 Bank 0 1 2 1 2 3 1 2 3 4 Bank 1 1 2 1 2 3 1 2 3 4 Bank 2 2 3 2 3 4 2 3 4 4 Bank 3 2 3 2 3 3 2 3 3 4 Bank 4 0 0 0 0 0 0 0 2 2 Bank 6 2 3 2 3 4 2 3 4 4 Bank 7 2 3 2 3 3 2 3 3 4 Bank 8 2 2 2 2 2 2 2 2 2 VCCIO TAP 4 4 4 4 4 4 4 4 4 Miscellaneous Dedicated Pins 7 7 7 7 7 7 7 7 7 GND 83 59 83 59 113 83 59 113 166 NC 1 8 1 2 33 1 0 17 29 Reserved 0 2 0 2 4 0 2 4 4 SERDES 14 28 14 28 28 14 28 28 28 VCCA0 2 2 2 2 6 2 2 6 8 VCCA1 0 2 0 2 6 0 2 6 9 VCCAUXA0 2 2 2 2 2 2 2 2 2 VCCAUXA1 0 2 0 2 2 0 2 2 2 VCCA (SERDES) VCCAUX (SERDES) GNDA (SERDES) 26 26 26 26 49 26 26 49 60 Total Balls 285 381 285 381 554 285 381 554 756 4-5 Pinout Information ECP5 Family Data Sheet Pin Information Summary Total DQS Groups LFE5UM-85 381 caBGA 285 csfBGA 381 caBGA 554 caBGA 285 csfBGA 381 caBGA 554 caBGA 756 caBGA Bank 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 Bank 2 10/8 16/8 10/8 16/8 16/8 10/8 17/9 16/8 24/12 Bank 3 14/7 16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/16 Bank 4 0 0 0 0 0 0 0 0 0 Bank 6 13/6 16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/16 Bank 7 8/6 16/8 8/6 16/8 16/8 8/6 16/8 16/8 24/12 Bank 8 0 0 0 0 0 0 0 0 0 45/27 64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56 Bank 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 Bank 2 1 2 1 2 2 1 2 2 3 Bank 3 2 2 2 2 3 2 2 3 4 Bank 4 0 0 0 0 0 0 0 0 0 Bank 6 2 2 2 2 3 2 2 3 4 Bank 7 1 2 1 2 2 1 2 2 3 Bank 8 0 0 0 0 0 0 0 0 0 6 8 6 8 10 6 8 10 14 Total High Speed Differential I/O Pairs DQS Groups (> 11 pins in group) LFE5UM-45 285 csfBGA Pin Type High Speed Differential Input / Output Pairs LFE5UM-25 4-6 Pinout Information ECP5 Family Data Sheet LFE5U Pin Information Summary LFE5U-45 LFE5U-85 381 caBGA 285 csfBGA 381 caBGA 554 caBGA 285 csfBGA 381 caBGA 554 caBGA 756 caBGA Bank 0 6 24 6 27 32 6 27 32 56 Bank 1 6 32 6 33 40 6 33 40 48 Bank 2 21 32 21 32 32 21 34 32 48 Bank 3 28 32 28 33 48 28 33 48 64 Pin Type General Purpose Inputs/Outputs per Bank LFE5U-25 285 csfBGA Bank 4 0 0 0 0 0 0 0 14 24 Bank 6 26 32 26 33 48 26 33 48 64 Bank 7 18 32 18 32 32 18 32 32 48 Bank 8 13 13 13 13 13 13 13 13 13 Total Single-Ended User I/O 118 197 118 203 245 118 205 259 365 VCC 13 20 13 20 24 13 20 24 36 VCCAUX (Core) VCCIO 3 4 3 4 9 3 4 9 8 Bank 0 1 2 1 2 3 1 2 3 4 Bank 1 1 2 1 2 3 1 2 3 4 Bank 2 2 3 2 3 4 2 3 4 4 Bank 3 2 3 2 3 3 2 3 3 4 Bank 4 0 0 0 0 0 0 0 2 2 Bank 6 2 3 2 3 4 2 3 4 4 Bank 7 2 3 2 3 3 2 3 3 4 Bank 8 TAP Miscellaneous Dedicated Pins GND 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 7 7 7 7 7 7 7 7 7 123 59 123 59 113 123 59 113 166 NC 1 8 1 2 33 1 0 17 29 Reserved 4 2 4 2 4 4 2 4 4 SERDES VCCA (SERDES) VCCAUX (SERDES) GNDA (SERDES) Total Balls 0 28 0 28 28 0 28 28 28 VCCA0 0 2 0 2 6 0 2 6 8 VCCA1 0 2 0 2 6 0 2 6 9 VCCAUXA0 0 2 0 2 2 0 2 2 2 VCCAUXA1 0 2 0 2 2 0 2 2 2 0 26 0 26 49 0 26 49 60 285 381 285 381 554 285 381 554 756 4-7 Pinout Information ECP5 Family Data Sheet Pin Information Summary Total DQS Groups LFE5U-85 285 csfBGA 381 caBGA 554 caBGA 285 csfBGA 381 caBGA 554 caBGA 756 caBGA Bank 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 Bank 2 10/8 16/8 10/8 16/8 16/8 10/8 17/9 16/8 24/12 Bank 3 14/7 16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/16 Bank 4 0 0 0 0 0 0 0 0 0 Bank 6 13/6 16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/16 Bank 7 8/6 16/8 8/6 16/8 16/8 8/6 16/8 16/8 24/12 Bank 8 0 0 0 0 0 0 0 0 0 45/27 64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56 Bank 0 0 0 0 0 0 0 0 0 0 Bank 1 0 0 0 0 0 0 0 0 0 Bank 2 1 2 1 2 2 1 2 2 3 Bank 3 2 2 2 2 3 2 2 3 4 Bank 4 0 0 0 0 0 0 0 0 0 Bank 6 2 2 2 2 3 2 2 3 4 Bank 7 1 2 1 2 2 1 2 2 3 Bank 8 0 0 0 0 0 0 0 0 0 6 8 6 8 10 6 8 10 14 Total High Speed Differential I/O Pairs DQS Groups (> 11 pins in group) LFE5U-45 381 caBGA Pin Type High Speed Differential Input / Output Pairs LFE5U-25 285 csfBGA 4-8 ECP5 Family Data Sheet Ordering Information August 2014 Preliminary Data Sheet DS1044 ECP5 Part Number Description LFE5U - XX - X XXXXX X Device Family LFE5U (LFE5 FPGA) Grade C = Commercial I = Industrial Logic Capacity 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs Package MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA Speed 6 = Slowest 7 8 = Fastest LFE5UM - XX - X XXXXX X Device Family LFE5UM (LFE5 FPGA with SERDES) Logic Capacity 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs Grade C = Commercial I = Industrial Package MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA Speed 6 = Slowest 7 8 = Fastest © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1044 Order Info_01.2 Ordering Information ECP5 Family Data Sheet Ordering Part Numbers Commercial Grade Package Pins Temp. LUTs (K) SERDES LFE5U-25F-6MG285C Part number –6 Lead free csfBGA 285 Commercial 24 No LFE5U-25F-7MG285C –7 Lead free csfBGA 285 Commercial 24 No LFE5U-25F-8MG285C –8 Lead free csfBGA 285 Commercial 24 No LFE5U-25F-6BG381C –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 Lead free caBGA 381 Commercial 24 No Lead free caBGA 381 Commercial 24 No LFE5U-25F-7BG381C LFE5U-25F-8BG381C LFE5U-45F-6MG285C LFE5U-45F-7MG285C LFE5U-45F-8MG285C LFE5U-45F-6BG381C LFE5U-45F-7BG381C LFE5U-45F-8BG381C LFE5U-45F-6BG554C LFE5U-45F-7BG554C LFE5U-45F-8BG554C LFE5U-85F-6MG285C LFE5U-85F-7MG285C LFE5U-85F-8MG285C LFE5U-85F-6BG381C LFE5U-85F-7BG381C LFE5U-85F-8BG381C LFE5U-85F-6BG554C LFE5U-85F-7BG554C LFE5U-85F-8BG554C LFE5U-85F-6BG756C LFE5U-85F-7BG756C LFE5U-85F-8BG756C LFE5UM-25F-6MG285C LFE5UM-25F-7MG285C LFE5UM-25F-8MG285C LFE5UM-25F-6BG381C LFE5UM-25F-7BG381C LFE5UM-25F-8BG381C LFE5UM-45F-6MG285C LFE5UM-45F-7MG285C LFE5UM-45F-8MG285C LFE5UM-45F-6BG381C LFE5UM-45F-7BG381C LFE5UM-45F-8BG381C LFE5UM-45F-6BG554C LFE5UM-45F-7BG554C LFE5UM-45F-8BG554C Lead free caBGA 381 Commercial 24 No Lead free csfBGA 285 Commercial 44 No Lead free csfBGA 285 Commercial 44 No Lead free csfBGA 285 Commercial 44 No Lead free caBGA 381 Commercial 44 No Lead free caBGA 381 Commercial 44 No Lead free caBGA 381 Commercial 44 No Lead free caBGA 554 Commercial 44 No Lead free caBGA 554 Commercial 44 No Lead free caBGA 554 Commercial 44 No Lead free csfBGA 285 Commercial 84 No Lead free csfBGA 285 Commercial 84 No Lead free csfBGA 285 Commercial 84 No Lead free caBGA 381 Commercial 84 No Lead free caBGA 381 Commercial 84 No Lead free caBGA 381 Commercial 84 No Lead free caBGA 554 Commercial 84 No Lead free caBGA 554 Commercial 84 No Lead free caBGA 554 Commercial 84 No Lead free caBGA 756 Commercial 84 No Lead free caBGA 756 Commercial 84 No Lead free caBGA 756 Commercial 84 No Lead free csfBGA 285 Commercial 24 Yes Lead free csfBGA 285 Commercial 24 Yes Lead free csfBGA 285 Commercial 24 Yes Lead free caBGA 381 Commercial 24 Yes Lead free caBGA 381 Commercial 24 Yes Lead free caBGA 381 Commercial 24 Yes Lead free csfBGA 285 Commercial 44 Yes Lead free csfBGA 285 Commercial 44 Yes Lead free csfBGA 285 Commercial 44 Yes Lead free caBGA 381 Commercial 44 Yes Lead free caBGA 381 Commercial 44 Yes Lead free caBGA 381 Commercial 44 Yes Lead free caBGA 554 Commercial 44 Yes Lead free caBGA 554 Commercial 44 Yes Lead free caBGA 554 Commercial 44 Yes 5-2 Ordering Information ECP5 Family Data Sheet Part number LFE5UM-85F-6MG285C LFE5UM-85F-7MG285C LFE5UM-85F-8MG285C LFE5UM-85F-6BG381C LFE5UM-85F-7BG381C LFE5UM-85F-8BG381C LFE5UM-85F-6BG554C LFE5UM-85F-7BG554C LFE5UM-85F-8BG554C LFE5UM-85F-6BG756C LFE5UM-85F-7BG756C LFE5UM-85F-8BG756C Grade Package Pins Temp. LUTs (K) SERDES –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 Lead free csfBGA 285 Commercial 84 Yes Lead free csfBGA 285 Commercial 84 Yes Lead free csfBGA 285 Commercial 84 Yes Lead free caBGA 381 Commercial 84 Yes Lead free caBGA 381 Commercial 84 Yes Lead free caBGA 381 Commercial 84 Yes Lead free caBGA 554 Commercial 84 Yes Lead free caBGA 554 Commercial 84 Yes Lead free caBGA 554 Commercial 84 Yes Lead free caBGA 756 Commercial 84 Yes Lead free caBGA 756 Commercial 84 Yes Lead free caBGA 756 Commercial 84 Yes 5-3 Ordering Information ECP5 Family Data Sheet Industrial Part number LFE5U-25F-6MG285I LFE5U-25F-7MG285I LFE5U-25F-8MG285I LFE5U-25F-6BG381I LFE5U-25F-7BG381I LFE5U-25F-8BG381I LFE5U-45F-6MG285I LFE5U-45F-7MG285I LFE5U-45F-8MG285I LFE5U-45F-6BG381I LFE5U-45F-7BG381I LFE5U-45F-8BG381I LFE5U-45F-6BG554I LFE5U-45F-7BG554I LFE5U-45F-8BG554I LFE5U-85F-6MG285I LFE5U-85F-7MG285I LFE5U-85F-8MG285I LFE5U-85F-6BG381I LFE5U-85F-7BG381I LFE5U-85F-8BG381I LFE5U-85F-6BG554I LFE5U-85F-7BG554I LFE5U-85F-8BG554I LFE5U-85F-6BG756I LFE5U-85F-7BG756I LFE5U-85F-8BG756I LFE5UM-25F-6MG285I LFE5UM-25F-7MG285I LFE5UM-25F-8MG285I LFE5UM-25F-6BG381I LFE5UM-25F-7BG381I LFE5UM-25F-8BG381I LFE5UM-45F-6MG285I LFE5UM-45F-7MG285I LFE5UM-45F-8MG285I LFE5UM-45F-6BG381I LFE5UM-45F-7BG381I LFE5UM-45F-8BG381I LFE5UM-45F-6BG554I LFE5UM-45F-7BG554I LFE5UM-45F-8BG554I LFE5UM-85F-6MG285I LFE5UM-85F-7MG285I Grade Package Pins Temp. LUTs (K) SERDES –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 –6 –7 Lead free csfBGA 285 Industrial 24 No Lead free csfBGA 285 Industrial 24 No Lead free csfBGA 285 Industrial 24 No Lead free caBGA 381 Industrial 24 No Lead free caBGA 381 Industrial 24 No Lead free caBGA 381 Industrial 24 No Lead free csfBGA 285 Industrial 44 No Lead free csfBGA 285 Industrial 44 No Lead free csfBGA 285 Industrial 44 No Lead free caBGA 381 Industrial 44 No Lead free caBGA 381 Industrial 44 No Lead free caBGA 381 Industrial 44 No Lead free caBGA 554 Industrial 44 No Lead free caBGA 554 Industrial 44 No Lead free caBGA 554 Industrial 44 No Lead free csfBGA 285 Industrial 84 No Lead free csfBGA 285 Industrial 84 No Lead free csfBGA 285 Industrial 84 No Lead free caBGA 381 Industrial 84 No Lead free caBGA 381 Industrial 84 No Lead free caBGA 381 Industrial 84 No Lead free caBGA 554 Industrial 84 No Lead free caBGA 554 Industrial 84 No Lead free caBGA 554 Industrial 84 No Lead free caBGA 756 Industrial 84 No Lead free caBGA 756 Industrial 84 No Lead free caBGA 756 Industrial 84 No Lead free csfBGA 285 Industrial 24 Yes Lead free csfBGA 285 Industrial 24 Yes Lead free csfBGA 285 Industrial 24 Yes Lead free caBGA 381 Industrial 24 Yes Lead free caBGA 381 Industrial 24 Yes Lead free caBGA 381 Industrial 24 Yes Lead free csfBGA 285 Industrial 44 Yes Lead free csfBGA 285 Industrial 44 Yes Lead free csfBGA 285 Industrial 44 Yes Lead free caBGA 381 Industrial 44 Yes Lead free caBGA 381 Industrial 44 Yes Lead free caBGA 381 Industrial 44 Yes Lead free caBGA 554 Industrial 44 Yes Lead free caBGA 554 Industrial 44 Yes Lead free caBGA 554 Industrial 44 Yes Lead free csfBGA 285 Industrial 84 Yes Lead free csfBGA 285 Industrial 84 Yes 5-4 Ordering Information ECP5 Family Data Sheet Part number LFE5UM-85F-8MG285I LFE5UM-85F-6BG381I LFE5UM-85F-7BG381I LFE5UM-85F-8BG381I LFE5UM-85F-6BG554I LFE5UM-85F-7BG554I LFE5UM-85F-8BG554I LFE5UM-85F-6BG756I LFE5UM-85F-7BG756I LFE5UM-85F-8BG756I Grade Package Pins Temp. LUTs (K) SERDES –8 –6 –7 –8 –6 –7 –8 –6 –7 –8 Lead free csfBGA 285 Industrial 84 Yes Lead free caBGA 381 Industrial 84 Yes Lead free caBGA 381 Industrial 84 Yes Lead free caBGA 381 Industrial 84 Yes Lead free caBGA 554 Industrial 84 Yes Lead free caBGA 554 Industrial 84 Yes Lead free caBGA 554 Industrial 84 Yes Lead free caBGA 756 Industrial 84 Yes Lead free caBGA 756 Industrial 84 Yes Lead free caBGA 756 Industrial 84 Yes 5-5 ECP5 Family Data Sheet Supplemental Information August 2015 Preliminary Data Sheet DS1044 For Further Information A variety of technical notes for the ECP5 family are available. • TN1184, LatticeECP3 and ECP5 Soft Error Detection (SED)/Correction (SEC) Usage Guide • TN1260, ECP5 sysCONFIG Usage Guide • TN1261, ECP5 SERDES/PCS Usage Guide • TN1262, ECP5 sysIO Usage Guide • TN1263, ECP5 sysClock PLL/DLL Design and Usage Guide • TN1264, ECP5 Memory Usage Guide • TN1265, ECP5 High-Speed I/O Interface • TN1266, Power Consumption and Management for ECP5 Devices • TN1267, ECP5 sysDSP Usage Guide For further information on interface standards refer to the following websites: • JEDEC Standards (LVTTL, LVCMOS, SSTL): www.jedec.org • PCI: www.pcisig.com © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1044 Further Info_01.2 ECP5 Family Data Sheet Revision History August 2015 Preliminary Data Sheet DS1044 Date Version Section August 2015 1.3 Introduction Change Summary Updated Features section. — Removed SMPTE3G under Embedded SERDES. — Added Single Event Upset (SEU) Mitigation Support. Updated Introduction section. Removed SMPTE protocol in fifth paragraph. Architecture General update. DC and Switching Characteristics General update. Pinout Information Updated Signal Descriptions section. Revised the descriptions of the following signals: — P[L/R] [Group Number]_[A/B/C/D] — P[T/B][Group Number]_[A/B] — D4/IO4 (Previously named D4/MOSI2/IO4) — D5/IO5 (Previously named D5/MISO/IO5) — VCCHRX_D[dual_num]CH[chan_num] — VCCHTX_D[dual_num]CH[chan_num] Supplemental Information August 2014 1.2 All Introduction Added TN1184 reference. Changed document status from Advance to Preliminary. Updated Features section. — Deleted Serial RapidIO protocol under Embedded SERDES. — Corrected data rate under Pre-Engineered Source Synchronous I/O. Updated Introduction section. — Changed DD3. LPDDR3 to DDR2/3, LPDDR2/3. — Mentioned transmit de-emphasis “pre- and post-cursors”. Architecture Updated Architecture Overview section. — Revised description of PFU blocks. — Specified SRAM cell settings in describing the control of SERDES/ PCS duals. Updated SERDES and PCS (Physical Coding Sublayer) section. — Changed PCI Express 2.0 to PCI Express Gen1 and Gen2. — Deleted Serial RapidIO protocol. — Updated Table 2-13, LFE5UM SERDES Standard Support. — Updated Table 2-15, LFE5UM Mixed Protocol Support. Updated On-Chip Oscillator section. — Deleted “130 MHz +/– 15% CMOS” oscillator. — Updated Table 2-16, Selectable Master Clock (MCCLK) Frequencies During Configuration (Nominal) DC and Switching Characteristics Updated Absolute Maximum Ratings section. Added supply voltages VCCA and VCCAUXA. Updated sysI/O Recommended Operating Conditions section. Revised HSULD12D VCCIO values and removed footnote 1. Updated sysI/O Single-Ended DC Electrical Characteristics section. Revised some values for SSTL15 _I, SSTL15 _II, SSTL135_I, SSTL15_II, and HSUL12. Updated ECP5 External Switching Characteristics section. Changed parameters to tSKEW_PR VCCA and tSKEW_EDGE and added LFE5-85 as device. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 DS1044 Revision History Revision History ECP5 Family Data Sheet Date Version Section Change Summary Updated ECP5 Family Timing Adders section. Added SSTL135_II buffer type data. Removed LVCMOS33_20mA, LVCMOS25_20mA, LVCMOS25_16mA, LVCMOS25D_16mA, and LVCMOS18_16mA buffer types. Changed buffer type to LVCMOS12_4mA and LVCMOS12_8mA. Updated ECP5 Maximum I/O Buffer Speed section. Revised Max. values. Updated sysCLOCK PLL Timing section. Revised tDT Min. and Max. values. Revised tOPJIT Max. value. Revised number of samples in footnote 1. Updated SERDES High-Speed Data Transmitter1 section. Updated Table 3-6, Serial Output Timing and Levels and Table 3-7, Channel Output Jitter. SERDES High Speed Data Receiver section. Updated Table 3-9, Serial Input Data Specifications, Table 3-10, Receiver Total Jitter Tolerance Specification, and Table 3-11, Periodic Receiver Jitter Tolerance Specification. Modified section heading to XAUI/CPRI LV E.30 Electrical and Timing Characteristics. Updated Table 3-12, Transmit and Table 3-13, Receive and Jitter Tolerance. Modified section heading to CPRI LV E.24 Electrical and Timing Characteristics. Updated Table 3-14, Transmit and Table 3-15, Receive and Jitter Tolerance. Modified section heading to Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics. Updated Table 3-16, Transmit and Table 3-17, Receive and Jitter Tolerance. June 2014 1.1 Ordering Information March 2014 1.0 All Updated ECP5 Part Number Description and Ordering Part Numbers sections. Initial release. 7-2