753AA

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
VSOIC8 NB
CASE 753AA
ISSUE O
8
1
SCALE 1:1
D
A
8
NOTE 5
DATE 16 OCT 2012
2X
F
0.10 C D
5
NOTE 6
E
E1
A1
NOTE 4
L2
2X 4 TIPS
0.20 C
L
4
1
NOTE 5
8X
B
b
0.25
DETAIL A
M
C
C A-B D
TOP VIEW
2X
NOTE 4
D
0.10 C A-B
0.10 C
A
DETAIL A
8X
0.10 C
e
SIDE VIEW
C
SEATING
PLANE
END VIEW
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL
CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15mm PER SIDE. DIMENSION E DOES
NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25mm PER
SIDE. DIMENSIONS D AND E ARE DETERMINED AT
DATUM F.
5. DATUMS A AND B ARE TO BE DETERMINED AT
DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
DIM
A
A1
b
c
D
E
E1
e
L
L2
MILLIMETERS
MIN
MAX
0.65
0.85
−−−
0.05
0.31
0.51
0.17
0.25
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.40
1.27
0.25 BSC
GENERIC
MARKING DIAGRAM*
8
RECOMMENDED
SOLDERING FOOTPRINT*
XXXXXXXXX
ALYWXG
G
1
8X 1.52
7.00
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
1
8X
1.27
PITCH
0.60
DIMENSION: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
STATUS:
98AON81076E
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
VSOIC8 NB
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON81076E
PAGE 2 OF 2
ISSUE
O
REVISION
RELEASED FOR PRODUCTION. REQ. BY C. TAN.
DATE
16 OCT 2012
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. O
Case Outline Number:
753AA