LE25S81A Serial Flash Memory 8M-bit (1024K x 8) www.onsemi.com 1. Overview The LE25S81A is a SPI bus flash memory device with a 8M bit (1024K × 8-bit) configuration. It uses a single power supply. While making the most of the features inherent to a serial flash memory device, the LE25S81A is housed in an 8-pin ultra-miniature package. All these features make this device ideally suited to storing program in applications such as portable information devices, which are required to have increasingly more compact dimensions. The LE25S81A also has a small sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and conventional EEPROMs cannot handle due to insufficient capacity. SOIC 8, 150 mils VSOIC8 NB 2. Features • Operations power supply : 1.65 to 1.95V supply voltage range • Operating frequency : 70MHz (max) • Temperature range : –40 to +90°C • Serial interface : SPI mode 0, mode 3 supported • Electronic Identification : JDEC ID, Device ID, Serial Flash Discoverable Parameter (SFDP) • Sector size : 4K bytes/small sector, 64K bytes/sector • Erase functions : small sector erase(SSE), sector erase(SE), chip erase(CHE) • Page program function : 256 bytes/page • Status functions : Ready/Busy information, protect information • Low operation current : 5.0mA (Low-power program mode, typ), 3.0mA(Low-Power Read mode, typ) • Erase time : 10ms(SSE, typ), 15ms(SE, typ), 120ms(CHE, typ) • Page program time (tPP) : 0.3ms/256 bytes (typ), 0.5ms/256 bytes (max) • Emergency shutdown of the current consumption : transition to a standby state in less than 20us from the active by Write Suspend : transition to a standby state in less than 40us from the active by Software Reset • High reliability : 100,000 erase/program cycles : 20 years data retention period • Package : LE25S81AMD SOIC8, 150 mils CASE 751BD-01 : LE25S81AFD VSOIC8 NB CASE 753AA : KGD N/A * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 51 of this data sheet. © Semiconductor Components Industries, LLC, 2015 September 2015 - Rev. 3 1 Publication Order Number : LE25S81A/D LE25S81A 3. Package Types and Pin Configurations CS 1 8 VDD SO (SIO1) 2 7 HOLD WP 3 6 SCK VSS 4 5 SI (SIO0) Top view 4 Pad No. Name 1 CS 2 SO (SIO1) 3 WP 4 VSS 5 SI (SIO0) 6 SCK 7 HOLD 8 VDD 3 2 1 SOIC8 (LE25S81AMD) VSOIC8 NB (LE25S81AFD) 5 6 7 KGD www.onsemi.com 2 8 LE25S81A 4. Package Dimensions unit : mm LE25S81AMDTWG SOIC 8, 150 mils CASE 751BD-01 ISSUE O SYMBOL E1 E MIN MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. www.onsemi.com 3 LE25S81A Package Dimensions unit : mm LE25S81AFDTWG VSOIC8 NB CASE 753AA ISSUE O D A 8 NOTE 5 2X 0.10 C D 5 F NOTE 6 E E1 A1 NOTE 4 L2 2X 4 TIPS 0.20 C L 4 1 NOTE 5 8X B b 0.25 C DETAIL A M C A-B D TOP VIEW 2X NOTE 4 D 0.10 C A-B 0.10 C A DETAIL A 8X 0.10 C e SIDE VIEW C SEATING PLANE END VIEW SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSION E DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DATUMS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 b c D E E1 e L L2 MILLIMETERS MIN MAX 0.65 0.85 0.05 0.31 0.51 0.17 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 0.25 BSC GENERIC MARKING DIAGRAM* 8 RECOMMENDED SOLDERING FOOTPRINT* XXXXXXXXX ALYWX 1 8X 1.52 7.00 XXXXX A L Y W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) 1 8X 1.27 PITCH 0.60 DIMENSION: MILLIMETERS *This information is generic. Please refer to device data sheet for actual part *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 4 LE25S81A 5. Pin Description Symbol CS Pin Name IO Chip select I Serial clock I Description The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. This pin controls the data input/output timing. SCK The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI (SIO0) SO (SIO1) WP HOLD Serial data input (Serial data input output) Serial data output (Serial data input output) The data and addresses are input from this pin, and latched internally synchronized to the rising I/O edge of the serial clock. (It changes into input/output pin during the Dual operation.) The data stored inside the device is output from this pin synchronized to the falling edge of the I/O serial clock. ( It changes into input/output pin during the Dual operation.) Write protect I The Write Status Register Protect (SRWP) takes effect when the logic level of this pin is low. Hold I Serial communication is suspended when the logic level of this pin is low. NC No Connection VDD Power supply This pin supplies the 1.65 to 1.95V supply voltage. VSS Ground This pin supplies the 0V supply voltage. www.onsemi.com 5 LE25S81A 6. Block Diagram 8M Bit Flash EEPROM Cell Array Power Circuit Energyconsumption Control Unit Memory Control Logic Decoder Logic & Serial-parallel conversion Logic Command Logic Serial interface CS SCK SI (SIO0) SO (SIO1) www.onsemi.com 6 WP HOLD LE25S81A 7. Device Operation 7-1. Standard SPI Modes The read, erase, program and other required functions of the device are executed through the command registers. The serial I/O corrugate is shown in "Figure 1. SPI Modes" and the command list are shown in "Table.1-1. Command Settings (Standard SPI)". At the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute operation according to the command that is input. The LE25S81A supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 1. SPI Modes CS Mode3 SCK Mode0 8CLK SI 1st byte MSB (Bit7) Nth byte 2nd byte LSB (Bit0) High Impedance DATA SO DATA 7-2. Dual SPI Modes The LE25S81A supports Dual SPI operations when using "Dual Output Read (RDDO: 3Bh)", "Dual I/O Read (RDIO: BBh)". The SI and SO pins change into the input/output pin (SIOx) during the Dual SPI modes. The command list is shown in "Table.1-2. Command Settings (Dual SPI)". Pin Configurations at Dual SPI Mode Standard SPI Dual SPI SI SIO0 SO SIO1 www.onsemi.com 7 LE25S81A Table 1-1. Command Settings (Standard SPI) Command Description 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Nth byte (clock number) (0 - 7) (8 - 15) (16- 23) (24 - 31) (32 - 39) (40 - 47) (8N-8 to 8N-1) WREN Write enable 06h WRDI Write disable 04h RDSR Read Status Register 05h WRSR Write Status Register 01h DATA RDLP Low -Power Read (Max: 40MHz) 03h A23-A16 A15-A8 A7-A0 RD 0Bh A23-A16 A15-A8 A7-A0 X RDHS SSE High-Speed Read (Max: 70MHz) Small Sector Erase (4KB) 20h / D7h A23-A16 A15-A8 A7-A0 SE Sector Erase (64KB) D8h A23-A16 A15-A8 A7-A0 CHE Chip Erase (8M bits) 60h / C7h A23-A16 A15-A8 A7-A0 Manufacture Memory Capacity (62h) Type (16h) (14h) ABh X X X 5Ah A23-A16 A15-A8 A7-A0 X PP Normal Page Program 02h PPL Low-Power Page Program 0Ah WSUS Write Suspend B0h RESM Resume 30h Read JEDEC ID 9Fh RJID RID RSFDP DP EDP RSTEN RST Read Device ID (Exit power down mode) Read SFDP (Max: 70MHz) Deep Power down Exit Deep Power down PD (5) (7) RD (5) RD (5) RD (5) RD (5) PD (7) PD (7) RD (5) RD (5) Device ID (87h) B9h ABh Reset Enable 66h Reset 99h Table 1-2. Command Settings (Dual SPI) --- Max: 66MHz Command RDDO Description 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Nth byte (clock number) (0 - 7) (8 - 15) (16- 23) (24 - 31) (32 - 39) (40 - 47) (8N-8 to 8N-1) 3Bh A23-A16 A15-A8 A7-A0 Z Dual Output Read RDD (6) RDD (6) RDD (6) RDD (6) (8) RDIO Dual I/O Read BBh A23-A8 A7-A0 , (8) X, Z RDD (6) Note: 1. "X" signifies "don’t care" (that is to say, any value may be input). 2. "Z" signifies "high-impedance". 3. The "h" following each code indicates that the number given is in hexadecimal notation. 4. Addresses A23 to A20 for all commands are "Don't care". 5. "RD" Read data on SO. 6. "RDD" Dual Read data: SIO0=(Bit6, Bit4, Bit2, Bit0) SIO1=(Bit7, Bit5, Bit3, Bit1) 7. "PD" Page Program data on SO. 8. Dual SPI address input from SIO0 and SIO1: SIO0=(A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0) SIO1=(A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1) www.onsemi.com 8 RDD (6) LE25S81A 8. Memory Organization Table 2. Memory Organization 8M Bits Sector (64KB) Symbol :SE 15 14 to 6 5 4 3 2 1 small sector (4KB) Symbol :SSE SSE[255] to SSE[240] SSE[239] to SSE[96] SSE[95] to SSE[80] SSE[79] to SSE[64] SSE[63] to SSE[48] SSE[47] to SSE[32] SSE[31] to SSE[16] SSE[15] to SSE[4] address space (A23 to A0) SSE[3] 0 SSE[2] SSE[1] SSE[0] 0FF000h 0FFFFFh 0F0000h 0EF000h 0F0FFFh 0EFFFFh 060000h 05F000h 060FFFh 05FFFFh 050000h 04F000h 050FFFh 04FFFFh 040000h 03F000h 040FFFh 03FFFFh 030000h 02F000h 030FFFh 02FFFFh 020000h 01F000h 020FFFh 01FFFFh 010000h 00F000h 010FFFh 00FFFFh 004000h 003800h 003000h 002800h 002000h 001800h 001000h 000800h 000000h 004FFFh 003FFFh 0037FFh 002FFFh 0027FFh 001FFFh 0017FFh 000FFFh 0007FFh www.onsemi.com 9 LE25S81A 9. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read by Read Status Register (RDSR) and the protect information can be rewritten by Write Status Register (WRSR). There are 8 bits in total, and "Table 3. Status registers" gives the significance of each bit. Table 3. Status Registers Bit Bit0 Bit1 Name RDY Logic Function 0 Ready 1 Erase/Program 0 Write disabled 1 Write enabled Power-on Time Information 0 WEN 0 0 Bit2 BP0 1 Bit3 0 Block protect information 1 Protected area switch BP1 Nonvolatile information 0 Bit4 BP2 1 Bit5 0 Block protect 1 Upper side/Lower side switch 0 Erase/Program is not suspended 1 Erase/Program suspended 0 Write Status Register enabled 1 Write Status Register disabled TB Bit6 SUS Bit7 SRWP Nonvolatile information 0 Nonvolatile information Note: All non-volatile bits of the status registers-1 are set "0" in the factory. www.onsemi.com 10 LE25S81A 9-1. Contents of each status register 9-1-1. RDY (bit 0) The RDY register is for detecting the write (Program, Erase and Write Status Register) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. 9-1-2. WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable (WREN) and write disable (WRDI). By inputting the write enable (WREN: 06h), WEN can be set to "1" by inputting the write disable (WRDI: 04h), it can be set to "0." In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. • At power-on • Upon completion of Erase (SSE, SE, or CHE) • Upon completion of Page Program (PP or PPL) • Upon completion of Write Status Register (WRSR) * If a write operation has not been performed inside the LE25S81A because, for instance, the command input for any of the write operations (SSE, SE, CHE, PP, PPL or WRSR) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. 9-1-3. BP0, BP1, BP2, TB (bits 2, 3, 4, 5) Block Protect: BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 4. Protected Level Setting Conditions". BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address area or lower-order address area. Table 4. Protection Level Setting Conditions Status Register Bits Protected Level Protected Block Protected Area TB BP2 BP1 BP0 0 Whole area unprotected X 0 0 0 None T1 Upper side 1/16 protected 0 0 0 1 F0000h to FFFFFh T2 Upper side 1/8 protected 0 0 1 0 E0000h to FFFFFh T3 Upper side 1/4 protected 0 0 1 1 C0000h to FFFFFh T4 Upper side 1/2 protected 0 1 0 0 80000h to FFFFFh B1 Lower side 1/16 protected 1 0 0 1 00000h to 0FFFFh B2 Lower side 1/8 protected 1 0 1 0 00000h to 1FFFFh B3 Lower side 1/4 protected 1 0 1 1 00000h to 3FFFFh B4 Lower side 1/2 protected 1 1 0 0 00000h to 7FFFFh 5 Whole area protected X 1 0 1 00000h to FFFFFh 5 Whole area protected X 1 1 X 00000h to FFFFFh Note: Chip Erase is enabled only when the protection level is 0. www.onsemi.com 11 LE25S81A 9-1-4. SUS (bit 6) The SUS register indicates when Erase/Program operation has been suspended. The SUS becomes "1" when the Erase/Program operation has been suspended (WSUS: B0h). The SUS is cleared to"0" by Resume (RESM:30h) or re-erase/program (SSE, SE, CHE, PP, PPL). 9-1-5. SRWP (bit 7) Write Status Register protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the Write Status Register (WRSR: 01h) is ignored, and status registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5. SRWP Setting Conditions". Table 5. SRWP Setting Conditions WP Pin SRWP Status Register Protect State 0 Unprotected 0 1 Protected 0 Unprotected 1 Unprotected 1 www.onsemi.com 12 LE25S81A 10. Description of Commands and Operations A detailed description of the functions and operations corresponding to each command is presented below. 10-1. Read Status Register (RDSR) The contents of the status registers can be read using the Read Status Register (RDSR). This command can be executed even during the following operations. • Erase (SSE, SE or CHE) • Page Program (PP or PPL) • Write Status Register (WRSR) "Figure 2. Read Status Register (RDSR)" shows the timing waveforms. The sequence of RDSR operation : CS goes to low input RDSR command (05h) Status Register data (SRWP, SUS, TB, BP2, BP1, BP0,WEN, RDY) out on SO completed by CS=high * The data output starts from the falling edge of SCK(7th clock) This command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK). If the clock input is continued after bit0 (RDY) has been output, the data is output by returning to bit7 (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by this command at any time (even during a program, erase cycle). By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state Figure 2. Read Status Register (RDSR) CS Mode 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode 0 8CLK SI 05h MSB SO High Impedance DATA MSB DATA MSB ● DATA: Status Resister, "Table 3 Status Register" www.onsemi.com 13 DATA MSB LE25S81A 10-2. Write Status Register (WRSR) The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using this command. bit0 ( RDY), bit1 (WEN) and bit6 (SUS) are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down. "Figure 3. Write Status Register (WRSR)" shows the timing waveforms. "Figure 31. Write Status Register Flowcharts" shows the flowcharts. The sequence of WRSR operation : CS goes to low input WRSR command (01h) Status Register data input on SI CS goes to high (be executed by the rising CS edge) Erase and program are performed automatically inside the device by Write Status Register. So that erasing or other processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, BP2, TB and SRWP can be rewritten. Since bits bit0 (RDY), bit1 (WEN), bit 6 (SUS) of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Write Status Register ends can be detected by RDY of Read Status Register (RDSR). To initiate Write Status Register, the logic level of the WP pin must be set high and status register WEN must be set to "1". Self-timed Write Cycle Figure 3. Write Status Register (WRSR) tWRSR CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 Mode0 8CLK SI 01h DATA MSB SO High Impedance www.onsemi.com 14 LE25S81A 10-3. Write Enable (WREN) Before performing any of the operations listed below, the device must be placed in the write enable state. • Erase (SSE, SE, CHE or CHE) • Page Program (PP or PPL) • Write Status Register (WRSR) Operation is the same as for setting status register WEN to "1", and the state is enabled by this command. "Figure 4. Write Enable (WREN)" shows the timing waveforms. The sequence of WREN operation : CS goes to low input WREN command (06h) CS goes to high (be executed by the rising CS edge) Figure 4. Write Enable (WREN) CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 06h MSB SO High Impedance www.onsemi.com 15 LE25S81A 10-4. Write Disable (WRDI) This command sets status register WEN to "0" to prohibit unintentional writing. The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable (WREN: 06h). "Figure 5. Write Disable (WRDI)" shows the timing waveforms. The sequence of WRDI operation : CS goes to low input WRDI command (04h) CS goes to high (be executed by the rising CS edge) Figure 5. Write Disable (WRDI) CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 04h MSB SO High Impedance www.onsemi.com 16 LE25S81A Standard SPI Read There are two Read commands, "Low-Power Read (RDLP: 03h)" and "High-Speed Read (RDHS: 0Bh)". 10-5. Standard SPI Read There are two Read commands, Low-Power Read (RDLP) and High-Speed Read (RDHS). 10-5-1. Low-Power Read command (RDLP) Maximum Clock frequency: 40MHz This command is for reading data out. "Figure 6. Low-Power Read (RDLP)" shows the timing waveforms. The sequence of RDLP operation : CS goes to low input RDLP command (03h) 3 Byte address (A23-A0) input on SI the corresponding data out on SO continuous data out (n-byte) completed by CS=high * The data output starts from the falling edge of SCK(31th clock) The Address is latched on rising edge of SCK, and the corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the highest address (0FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 6. Low-Power Read (RDLP) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 Mode0 8CLK SI 03h Add Add Add (A23-A16) (A15-A8) (A7-A0) Byte 1 SO High Impedance DATA MSB ● Address A23 to A20 are "Don't care". www.onsemi.com 17 Byte 2 DATA MSB Byte 3 DATA MSB LE25S81A 10-5-2. High-Speed Read command (RDHS) Maximum Clock frequency: 70MHz This command is for reading data out at the high frequency operation. "Figure 7. High-Speed Read (RDHS)" shows the timing waveforms. The sequence of RDHS operation : CS goes to low input RDHS command (0Bh) 3 Byte address (A23-A0) input on SI 1 byte dummy cycle the corresponding data out on SO continuous data out (n-byte) completed by CS=high * The data output starts from the falling edge of SCK(39th clock) The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the highest address (0FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 7. High-Speed Read (RDHS) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI 0Bh Add Add Add (A23-A16) (A15-A8) (A7-A0) X MSB Byte 1 SO High Impedance DATA MSB ● Address A23 to A20 are "Don't care". www.onsemi.com 18 Byte 2 DATA MSB Byte 3 DATA MSB LE25S81A 10-6. Dual read There are two Dual read commands, the Dual Output Read (RDDO) and the Dual I/O Read (RDIO). They achieve the twice speed-up from "High-Speed Read (RDHS: 0Bh)". The command list is shown in "Table.1-2. Command Settings (Dual SPI)" Pin Configurations at Dual SPI Mode Standard SPI Dual SPI SI SIO0 SO SIO1 10-6-1. Dual Output Read command (RDDO) Maximum Clock frequency: 66MHz The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the data output x2 bit and has achieved a high-speed output. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1. "Figure 8. Dual Output Read (RDDO)" shows the timing waveforms. The sequence of RDDO operation : CS goes to low input RDDO command (3Bh) 3 Byte address (A23-A0) input on SI 1 byte dummy cycle the corresponding data out on SI/SIO0 and SO/SIO1 continuous data out (n-byte) per 4clock completed by CS=high * The data output starts from the falling edge of SCK(39th clock) Output Data SI/SIO0 bit6,4,2,0 SO/SIO1 bit7,5,3,1 The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued after the internal address arrives at the highest address (0FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 8. Dual Output Read (RDDO) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 47 Mode0 8CLK 3Bh SIO0 Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SIO1 dummy bit Byte 2 Byte 3 DATA0 DATA0 DATA0 Byte 1 4CLK High Impedance 4CLK DATA1 DATA1 DATA1 MSB MSB MSB DATA0: bit6,bit4,bit2,bit0 DATA1: bit7,bit5,bit3,bit1 ● Address A23 to A20 are "Don't care". www.onsemi.com 19 LE25S81A 10-6-2. Dual I/O Read command (RDIO) Maximum Clock frequency: 66MHz The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the address input and data output x2 bit and has achieved a high-speed output. Add1 (A23, A21, -, A3 and A1) is input from SIO1 and Add0 (A22, A20, -, A2 and A0) is input from SIO0. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1. "Figure 9. Dual I/O Read (RDIO)" shows the timing waveforms. The sequence of RDIO operation : CS goes to low input RDIO command (BBh) 3 Byte address (A23-A0) input on SI/SIO0 and SO/SIO1 by 12 clock cycle 2 dummy clock (SI/SIO0 and SO/SIO1 are don’t care) + 2 dummy clock (must set SI/SIO0 and SO/SIO1 high impedance) the corresponding data out on SI/SIO0 and SO/SIO continuous data out (n-byte) per 4clock completed by CS=high * The data output starts from the falling edge of SCK(23th clock) Input Address Output Data SI/SIO0 A22,20,18 --,A2,A0 bit6,4,2,0 SO/SIO1 A23,21,19 --,A3,A1 bit7,5,3,1 The Address is latched on rising edge of SCK. It is necessary to add 4 dummy clocks after address is latched, 2CLK of the latter half of the dummy clock is in the state of high impedance, the controller can switch I/O for this period. The corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued after the internal address arrives at the highest address (0FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 9. Dual I/O Read (RDIO) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 19 20 21 22 23 24 31 Mode0 dummy bit 8CLK BBh SIO0 MSB SIO1 27 28 High Impedance Add1:A22,A20-A2,A0 12CLK Add2:A23,A21-A3,A1 X Byte2 Byte3 DATA0 DATA0 DATA0 Byte 1 4CLK 2CLK 2CLK X DATA1 DATA1 DATA1 MSB MSB MSB DATA0: bit6,bit4,bit2,bit0 DATA1: bit7,bit5,bit3,bit1 ● Address A23 to A20 are "Don't care". www.onsemi.com 20 LE25S81A 10-7. Small Sector Erase (SSE) Small Sector Erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 10. Small Sector Erase (SSE)" shows the timing waveforms. "Figure 32. Small Sector Erase Flowcharts" shows the flowcharts. The sequence of SSE operation : CS goes to low input SSE command (20h or D7h) 3 Byte address (A23-A0) input on SI CS goes to high (be executed by the rising CS edge) * A19 to A12 are valid address After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSSE). The end of erase operation can also be detected by status register (RDY). Figure 10. Small Sector Erase (SSE) Self-timed Erase Cycle tSSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI 20h / D7h Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SO High Impedance ● Address A23 to A20, A11 to A0 are "Don't care". www.onsemi.com 21 LE25S81A 10-8. Sector Erase (SE) Sector Erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 11. Sector Erase (SE)" shows the timing waveforms. "Figure 33. Sector Erase Flowcharts" shows the flowcharts. The sequence of SE operation : CS goes to low input SE command (D8h) 3 Byte address (A23-A0) input on SI CS goes to high (be executed by the rising CS edge) * A19 to A16 are valid address After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by status register (RDY). Figure 11. Sector Erase (SE) Self-timed Erase Cycle tSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI D8h Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SO High Impedance ● Address A23 to A20 , A15 to A0 are "Don't care. www.onsemi.com 22 LE25S81A 10-9. Chip Erase (CHE) Chip Erase is an operation that sets the memory cell data in all sectors to "1". "Figure 12. Chip Erase (CHE)" shows the timing waveforms. "Figure 34. Chip Erase Flowcharts" shows the flowcharts. The sequence of CHE operation : CS goes to low input CHE command (60h or C7h) CS goes to high (be executed by the rising CS edge) After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by status register (RDY). Figure 12. Chip Erase (CHE) Self-timed Erase Cycle tCHE CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 60h / C7h MSB SO High Impedance www.onsemi.com 23 LE25S81A 10-10. Page Program 10-10-1. Normal Page Program (PP) 10-10-2. Low-Power Page Program (PPL) There are two Page Program commands, Normal program (PP: 02h ) and Low-Power program (PPL: 0Ah) These two commands are completely functionally the same. By selecting the Low-Power program (PPL), the operating current is reduced, but the program cycle time is extended. (Iccpp > Iccppl , tPPL > tPP) Page Program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: A19 to A8). Before initiating Page Program, the data on the page concerned must be erased using Small Sector Erase, Sector Erase, or Chip Erase. Page Program (PP, PPL) allows only previous erased data (FFh). "Figure 13. Normal Page Program (PP)". "Figure 14. Low-power Page Program (PPL)" shows the timing waveforms. "Figure 35. Page Program Flowcharts" shows the flowcharts. The sequence of PP or PPL operation : CS goes to low input PP command (02h) or PPL command (0Ah) 3 Byte address (A23-A0) input on SI n-Byte data input on SI CS goes to high (be executed by the rising CS edge) The program data must be loaded in 1-byte increments. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. After the correct input sequence the internal program operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tPP or tPPL). The end of program operation can also be detected by status register (RDY). Self-timed Program Cycle Figure 13. Normal Page Program (PP) tPP CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI 02h Add Add Add (A23-A16) (A15-A8) (A7-A0) Byte 1 Byte 2 Byte 256 PD PD PD MSB High Impedance SO ● Address A23 to A20 are "Don't care". Self-timed Program Cycle Figure 14. Low-Power Page Program (PPL) tPPL CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI 0Ah Add Add Add (A23-A16) (A15-A8) (A7-A0) MSB SO High Impedance ● Address A23 to A20 are "Don't care". www.onsemi.com 24 Byte 1 Byte 2 Byte 256 PD PD PD LE25S81A 10-11. Write Suspend (WSUS) The Write Suspend (WSUS) allow the system to interrupt Small Sector Erase (SSE), Sector Erase (SE), Chip Erase (CHE) or Page Program (PP, PPL). "Figure 15. Write Suspend (WSUS)" shows the timing waveforms. The sequence of WSUS operation : CS goes to low input WSUS command (B0h) CS goes to high (be executed by the rising CS edge) After the command has been input, the device becomes consumption current equivalent to standby within 20 us. The recovery time (tRSUS) is needed before next command from suspend. The internal operation status could be checked by using status register RDY bit or SUS bit, but the device will not accept another command until it is ready. • The Write Suspend is valid Erase cycle (SSE, SE and CHE) or Program cycle (PP, PPL). • If the Erase (SSE, SE, CHE) or Program (PP, PPL) entry during the suspension, the suspension will be canceled automatically. And a new Erase (SSE, SE, CHE), Program (PP, PPL) will be executed. In this case, it is necessary to erase/program the suspended area again. • During Write Suspend, Read (RDSR, RDLP, RDHS, RDDO, RDIO) and Resume (RESM) can be accepted. • If the Software Reset is executed during the suspension, the suspension will be canceled automatically. Figure 15. Write Suspend (WSUS) Recovery time from Suspend tRSUS CS Mode3 SCK 20us 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Mode0 8CLK SI Next Command (Read or Resume) MSB B0h MSB SO High Impedance Operation Current = ISB www.onsemi.com 25 LE25S81A 10-12. Resume (RESM) This command (RESM) restarts erase cycle (SSE, SE, CHE) or program cycle (PP, PPL) that was suspended. "Figure 16. Resume (RESM)" shows the timing waveforms. The sequence of RESM operation : CS goes to low input RESM command (30h) CS goes to high (be executed by the rising CS edge) The internal operation status could be checked by using status register RDY bit or SUS bit. This command will be ignored if the previous Write Suspend operation was interrupted by unexpected power off or re-erase/program (cancel of suspend) or Software Reset(RST). To execute Write Suspend (WSUS) again after Resume, it is necessary to wait for some time (tSUS). Figure 16. Resume (RESM) Self-timed Write Cycle tCHE/ tSE/ tSSE/ tPP/ tPPL CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 30h MSB SO High Impedance www.onsemi.com 26 LE25S81A 10-13. Read ID Read ID is an operation that reads the manufacturer code (RJID) and device ID information (RID). These Read ID commands are not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID. 10-13-1. Read JEDEC ID (RJID) This command (RJID) is compatible with the JEDEC standard for SPI compatible serial memories. "Table 6. JEDEC ID codes" lists the silicon ID codes. "Figure 17. Read JEDEC ID (RJID)" shows the timing waveforms. The sequence of RJID operation : CS goes to low input RJID command (9Fh) Manufacture code (62h) out on SO Memory type code (16h) out on SO Memory capacity code out on SO (14h) Reserve code (00h) completed by CS=high * The 4-byte code is output repeatedly as long as clock inputs are present * The data output starts from the falling edge of SCK(7th clock) By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Table 6. JEDEC ID codes Output code 62h Manufacturer code Memory type 16h Memory capacity code 14h (8M Bit) 2 byte device ID 00h Reserve code Figure 17. Read JEDEC ID (RJID) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 Mode0 8CLK SI SO 9Fh High Impedance 62h MSB 16h MSB 14h MSB www.onsemi.com 27 00h MSB 62h MSB LE25S81A 10-13-2. Read Device ID (RID) This command (RID) is an operation that reads the Device ID. "Table 7. Device ID code" lists the device ID codes. "Figure 18. Read Device ID (RID)" shows the timing waveforms. The sequence of RID operation : CS goes to low input RID command (ABh) 3 byte dummy cycle Device ID (87h) out on SO completed by CS=high * The Device ID (87h) is output repeatedly as long as clock inputs are present * The data output starts from the falling edge of SCK(31th) By setting CS to high, the device is deselected, and Read ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Table 7. Device ID code Output Code 1 byte device ID 87h (LE25S81A) Figure 18. Read Device ID (RID) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 Mode0 8CLK SI SO ABh X X High Impedance X 87h MSB www.onsemi.com 28 87h MSB LE25S81A 10-14. Deep Power-down (DP) The standby current can be further reduced with this command (DP). "Figure 19. Deep Power-down (DP)" shows the timing waveforms. The sequence of DP operation : CS goes to low input DP command (B9h) CS goes to high (be executed by the rising CS edge) The deep power-down command issued during an internal write operation will be ignored. The deep power-down state is exited using the deep power-down exit (EDP). All other commands are ignored. Figure 19. Deep Power-down (DP) Standby current (ISB) CS tDP Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI B9h MSB SO High Impedance www.onsemi.com 29 Deep Power-down Standby Current (IDSB) LE25S81A 10-15. Exit Deep Power-down (EDP) / Read Device ID (RDDI) The Exit Deep Power-down (EDP) / Read Device ID (RID) command is a multi-purpose command. It can be used to exit the device from the deep power-down state, or read the device ID information. Exit Deep Power-down (EDP) The exit deep power-down command consists only of the first byte cycle, and it is initiated by inputting (ABh). "Figure 20. Exiting from Deep Power-down" shows the timing waveforms. The sequence of EDP operation : CS goes to low input EDP command (ABh) CS goes to high (be executed by the rising CS edge) Figure 20. Exiting from Deep Power-down (EDP) Deep Power-down Standby current (IDSB) Standby current (ISB) CS tRDP Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI ABh MSB SO High Impedance www.onsemi.com 30 LE25S81A Read Device ID (RDDI) Also the exit from deep power-down is completed by one byte cycle or more of the Read Device ID (RID: ABh). "Table 7. Device ID code" lists the device ID codes. "Figure 21. Read Device ID " shows the timing waveforms. The sequence of EDP & RID operation : CS goes to low input RID command (ABh) 3 byte dummy cycle Device ID out on SO completed by CS=high * The Device ID is output repeatedly as long as clock inputs are present * The data output starts from the falling edge of SCK(31th clock) By setting CS to high, the device is deselected, and Read ID cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 21. Read Device ID Standby current (ISB) Deep Power-down Standbycurrent (IDSB) CS tRDP Mode3 SCK 0 1 2 3 4 5 6 7 8 SO 39 Mode0 8CL SI 31 32 ABh 24 Dummy Bits X X High Impedance Dev ID MSB www.onsemi.com 31 Dev ID Dev ID LE25S81A 10-16. Software Reset The Software Reset reset the device to the state just after power-on. This operation consists of two commands: the Reset Enable (RSTEN) and the Reset command (RST). "Figure 22. Software Reset" shows the timing waveforms. The sequence of Software Reset operation : CS goes to low input RSTEN command (66h) CS goes to high CS goes to low input RST command (99h) CS goes to high (be executed by the rising CS edge) When the Software Reset is executed, an internal write (erase/program) operation is cancel, a suspended status is reset, and all volatility status register bits (WEN/ RDY/SUS) are reset. After the internal reset time (tRST), the device will become stand-by state. If the Software Reset is executed during a write (erase/program) operation, any dates on the write operation will be broken. The Reset command must input just after input the Reset Enable command. If another command input after the Reset Enable command, the Reset-Enable state will be invalid. Figure 22. Software Reset Internal reset time (tRST) CS Mode3 SCK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8CLK 8CLK 66h 99h Mode0 SI MSB SO MSB High Impedance www.onsemi.com 32 LE25S81A 10-17. Read SFDP (RSFDP) The Read SFDP (Serial Flash Discoverable Parameter) is an operation that reads the parameter about device configurations, available commands and other features. The SFDP parameters are stored in internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. SFDP is a standard of JEDEC. JESD216. Rev 1.0. "Table 8. SFDP Header" shows SFDP Header. "Table 9. SFDP Parameter Table" shows SFDP Parameter Table. "Figure 23. Read SFDP (RSFDP)" shows the timing waveforms. The sequence of RSFDP operation : CS goes to low input RSFDP command (5Ah) 3 Byte address (A23-A0) input on SI 1 byte dummy cycle the corresponding parameter out on SO continuous parameter out (n-byte) completed by CS=high * A10 to A0 are valid address * The parameter output starts from the falling edge of SCK(39th clock) The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding parameter is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte parameter is shifted out. By setting CS to high, the device is deselected, and Read SFDP cycle is completed. While the device is deselected, the output pin SO is in a high-impedance state. Figure 23. Read SFDP (RSFDP) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI 5Ah Add Add Add (A23-A16) (A15-A8) (A7-A0) X MSB Byte 1 SO High Impedance Param1 Param2 Param3 MSB www.onsemi.com 33 Byte 2 Byte 3 MSB MSB LE25S81A Table 8. SFDP Header st SFDP Header 1 nd and 2 DWORD Description SFDP Signature Byte Address (Hex) Comment 50444653h (SFDP) Bits Data (Hex) 00h 7:0 53h 01h 15:8 46h 02h 23:16 44h 03h 31:24 50h 7:0 05h 01h SFDP Minor Revision Number Start from 00h 04h SFDP Major Revision Number Start from 01h 05h 15:8 Number of Parameter Headers 02h indicates 3 parameters 06h 23:16 02h 07h 31:24 FFh Byte Address (Hex) Bits Data (Hex) 00h(JEDEC specified header) 08h 7:0 00h Start from 00h 09h 15:8 00h Start from 01h 0Ah 23:16 01h How many DWORDs in the Parameter table 10h indicates 16 DWORDs 0Bh 31:24 10h 0Ch 7:0 40h 0Dh 15:8 00h 0Eh 23:16 00h 0Fh 31:24 FFh Byte Address (Hex) Bits Data (Hex) 62h(ON Semiconductor manufacturer ID) 10h 7:0 62h Start from 00h 11h 15:8 00h Start from 01h 12h 23:16 01h How many DWORDs in the Parameter table 04h indicates 4 DWORDs 13h 31:24 04h 14h 7:0 C0h 15h 15:8 00h 16h 23:16 00h 17h 31:24 FFh Unused st 1 Parameter Header (JDEC Basic Flash parameters) Description ID number (JEDEC ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Comment First address of JEDEC Flash Parameter table Unused 2nd Parameter Header (Vender parameters 1) Description ID number (ON Semiconductor manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Comment First address of On Semiconductor Parameter table Unused www.onsemi.com 34 LE25S81A Table 9. SFDP Parameter Tables th Parameter Table : JDEC Basic Flash Parameter Tables (from 1th DWORD to 4 DWORD) Description Byte Address (Hex) Comment 40h Unused 00b: Reserved 01b: support 4 KB Erase 10b: Reserved 11b: not support 4KB Erase 0: 1Byte, 1:64 Byte or larger 0: Non-volatile 1: Volatile 0: use 50h opcode, 1: use 06h opcode Note: If target flash status register is nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be changed 4KB Erase Instruction 20h 41h (1-1-2) Fast Read 0=not support 1=support 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved Block/Sector Erase Sizes Write Granularity Volatile Status Register Block Protect bits Write Enable Instruction Select for Writing to Volatile Status Register Address Bytes Double Transfer Rate (DTR) Clocking (1-2-2) Fast Read 0=not support 1=support 42h 0=not support 1=support Bits Data (Binary) 1:0 01b 2 1b 3 0b 4 0b 7:5 111b 15:8 0010_0000b 16 1b 18:17 00b 19 0b 20 1b 0b (1-4-4) Fast Read 0=not support 1=support 21 (1-1-4) Fast Read 0=not support 1=support 22 0b 23 1b Unused Data (Hex) E5h 20h 91h Unused 43h 31:24 1111_1111b FFh Flash Memory Density 44h 45h 46h 47h 31:0 - 007FFFFFh 4:0 0_0000b 7:5 000b (1-4-4) Fast Read Number of Wait states (dummy clocks) (1-4-4) Fast Read Number of Mode Clocks (1-4-4) Fast Read Instruction (1-1-4) Fast Read Number of Wait states (dummy clocks) (1-1-4) Fast Read Number of Mode Clocks (1-1-4) Fast Read Instruction (1-1-2) Fast Read Number of Wait states (dummy clocks) (1-1-2) Fast Read Number of Mode Clocks (1-1-2) Fast Read Instruction (1-2-2) Fast Read Number of Wait states (dummy clocks) (1-2-2) Fast Read Number of Mode Clocks (1-2-2) Fast Read Instruction 8 M bits 0 0000b: Wait states (dummy Clocks) not support 48h 000b: Mode Bits not support 49h 0 0000b: Wait states (dummy Clocks) not support 00h 15:8 1111_1111b 20:16 0_0000b 23:21 000b 31:24 1111_1111b 4:0 0_1000b 7:5 000b 15:8 0011_1011b 20:16 0_0100b 23:21 000b 31:24 1011_1011b 4Ah 000b: Mode Bits not support 4Bh 0 0000b: Wait states (dummy Clocks) not support 00h 4Ch 000b: Mode Bits not support 4Dh 0 0000b: Wait states (dummy Clocks) not support 4Fh www.onsemi.com 35 FFh 08h 4Eh 000b: Mode Bits not support FFh 3Bh 04h BBh LE25S81A Parameter Table : JDEC Basic Flash Parameter Tables (from 5th DWORD to 8th DWORD) Description (2-2-2) Fast Read 0=not support 1=support Reserved Default all 1’s (4-4-4) Fast Read 0=not support 1=support Reserved Default all 1’s Reserved Default all 1’s Reserved Default all 1’s (2-2-2) Fast Read Number of Wait states (dummy clocks) (2-2-2) Fast Read Number of Mode Clocks (2-2-2) Fast Read Instruction Reserved (4-4-4) Fast Read Number of Wait states (dummy clocks) (4-4-4) Fast Read Number of Mode Clocks (4-4-4) Fast Read Instruction Sector Type 1 Size Byte Address (Hex) Comment Data (Binary) 0 0b 111b 4 0b 7:5 111b 31:8 - 15:0 - 20:16 0_0000b 23:21 000b 57h 31:24 1111_1111b FFh 58h 59h 15:0 - FFh FFh 20:16 0_0000b 23:21 000b 31:24 1111_1111b FFh 5Ch 7:0 0000_1100b 0Ch 5Dh 15:8 0010_0000b 20h 5Eh 23:16 0001_0000b 10h 5Fh 31:24 1101_1000b D8h 51h 52h 53h 54h 55h 0 0000b: Wait states (dummy Clocks) not support 56h 000b: Mode Bits not support Default all 1’s 0 0000b: Wait states (dummy Clocks) not support 000b: Mode Bits not support 5Bh Sector/block size = 2^N bytes 10h indicates 64Kbytes Sector Type 2 erase Instruction www.onsemi.com 36 EEh FFh FFh FFh FFh FFh 00h 5Ah Sector/block size = 2^N bytes 0Ch indicates 4Kbytes Data (Hex) 3:1 50h Sector Type 1 erase Instruction Sector Type 2 Size Bits 00h LE25S81A Parameter Table : JDEC Basic Flash Parameter Tables (from 9th DWORD to 12th DWORD) Description Sector Type 3 Size Comment Sector/block size = 2^N bytes 00h indicates not exist Sector Type 3 erase Instruction Sector Type 4 Size Sector/block size = 2^N bytes 00h indicates not exist Sector Type 4 erase Instruction Multiplier from typical erase time to maximum erase time Sector Type 1 Erase, Typical time Sector Type 2 Erase, Typical time SE (64K-Byte erase): 180ms=2*(n+1)*15ms n=5 SSE (4K-Byte erase) 10ms: ((n+1)*1ms=10ms) n=9 SE (64K-Byte erase) 15ms: ((n+1)*1ms=15ms) n=14 Sector Type 3 Erase, Typical time - Sector Type 4 Erase, Typical time - Multiplier from typical time to max time for Page or byte program Page Size (n+1)*0.3ms =0.6ms: n=1, 256Bytes=2^8 (n+1)*64us =320us: n=4, Page Program Typical time Reserved Program Resume to Suspend Interval Suspend in-progress Program max latency Erase Resume to Suspend Interval Suspend in-progress erase max latency Suspend /resume supported 60h 7:0 0000_0000b 00h 61h 15:8 1111_1111b FFh 62h 23:16 0000_0000b 00h 63h 31:24 1111_1111b FFh 3:0 0101b 10:4 00_01001b 17:11 00_01110b 24:18 00_00000b 31:25 00_00000b 3:0 0001b 7:4 1000b 13:8 1_00100b 67h 0.6ms > 0.5ms(spec) 320us > 300us(spec) 68h 69h 95h 70h 00h 00h 15:14 (count+1)*1us/byte =1us/byte: Count=0 (n+1)*16ms =112ms: n=6 112ms > 100ms(spec) Prohibited Operations During Erase Suspend Data (Hex) 66h Byte Program Typical time, additional byte Prohibited Operations During Program Suspend Data (Binary) 65h (n+1)*8us =128us: n=15, Reserved Bits 64h Byte Program Typical time, first byte Chip Erase, Typical time Byte Address (Hex) 81h E4h 1_1111b 18:16 6Ah 6Bh xxx0b: May not initiate a new erase anywhere xxx1b: May not initiate a new erase in the program suspended page size xx0xb: May not initiate a new page program anywhere xx1xb: May not initiate a new page program in the program suspended page size x0xxb: Refer to vendor datasheet for read restrictions x1xxb: May not initiate a read in the program suspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 1:0 are sufficient xxx0b: May not initiate a new erase anywhere xxx1b: May not initiate a new erase in the erase suspended sector size xx0xb: May not initiate a page program anywhere xx1xb: May not initiate a page program in the erase suspended sector size x0xxb: Refer to vendor datasheet for read restrictions x1xxb: May not initiate a read in the erase suspended sector size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 5:4 are sufficient 0_0000b 30:24 00_00110b 31 0b 3:0 1101b 6Ch 6Dh <64us: (count+1)*64us, count=0 23:19 7:4 1111b 8 0b 12:9 0000b 19:16 6Eh <64us: (count+1)*64us, count=0 40us: ((4+1)*8us=40us) 6Fh 0=support 1=not support www.onsemi.com 37 06h FDh 15:13 40us: ((4+1)*8us=40us) 07h 80h 10_00100b 23:20 0000b 30:24 10_00100b 31 0b 08h 44h LE25S81A Parameter Table : JDEC Basic Flash Parameter Tables (from 13th DWORD to 16th DWORD) Byte Address (Hex) Bits Data (Binary) Data (Hex) 30h (as same as erase resume) 70h 7:0 0011_0000b 30h B0h (as same as erase suspend) 71h 15:8 1011_0000b B0h 30h (as same as program resume) 72h 23:16 0011_0000b 30h B0h (as same as program suspend) 73h 31:24 1011_0000b B0h Description Program Resume Instruction (program operation) Program Suspend Instruction (program operation) Resume Instruction (write or erase type operation) Suspend Instruction (write or erase type operation) Reserved Status Register Polling Device Busy Exit Deep Power down to next operation delay Exit Deep Power down Instruction Comment Use legacy polling by reading the Status Register with 05h instruction 40us: ((4+1)*8us=40us) 75h 76h B9h Deep Power down Supported 0=support 1=not support (4-4-4) Mode Disable Sequences - 00b 7:2 0000_01b 14:8 10_00100b 15 ABh Enter Deep Power down Instruction 1:0 74h 77h 78h (4-4-4) Mode Enable Sequences - (0-4-4) Mode supported 0=not support 1=support (0-4-4) Mode Exit Method - (0-4-4) Mode Entry Method - Quad Enable requirements (QER) 00b:not have a QE bit Hold and WP Disable 0: not supported Reserved - Volatile or Non-Volatile Register and Write Enable Instruction for Status Register 1 xxx_xxx1b: Non-Volatile Status Register 1, powers-up to last written value, use instruction 06h to enable write xx1_xxxxb: Status Register 1 contains a mix of volatile and non-volatile bits. The 06h instruction is used to enable writing of the register. Reserved - Soft Reset and Rescue Sequence Support Issue reset enable instruction 66h, and then issue reset instruction 99h. 79h www.onsemi.com 38 D5h 1011_1001b 30:24 31 0b 3:0 0000b 7:4 0000b 8 0b 9 0b 15:10 00_0000b 5Ch 00h 00h 19:16 0000b 000b 23 0b 31:24 0000_0000b 6:0 001_1001b 7 0b 13:8 01_0000b 15:14 00b 7Eh 23:16 0000_0000b 00h 7Fh 31:24 0000_0000b 00h 7Bh Enter 4-Byte Addressing 1010_1011b 22:20 7Ah Exit 4-Byte Addressing C4h 22:16 23 04h 7Ch 7Dh 00h 00h 19h 10h LE25S81A Parameter Table : Vender(ON Semiconductor) Parameter 1 Tables (from 1th DWORD to 4th DWORD) Byte Data Description Comment Address Bits (Binary) (Hex) 1900h=1.900V 2400h=2.400V 1950h=1.950V 2700h=2.700V C0h 15:0 Supply Maximum Voltage 3000h=3.000V C1h 2000h=2.000V 2200h=2.200V 3600h=3.600V 1600h=1.600V 20000h=2.000V 1650h=1.650V 22000h=2.200V C2h Supply Minimum Voltage 31:16 1700h=1.700V 23000h=2.300V C3h 1800h=1.800V 27000h=2.700V 0=not support 0 0b RESET Pin 1= support 0=active logic is 0 RESET Active Logic Level 1 0b 1=active logic is 1 0=not support HOLD Pin 2 1b 1= support 0=active logic is 0 C4h HOLD Active Logic Level 3 0b 1=active logic is 1 0=not support WP Pin 4 1b 1= support 0=active logic is 0 WP Active Logic Level 5 0b 1=active logic is 1 Reserved 00b 7:6 00b Data (Hex) LE25S81A 50h 19h 50h 16h 14h Reserved All FFh C5h C6h C7h 31:8 1111_1111b 1111_1111b 1111_1111b FFh FFh FFh JDEC ID Operation code JDEC ID Read Data (Manufacture code) JDEC ID Read Data (Memory type) JDEC ID Read Data (Memory capacity code) 9Fh C8h 7:0 1001_1111b 9Fh 62h (ON Semiconductor) C9h 15:8 0110_0010b 62h 16h CAh 23:16 0001_0110b 16h 14h (8M bits) CBh 31:24 0001_0100b 14h Device ID Operation code ABh CCh 7:0 1010_1011b ABh Device ID Read Data 87h(LE25S81A) 15:8 Reserved All FFh CDh CEh CFh 1000_0111b 1111_1111b 1111_1111b 87h FFh FFh www.onsemi.com 39 31:16 LE25S81A 11. Hold Function Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 24. HOLD Function" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care". Figure 24. HOLD Function CS Active Active HOLD tHS tHS SCK tHH tHH HOLD tHHZ SO tHLZ High Impedance www.onsemi.com 40 LE25S81A 12. Power-on In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After power-on, the supply voltage has stabilized at VDD (min) or higher, and waits for tVSL before CS is driven to "Low". The device is in the standby state after power is turned on. Figure 25. Power-on Timing VDD VDD(Max) Program, Erase and Write Commands are Ignored Chip Select ( CS="L") is Not Allowed VDD(Min) Read Command is allowed tVSL Reset State Full Access Allowed VWI tPUW 0V time Power-up timing Parameter Symbol spec min max unit µs VDD(Min) to CS Low tVSL 300 Time to Write Operation tPUW 100 500 µs Operation Inhibit Voltage VWI 1.0 1.5 V www.onsemi.com 41 LE25S81A 13. Hardware Data Protection LE25S81A incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 26. Power-down Timing VDD VDD(Max) VDD(Min) tPD 0V vBOT Power-down timing Parameter Symbol power-down time tPD power-down voltage VBOT spec min max 10 unit ms 0.2 V 14. Software Data Protection The LE25S81A eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. • When a write command is input and the rising CS edge timing is not in a byte cycle (8 CLK units of SCK) • When the Page Program data is not in 1-byte increments • When the Write Status Register command is input for 2 bytes cycles or more 15. Decoupling Capacitor 0.1µF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. www.onsemi.com 42 LE25S81A 16. Specifications 16-1. Absolute Maximum Ratings Parameter Symbol Conditions Ratings unit −0.5 to +2.6 V DC voltage (all pins) −0.5 to VDD+0.5 V Over-shoot voltage −1.0 to VDD+1.0 V −55 to +150 °C Maximum supply voltage Storage temperature Tstg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 16-2. Operating Conditions Parameter Symbol Conditions Operating supply voltage Ratings unit 1.65 to 1.95 V −40 to +90 °C Operating ambient temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 16-3. Data retention, Rewriting cycles Parameter Symbol condition Status resister write Rewrite Cycles min max 1,000 cycles/ 100,000 Sector 20 year cycRW Program/Erase Data retention tDRET unit 16-4. Pin Capacitance at Ta=25°C, f=1MHz Ratings Parameter Symbol Conditions unit max Output pin capacitance CSO VSO=0V 12 pF Input pin Capacitance CIN VIN=0V 6 pF Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. 16-5. AC Test Conditions Input pulse level ··········· 0.2VDD to 0.8VDD Input rising/falling time ·· 5ns Input timing level ········· 0.3VDD, 0.7VDD Output timing level ······· 1/2×VDD Output load················· 15pF Note: As the test conditions for "typ", the measurements are conducted using 1.8V for VDD at room temperature. 0.8VDD Input level Input / Output timing level 0.7VDD 1/2VDD 0.3VDD 0.2VDD www.onsemi.com 43 LE25S81A 16-6. DC Characteristics VDD=1.65 to 1.95V Parameter Symbol Conditions Ratings min Low-Power Read unit typ max 33MHz 3.0 4.0 mA 40MHz 3.5 5.0 mA 50MHz 4.0 5.5 mA 70MHz 5.0 7.0 mA 33MHz 4.0 5.0 mA 50MHz 5.0 6.5 mA 66MHz 5.5 8.0 mA (RDLP: 03h) SCK= 0.1VDD/0.9VDD, Read mode operating current High-Speed Read (RDHS: 0Bh) ICCR HOLD=WP= 0.9VDD, SO=open Dual Output Read (RDDO: 3Bh) or Dual I/O Read (RDIO: BBh) Small Sector Erase operating current Sector Erase operating current Chip Erase operating current ICCSSE tSSE=max, Average current 3.5 4.5 mA ICCSE tSE=max Average current 3.5 4.5 mA ICCCHE tCHE=max Average current 4.0 5.0 mA ICCPP tPP=max Average current 6.5 7.5 mA ICCPPL tPPL=max Average current 5.0 6.5 mA Normal Program mode operating current Low-Power Program mode operating current CMOS standby current Deep Power-down standby current ISB CS=VDD, HOLD=WP=VDD, SI=VSS/VDD, SO=open, 9 50 µA IDSB CS=VDD, HOLD=WP=VDD, SI=VSS/VDD, SO=open, 3.0 12 µA Input leakage current ILI 2.0 µA Output leakage current ILO 2.0 µA Input low voltage VIL −0.3 0.3VDD V Input high voltage VIH 0.7VDD VDD+0.3 V Output low voltage VOL Output high voltage VOH IOL=100µA, VDD=VDD min 0.2 IOL=1.6mA, VDD=VDD min 0.4 V IOH=−100µA, VDD=VDD min VDD-0.2 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 44 LE25S81A 16-7. AC Characteristics Ratings Parameter Symbol unit min typ max Low-Power Read Clock frequency (RDLP: 03h) Dual Output Read (RDDO: 3Bh) Dual I/O Read (RDIO: BBh) 40 fCLK 66 Other instructions Input signal rising/falling time 70 0.1 tRF 40MHz width 66MHz 11 tCLHI 6 33MHz 12 40MHz width 66MHz ns 6 70MHz SCK logic low level pulse V/ns 12 33MHz SCK logic high level pulse MHz 11 tCLLO ns 6 6 70MHz CS active setup time tSLCH 8 ns CS not active hold time tCHSL 3 ns Data setup time tDS 3 ns Data hold time tDH 3 ns CS wait pulse width tCPH 20 ns CS active hold time tCHSH 8 ns CS not active setup time tSHCH 3 Output high impedance time from CS Output data time from SCK ns tCHZ 8 tV 8 ns ns Output data hold time tHO 1 ns Output low impedance time from SCK tCLZ 0 ns HOLD setup time tHS 6 ns HOLD hold time tHH 6 Output low impedance time from HOLD tHLZ 10 ns Output high impedance time from HOLD tHHZ 10 ns WP setup time tWPS 20 WP hold time tWPH 20 Write status register time Normal Page Programming cycle time Low-Power Page Programming cycle time Small Sector Erase cycle time Sector Erase cycle time Chip Erase cycle time Recovery time from suspend Deep Power-down time tWRSR 256Byte nByte tPP ns ns 5 8 0.30 0.50 0.14 + n * 0.16/256 256Byte nByte ns 0.45 tPPL 0.14 + n * 0.31/256 ms ms 0.35 + n * 0.15/256 1.00 ms 0.50 + n * 0.50/256 tSSE 10 130 ms tSE 15 180 ms 120 1500 ms tRSUS tCHE 40 µs tDP 5 µs Deep Power-down recovery time tRDP 40 µs Internal reset time tRST 40 µs Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 45 LE25S81A 17. Timing waveforms Figure 27. Serial Input Timing tCPH CS tCHSL tSLCH tCLHI tCLLO tCHSH tSHCH SCK tDS SI tDH DATA VALID High Impedance SO High Impedance Figure 28. Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI Figure 29. Hold Timing CS tHH tHS tHH tHS SCK HOLD tHLZ tHHZ High Impedance SI Figure 30. Status Resister Write Timing CS tWPS tWPH WP www.onsemi.com 46 LE25S81A Figure 31. Write Status Register Flowcharts Write Status Register Start 06h 01h Data Write enable (WREN) Set Write Status Register command (WRSR) Program start on rising edge of CS 05h Set Read Status Register command (RDSR) NO Bit 0= "0" ? YES End of Write Status Register * Automatically placed in write disabled state at the end of the Write Status Register www.onsemi.com 47 LE25S81A Figure 32. Small Sector Erase Flowcharts Small Sector Erase Sector Erase Start Start 06h 20h / D7h Write enable (WREN) 06h Write enable (WREN) Set Small Sector Erase command (SSE) D8h Set Sector Erase command (SE) Address 1 Address 1 Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS Set Read Status Register command (RDSR) 05h NO Figure 33. Sector Erase Flowcharts 05h NO Bit 0 = "0" ? Set Read Status Register command (RDSR) Bit 0 = "0" ? YES YES End of erase End of erase * Automatically placed in write disabled state at the end of the erase * Automatically placed in write disabled state at the end of the erase www.onsemi.com 48 LE25S81A Figure 34. Chip Erase Flowcharts Chip Erase Start 06h 60h / C7h Write enable (WREN) Set Chip Erase command (CHE) Start erase on rising edge of CS 05h Set Read Status Register command (RDSR) Bit 0 = "0" ? YES NO End of erase * Automatically placed in write disabled state at the end of the erase www.onsemi.com 49 LE25S81A Figure 35. Page Program Flowcharts Page Program Start 06h Write enable (WREN) 02h or 0Ah Address 1 Address 2 Set Page Program command (PP/PPL) *02h: Normal Program Mode (PP) *0Ah: Low-Power Program Mode (PPL) Address 3 Data 0 Data n Start program on rising edge of CS Set Read Status Register command (RDSR) 05h NO Bit 0= "0" ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. www.onsemi.com 50 LE25S81A ORDERING INFORMATION Device Package Shipping (Qty / Packing) LE25S81AMDTWG SOIC8, 150mils (Pb-Free / Halogen Free) 2000 / Tape & Reel LE25S81AFDTWG VSOIC8 NB (Pb-Free / Halogen Free) 3000 / Tape & Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 51