VEML6075 www.vishay.com Vishay Semiconductors UVA and UVB Light Sensor with I2C Interface FEATURES • Package type: surface mount • Dimensions (L x W x H in mm): 2.0 x 1.25 x 1.0 • Integrated modules: ultraviolet sensor (UV), and signal conditioning IC • Converts solar UV light intensity to digital data • Excellent UVA and UVB sensitivity • Reliable performance of UV radiation measurement under long time solar UV exposure • 16-bit resolution per channel • UVA and UVB individual channel solution DESCRIPTION The VEML6075 senses UVA and UVB light and incorporates photodiode, amplifiers, and analog / digital circuits into a single chip using a CMOS process. When the UV sensor is applied, it is able to detect UVA and UVB intensity to provide a measure of the signal strength as well as allowing for UVI measurement. The VEML6075 provides excellent temperature compensation capability for keeping the output stable under changing temperature. VEML6075’s functionality is easily operated via the simple command format of I2C (SMBus compatible) interface protocol. VEML6075’s operating voltage ranges from 1.7 V to 3.6 V. VEML6075 is packaged in a lead (Pb)-free 4 pin OPLGA package which offers the best market-proven reliability. • Low power consumption I2C protocol (SMBus compatible) interface • Package: OPLGA • Temperature compensation: -40 °C to +85 °C • Output type: I2C bus • Operation voltage: 1.7 V to 3.6 V • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Handheld device • Notebook • Consumer device • Industrial and medical application PRODUCT SUMMARY PART NUMBER VEML6075 OPERATING VOLTAGE RANGE (V) I2C BUS VOLTAGE RANGE (V) PEAK SENSITIVITY UVA, UVB (nm) RANGE OF SPECTRAL BANDWIDTH λ0.5 (nm) OUTPUT CODE 1.7 to 3.6 1.7 to 3.6 365, 330 ± 10 16 bit, I2C Note (1) Adjustable through I2C interface ORDERING INFORMATION ORDERING CODE PACKAGING VOLUME (1) REMARKS VEML6075 Tape and reel MOQ: 2500 pcs 2.0 mm x 1.25 mm x 1.0 mm Note MOQ: minimum order quantity (1) Rev. 1.1, 19-May-16 Document Number: 84304 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL MIN. MAX. UNIT Supply voltage TEST CONDITION VDD 0 3.6 V Operation temperature range Tamb -40 +85 °C Storage temperature range Tstg -40 +85 °C RECOMMENDED OPERATING CONDITIONS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL MIN. MAX. Supply voltage TEST CONDITION VDD 1.7 3.6 UNIT V Operation temperature range Tamb -40 +85 °C I2C bus operating frequency f(I2CCLK) 10 400 kHz PIN DESCRIPTIONS PIN ASSIGNMENT SYMBOL TYPE 1 GND I FUNCTION Ground 2 SDAT I / O (open drain) I2C data bus data input / output 3 SCLK I I2C digital bus clock input 4 VDD I Power supply input BLOCK DIAGRAM VEML6075 GND VDD UV-PD State machine I2C interface VEML6075 pin-out assignment VDD Timing controller SDA 1 GND 2 SDAT 3 SCLK 4 VDD SCL Oscillator BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION Supply operation voltage Supply current I2C signal input I2C signal input VDD = 1.8 V Logic high Logic low Logic high Logic low VDD = 3.3 V VDD = 2.6 V Operating temperature Shutdown current Light condition = dark; VDD = 1.8 V, Tamb = 25 °C SYMBOL MIN. TYP. MAX. VDD 1.7 - 3.6 UNIT V IDD - 480 - μA VIH 1.5 - - VIL - - 0.8 VIH 1.4 - - VIL - - 0.6 Tamb -40 - +85 °C IDD (SD) - 800 - nA V V UVA responsivity IT = 50 ms (1) - 0.93 - counts/μW/cm2 UVB responsivity IT = 50 ms (2) - 2.1 - counts/μW/cm2 W-LED / IRED (940 nm) - 0.5 <1 % Visible / infrared response Notes (1) Nichia NCSU033X (365 nm) (2) UVTOP310TO39HS (315 nm) Rev. 1.1, 19-May-16 Document Number: 84304 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors I2C TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL Clock frequency STANDARD MODE MIN. MAX. f(SMBCLK) 10 t(BUF) 4.7 t(HDSTA) Repeated start condition setup time Stop condition setup time Data hold time Data setup time Bus free time between start and stop condition Hold time after (repeated) start condition; after this period, the first clock is generated FAST MODE UNIT MIN. MAX. 100 10 400 kHz - 1.3 - μs 4.0 - 0.6 - μs t(SUSTA) 4.7 - 0.6 - μs t(SUSTO) 4.0 - 0.6 - μs t(HDDAT) - 3450 - 900 ns t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Clock / data fall time t(F) - 300 - 300 ns Clock / data rise time t(R) - 1000 - 300 ns t(LOW) 2 t(R) t(F) VIH I C bus clock (SCLK) VIL t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO) t(BUF) t(HDDAT) I2C bus data (SDAT) t(SUDAT) VIH { { P Stop Condition { { VIL S P S Start Condition Start Stop t(LOSEXT) SCL ACK t(LOWMEXT) SDAACK t(LOWMEXT) t(LOWMEXT) 2 I C bus clock (SCLK) I2C bus data (SDAT) Fig. 1 - I2C Bus Timing Diagram Rev. 1.1, 19-May-16 Document Number: 84304 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors PARAMETER TIMING INFORMATION I2C bus clock (SCLK) I2C bus data (SDAT) SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 W SA6 SA5 SA4 SA3 SA2 SA1 SA0 ACK by VEML6075 Start by master ACK by VEML6075 I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data (SDAT) SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA6 SA7 SA5 SA4 SA3 SA2 SA1 SA0 ACK by Stop by VEML6075 master ACK by VEML6075 Data byte low Data byte high Fig. 2 - I2C Bus Timing for Sending Word Command Format I2C bus clock (SCLK) I2C bus data (SDAT) SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 W SA6 SA5 SA4 SA3 SA2 SA1 SA0 ACK by VEML6075 Start by master ACK by VEML6075 I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data (SDAT) SA7 SA6 SA5 SA4 SA3 SA2 R SA1 Start by master SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 ACK by master ACK by VEML6075 I2C bus slave address byte Data byte low I2C bus clock (SCLK) I2C bus data (SDAT) SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 ACK by master Stop by master Data byte high Fig. 3 - I2C Timing for Receive Word Command Format Rev. 1.1, 19-May-16 Document Number: 84304 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Axis Title Axis Title UVB 70 1000 1st line 2nd line 60 50 UVA 40 100 30 UVcomp2 20 UVcomp1 10 80 70 400 450 500 550 UV-V 50 UV-H 40 100 30 20 10 350 1000 60 10 0 300 10000 Cosine 90 80 2nd line Normalized Output (%) 90 2nd line Normalized Output (%) 100 10000 1st line 2nd line 100 0 600 10 -90 -60 -30 0 30 60 90 λ - Wavelength (nm) 2nd line Angle (deg) 2nd line Fig. 4 - Normalized Spectral Response Fig. 5 - Normalized Output vs. View Angle APPLICATION INFORMATION Pin Connection with the Host The configuration and data registers of the VEML6075 are accessed via the I2C interface. The hardware schematic is shown below in fig. 6. The 0.1 μF capacitor near the VDD pin is used for power supply noise rejection. The 2.2 kΩ is suitable for the pull high resistor of I2C. 1.7 V to 3.6 V R1 R2 GND (1) 1.7 V to 3.6 V C1 100 nF Host Micro Controller VDD (4) VEML6075 SDA (2) I2C bus data SDA SCL (3) I2C bus clock SCL Fig. 6 - Hardware Pin Connection Diagram Rev. 1.1, 19-May-16 Document Number: 84304 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors Digital Interface The VEML6075 contains a CONF register (00h) used for operation control and parameter setup. Measurement results are stored in four separate registers, one each for UVA, UVD, UVB, UVcomp1, and UVcomp2 (07h to 0Bh respectively). All registers are accessible via I2C communication. Fig. 7 shows the basic I2C communication with the VEML6075. Each of the registers in the VEML6075 are 16 bit wide, so 16 bit should be written when a write command is sent, and 16 bit should be read when a read command is sent. The built in I2C interface is compatible with I2C modes “standard” and “fast”: 100 kHz to 400 kHz Send Word ɦġWrite Command to VEML6075 1 7 S Slave address 1 1 8 1 Wr A Command code A 8 Data byte low 1 8 1 1 A Data byte high A P Receive Word ɦġRead Data from VEML6075 1 7 1 1 8 1 1 7 1 1 8 1 8 1 1 S Slave address Wr A Command code A S Slave address Rd A Data byte low A Data byte high A P S = start condition P = stop condition A = acknowledge Shaded area = VEML6075 acknowledge Fig. 7 - Command Protocol Format Note • Please note the repeat start condition when data is read from the sensor. A stop condition should not be sent here. Slave Address and Function Description VEML6075 uses 0x10 slave address for 7-bit I2C addressing protocol. VEML6075 has 16-bit resolution for each channel (UVA, UVB, UVcomp1, UVcomp2, and UVD). TABLE 1 - VEML6075 COMMAND CODE AND REGISTER DESCRIPTION COMMAND CODE DATE BYTE LOW / HIGH REGISTER NAME 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Rev. 1.1, 19-May-16 R/W DEFAULT VALUE FUNCTION DESCRIPTION L UV_CONF R/W 0x00 UV integration time, function enable and disable H Reserved R/W 0x00 Reserved L Reserved R/W 0x00 Reserved H Reserved R/W 0x00 Reserved L Reserved R/W 0x00 Reserved H Reserved R/W 0x00 Reserved L Reserved R/W 0x00 Reserved H Reserved R/W 0x00 Reserved L Reserved R/W 0x00 Reserved H Reserved R/W 0x00 Reserved L Reserved R/W 0x00 Reserved H Reserved R/W 0x00 Reserved L Reserved R/W 0x00 Reserved H Reserved R/W 0x00 Reserved L UVA_Data R 0x00 UVA LSB output data H UVA_Data R 0x00 UVA MSB output data UVD L Dummy R 0x00 H Dummy R 0x00 UVD L UVB_Data R 0x00 UVB LSB output data H UVB_Data R 0x00 UVB MSB output data L UVCOMP1_Data R 0x00 UVcomp1 LSB output data UVcomp1 MSB output data H UVCOMP1_Data R 0x00 L UVCOMP2_Data R 0x00 UVcomp2 LSB output data H UVCOMP2_Data R 0x00 UVcomp2 MSB output data L ID R 0x26 Device ID LSB H ID R 0x00 Device ID MSB Document Number: 84304 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors Command Register Format The VEML6075 has 16-bit registers used to set up the measurements as well as pick up the measurement results. The description of each command format is shown in the following tables. TABLE 2 - REGISTER UV_CONF DESCRIPTION REGISTER NAME COMMAND COMMAND CODE: 0x00_L (0x00 DATA BYTE LOW) OR 0x00_H (0x00 DATA BYTE HIGH) BIT 7 6 5 REGISTER: UV_CONF COMMAND BIT Reserved UV_IT 7 6:4 HD 4 3 2 1 0 COMMAND CODE: 0x00_L (0x00 DATA BYTE LOW) Description 0 (0 : 0 : 0) = 50 ms, (0 : 0 : 1) = 100 ms, (0 : 1 : 0) = 200 ms, (0 : 1 : 1) = 400 ms, (1 : 0 : 0) = 800 ms, (1 : 0 : 1) = reserved, (1 : 1 : 0) = reserved, (1 : 1 : 1) = reserved. 3 0 = normal dynamic setting, 1 = high dynamic setting UV_TRIG 2 0 = no active force mode trigger, 1 = trigger one measurement With UV_AF = 1 the VEML6075 conducts one measurement every time the host writes UV_Trig = 1. This bit returns to “0” automatically. UV_AF 1 0 = active force mode disable (normal mode), 1 = active force mode enable SD 0 0 = power on, 1 = shut down TABLE 3 - REGISTER 00_H DESCRIPTION REGISTER: reserved COMMAND BIT Reserved 7:0 COMMAND CODE: 0x00_H (0x00 DATA BYTE HIGH) Description Default = (0 : 0 : 0 : 0 : 0 : 0 : 0 : 0) TABLE 4 - REGISTER 01_L TO 06_L AND 01_H TO 06_L DESCRIPTION REGISTER: reserved COMMAND CODE: 0x01_L TO 0x06_L (0x01 TO 0x06 DATA BYTE LOW) COMMAND CODE: 0x01_H TO 0x06_H (0x01 TO 0x06 DATA BYTE HIGH) REGISTER BIT Reserved 7:0 Default = (0 : 0 : 0 : 0 : 0 : 0 : 0 : 0) Description Reserved 7:0 Default = (0 : 0 : 0 : 0 : 0 : 0 : 0 : 0) TABLE 5 - READ OUT COMMAND CODES DESCRIPTION REGISTER UVA_DATA DUMMY UVB_DATA UVCOMP1_DATA UVCOMP2_DATA ID COMMAND CODE DESCRIPTION 07:00 0x00 to 0xFF, UVA LSB output data 0x07_H (0x07 data byte high) 07:00 0x00 to 0xFF, UVA MSB output data 0x08_L (0x08 data byte low) 07:00 0x00 to 0xFF, UVD 0x08_H (0x08 data byte high) 07:00 0x00 to 0xFF, UVD 0x09_L (0x09 data byte low) 07:00 0x00 to 0xFF, UVB LSB output data 0x09_H (0x09 data byte high) 07:00 0x00 to 0xFF, UVB MSB output data 0x0A_L (0x0A data byte low) 07:00 0x00 to 0xFF, UVcomp1 LSB output data 0x0A_H (0x0A data byte high) 07:00 0x00 to 0xFF, UVcomp1 MSB output data 0x0B_L (0x0B data byte low) 07:00 0x00 to 0xFF, UVcomp2 LSB output data 0x0B_H (0x0B data byte high) 07:00 0x00 to 0xFF, UVcomp2 MSB output data 0x0C_L (0x0C data byte low) 07:00 Default = 0x26, device ID LSB byte 07:06 05:04 03:00 Company code = 00, (0 : 0) Slave address = 0x20 Version code (0 : 0 : 0 : 0) = VEML6075 CS Device ID MSB byte 0x0C_H (0x0C data byte high) Rev. 1.1, 19-May-16 BIT 0x07_L (0x07 data byte low) Document Number: 84304 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors Data Access VEML6075 has 16-bit high resolution sensitivity for each UV channel. One byte is the LSB and the other byte is the MSB. The host needs to follow the read word protocol as shown in fig. 7. The data format shows as below. TABLE 6 - 16-BIT DATA FORMAT VEML6075 16-BIT DATA FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data byte low Data byte high Note Receive byte S Read data from VEML6075 Slave address Wr S = start condition P = stop condition A = acknowledge N = no acknowledge A A Command code S Rd Slave address Data byte (LSB) A A Data byte (MSB) N P Host action VEML6075 response • Data byte low represents LSB and data byte high represents MSB. Data Auto-Memorization VEML6075 keeps the last results read. These values will remain in the registers, and can be read from these registers, until the device wakes up and a new measurement is made. UV-Index Calculation In order to use the result data to calculate the UV-Index, please refer to the “Designing the VEML6075 into an Application” application note (www.vishay.com/doc?84339). PACKAGE INFORMATION in millimeters TOP VIEW 0.45 ± 0.05 2.00 ± 0.15 1.10 0.35 ± 0.05 0 to 0.06 4 2 3 1 0 to 0.05 X’ X’ 0 to 0.02 0 to 0.04 X’ 0.25 X 0.70 4 0.625 ± 0.15 1.25 ± 0.15 1 3 2 0.1 1.00 ± 0.15 SIDE VIEW 0.55 ± 0.05 DIE 1.0 PAD AND CIRCUIT LAYOUT REFERENCE 1 4 2 3 3 0.7 0.35 0.45 0.1 1 ± 0.10 0.56 30 μm ± 10 μm Package edge to edge 2 ± 0.15 0.1 0.5 0.6 0.4 Fig. 8 - VEML6075 A3OP Package Dimensions Rev. 1.1, 19-May-16 Document Number: 84304 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors RECOMMENDED STORAGE AND REBAKING CONDITIONS PARAMETER Storage temperature Relative humidity Open time Total time Rebaking CONDITIONS From the date code on the aluminized envelope (unopened) Tape and reel: 60 °C Tube: 60 °C MIN. 5 - MAX. 50 60 168 12 22 22 UNIT °C % h months h h RECOMMENDED INFRARED REFLOW Soldering conditions which are based on J-STD-020 C. IR REFLOW PROFILE CONDITION PARAMETER Peak temperature Preheat temperature range and timing Timing within 5 °C to peak temperature Timing maintained above temperature / time Timing from 25 °C to peak temperature Ramp-up rate Ramp-down rate CONDITIONS TEMPERATURE 255 °C + 0 °C / - 5 °C (max.: 260 °C) 150 °C to 200 °C 217 °C 3 °C/s (max.) 6 °C/s (max.) TIME 10 s 60 s to 180 s 10 s to 30 s 60 s to 150 s 8 min (max.) - Temperature (°C) Recommend Normal Solder Reflow is 235 °C to 255 °C Max. Temperature (260 °C + 5 °C / - 5 °C)/10 s 255 Ramp-Up Rate 3 °C/s (max.) 217 200 150 Ramp-Down Rate 6 °C/s (max.) Soldering Zone 60 s to 150 s Ramp-Up Rate 3 °C/s (max.) Pre-Heating Time t2 - t1 = 60 s to 180 s t1 t2 Time (s) Fig. 9 - VEML6075 OPLGA Solder Reflow Profile Chart RECOMMENDED IRON TIP SOLDERING CONDITION AND WARNING HANDLING 1. Solder the device with the following conditions: 1.1. Soldering temperature: 400 °C (max.) 1.2. Soldering time: 3 s (max.) 2. If the temperature of the method portion rises in addition to the residual stress between the leads, the possibility that an open or short circuit occurs due to the deformation or destruction of the resin increases. 3. The following methods: VPS and wave soldering, have not been suggested for the component assembly. 4. Cleaning method conditions: 4.1. Solvent: methyl alcohol, ethyl alcohol, isopropyl alcohol 4.2. Solvent temperature < 45 °C (max.) 4.3. Time: 3 min (min.) Rev. 1.1, 19-May-16 Document Number: 84304 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6075 www.vishay.com Vishay Semiconductors TAPE PACKAGING INFORMATION in millimeters 0.28 ± 0.02 DIMENSION OF CARRIER TAPE TOP VIEW 4.0 ± 0.1 2.0 ± 0.05 Ø 1.5 ± 0.1 R9 max. 2.03 ± 0.10 5.50 ± 0.05 1.25 ± 0.10 12.00 + 0.30 - 0.10 4.0 ± 0.1 PIN 1 1.75 ± 0.10 SIDE VIEW Ø 1.0 ± 0.05 R9 max. 2.58 ± 0.10 Fig. 10 - VEML6070 A3OP Package Carrier Tape Fig. 11 - Taping Direction Fig. 12 - Reel Dimension Rev. 1.1, 19-May-16 Document Number: 84304 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000