EL5623 ® Data Sheet May 6, 2005 Multi-Channel Buffer Features The EL5623 integrates six channels of gamma buffers into a single device. The top three gamma channels in each device are designed to swing to the upper supply rail, with the other three designed to swing to the lower rail. The output capability of each channel is 10mA continuous, with 120mA peak. The gamma buffers feature a 10MHz -3dB bandwidth specification and a 9V/µs slew rate. • Six gamma buffers - 10MHz BW - 9V/µs SR - 120mA peak IOUT - 3 high side drivers - 3 low side drivers Packaged in the 16-pin TSSOP package, the EL5623 is specified for operation over the -40°C to +85°C temperature range. Ordering Information PART NUMBER (See Note) • 3.5mA supply current • Pb-free available (RoHS compliant) Applications • TFT-LCD monitors PACKAGE (Pb-Free) TAPE & REEL PKG DWG. # EL5623IRZ 16-Pin TSSOP - MDP0048 EL5623IRZ-T7 16-Pin TSSOP 7” MDP0048 EL5623IRZ-T13 16-Pin TSSOP 13” MDP0048 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 FN7507.1 • LCD televisions • Industrial flat panel displays Pinout EL5623 (16-PIN TSSOP) TOP VIEW VS+ 1 16 VS+ OUT1 2 15 IN1 OUT2 3 14 IN2 OUT3 4 13 IN3 OUT4 5 12 IN4 OUT5 6 11 IN5 OUT6 7 10 IN6 VS- 8 9 VS- CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5623 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current (VOUT1-6) . . . . . . . . . . 15mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +15V, VS- = 0, RL = 10kΩ, CL = 10pF to 0V, and TA = 25°C Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT 20 mV INPUT CHARACTERISTICS (REFERENCE BUFFERS) VOS Input Offset Voltage VCM = 0V 2 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 0V 2 µV/°C 50 nA RIN Input Impedance 10 MΩ CIN Input Capacitance 1.35 pF AV Voltage Gain 1V ≤ VOUT ≤ 14V CMIR Input Voltage Range 0.992 1.008 V/V IN1 to IN3 1.5 VS+ V IN4 to IN6 0 VS+ -1.5 V OUTPUT CHARACTERISTICS (REFERENCE BUFFERS) VOH High Level Output Voltage (OUT1) VS+ = 15V, IO = 5mA, VI = 15V, TO = 25°C High Level Output Voltage (OUT2-OUT3) VOL 14.85 14.9 V 14.8 14.85 V 13.45 13.5 V High Level Output Voltage (OUT4-OUT6) VS+ = 15V, IO = 5mA, VI = 13.5V, TO = 25°C Low Level Output Voltage (OUT1-OUT3) VS+ = 15V, IO = 5mA, VI = 1.5V, TO = 25°C 1.5 1.55 V Low Level Output Voltage (OUT4-OUT5) VS+ = 15V, IO = 5mA, VI = 0V, TO = 25°C 0.15 .2 V 0.1 0.15 V Low Level Output Voltage (OUT6) POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio IS Total Supply Current Reference buffer VS from 5V to 15V 50 80 3.5 dB 4.5 mA DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS) SR Slew Rate (Note 2) tS Settling to +0.1% (AV = +1) BW 5 9 V/µs (AV = +1), VO = 2V step 500 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 10 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 6 MHz PM Phase Margin RL = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. 2 FN7507.1 May 6, 2005 EL5623 Pin Descriptions PIN NUMBER PIN NAME PIN FUNCTION 1, 16 VS+ 2 OUT1 Positive supply voltage Output gamma channel 1 3 OUT2 Output gamma channel 2 4 OUT3 Output gamma channel 3 5 OUT4 Output gamma channel 4 6 OUT5 Output gamma channel 5 7 OUT6 Output gamma channel 6 8, 9 VS- Negative supply 10 IN6 Input gamma channel 6 11 IN5 Input gamma channel 5 12 IN4 Input gamma channel 4 13 IN3 Input gamma channel 3 14 IN2 Input gamma channel 2 15 IN1 Input gamma channel 1 Block Diagram VS+ EL5623 COLUMN DRIVER 3 FN7507.1 May 6, 2005 EL5623 Typical Performance Curves 5 10 VS=±7.5V CL=10pF 3 6 RL=10kΩ 1 -1 RL=562Ω RL=150Ω -3 -5 100 1K 10K 100K CL=100pF CL=47pF GAIN (dB) RL=1kΩ GAIN (dB) VS=±7.5V RL=10kΩ 2 -2 CL=12pF -6 1M 10M -10 1K 100M 10K 100K FREQUENCY (Hz) 1M 10M 100M FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RLOAD FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CLOAD VS=±7.5V RL=10kΩ CL=8pF VS=±7.5V RL=10kΩ CL=8pF VIN VIN 50mV/DIV 2V/DIV VOUT VOUT 100ns/DIV 1µs/DIV FIGURE 3. LARGE SIGNAL TRANSIENT RESPONSE VS=±5V VS=±7.5V 100 BUFFER 10 1 0 1K FIGURE 4. SMALL SIGNAL TRANSIENT RESPONSE VOLTAGE NOISE (nV/√Hz) 1K OUTPUT IMPEDANCE (Ω) 1G FREQUENCY (Hz) 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 5. OUTPUT IMPEDANCE vs FREQUENCY 4 100 10 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 6. INPUT NOISE SPECTRAL DENSITY vs FREQUENCY FN7507.1 May 6, 2005 EL5623 Typical Performance Curves 20 60 VS=±7.5V RL=10kΩ 50 V OPP=1V OVERSHOOT (%) PSRR (dB) VS=±7.5V RL=1kΩ 0 CL=1.5pF PSRR+ -20 PSRR-40 -60 40 30 20 10 -80 1K 10K 100K 1M 0 10M 0 500 1K FIGURE 7. PSRR vs FREQUENCY FIGURE 8. OVERSHOOT vs CAPACITANCE LOAD 800 1.4 POWER DISSIPATION (W) SETTLING TIME (ns) VS=±7.5V RL=10kΩ 700 C =8pF L 600 BUFFER 500 400 300 2 3 4 5 6 STEP SIZE (+V) JEDEC JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.031W 1 θ 0.8 JA 0.6 TS SO =9 P16 7° C/ W 0.4 0.2 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 9. SETTLING TIME vs STEP SIZE 0.9 2K CLOAD (pF) FREQUENCY (Hz) 200 1.5K FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 - LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 0.8 0.7 676mW 0.6 θ TS SO 1 4 P1 6 8° C/ W JA = 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 5 FN7507.1 May 6, 2005 EL5623 Description of Operation and Application Information The maximum power dissipation allowed in a package is determined according to: Product Description T JMAX - T AMAX P DMAX = -------------------------------------------Θ JA The EL5623 is fabricated using a high voltage CMOS process. It exhibits rail to rail input and output capability and has very low power consumption. When driving a load of 10K and 12pF, the buffers have a -3dB bandwidth of 10MHz and exhibit 9V/µs slew rate. Input, Output, and Supply Voltage Range The EL5623 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range from 4.5V to 16.5V. The input common-mode voltage range of the EL5623 is within 500mV beyond the supply rails. The output swings of the buffers typically extend to within 100mV of the positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage even closer to each supply rails. Output Phase Reversal The EL5623 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diode placed in the input stage of the device begin to conduct and over-voltage damage could occur. where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = V S × I S + Σi × [ ( V S + – V OUT i ) × I LOAD i ] when sourcing, and: P DMAX = V S × I S + Σi × [ ( V OUT i – V S - ) × I LOAD i ] when sinking. where: i = 1 to total number of buffers VS = Total supply voltage of buffer and VCOM ISMAX = Total quiescent current VOUTi = Maximum output voltage of the application Output Drive Capability The EL5623 does not have internal short-circuit protection circuitry. The buffers will limit the short circuit current to ±120mA if the outputs are directly shorted to the positive or the negative supply. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output continuous current never exceeds ±30mA, a limit is set by the design of the internal metal interconnections. The Unused Buffers ILOADi = Load current of buffer If we set the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. It is recommended that any unused buffers should have their inputs tied to ground plane. Power Supply Bypassing and Printed Circuit Board Layout Power Dissipation As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, one 0.1µF ceramic capacitor should be placed from the VS+ pin to ground. A 4.7µF tantalum capacitor should then be connected from the VS+ pin to ground. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. With the high-output drive capability of the EL5623, it is possible to exceed the 125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. 6 FN7507.1 May 6, 2005 EL5623 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN7507.1 May 6, 2005