DATASHEET 40V Precision Low Power Operational Amplifiers ISL28117, ISL28217, ISL28417, ISL28417SEH The ISL28117, ISL28217, ISL28417 and ISL28417SEH are a Features family of very high precision amplifiers featuring low noise vs power consumption, low offset voltage, low bias current and low temperature drift making them the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of precision, low noise and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Low input offset voltage . . . . . . . . . . . . . . . ±50µV, maximum ISL28417SEH ±110µV, maximum Applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls and industrial controls. • Input bias current TC . . . . . . . . . . . . . . . . ±5pA/°C, maximum The ISL28117 single and ISL28217 dual are offered in 8 Ld SOIC, MSOP and TDFN packages. The ISL28417 is offered in 14 Ld SOIC, 14 Ld TSSOP packages. All devices are offered in standard pin configurations and operate over the extended temperature range from -40°C to +125°C. The ISL28417SEH is offered in a 14 Ld Hermetic Ceramic Flatpack package. The device is offered in an industry standard pin configuration and operates over the extended temperature range from -55°C to +125°C. Related Literature • Superb offset voltage TC . . . . . . . . . . . . 0.6µV/°C, maximum ISL28417SEH 1µV/°C, maximum • Input bias current. . . . . . . . . . . . . . . . . . . . . . ±1nA, maximum ISL28417SEH ±5nA, maximum • Low current consumption . . . . . . . . . . . . . . . . . . . . . . . . 440µA • Voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/Hz • Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V • Operating temperature range. . . . . . . . . . . .-40°C to +125°C ISL28417SEH -55°C to +125°C • Small package offerings in single, dual and quad • Pb-free (RoHS compliant) • No phase reversal Applications • Precision instruments • AN1508 “ISL281X7SOICEVAL1Z Evaluation Board User’s Guide” • Medical instrumentation • AN1509 “ISL282X7SOICEVAL2Z Evaluation Board User’s Guide” • Active filter blocks • Power supply control • Thermocouples and RTD reference buffers • Data acquisition 18 8.2nF V+ - VIN R1 OUTPUT R2 + 1.84k 4.93k 3.3nF C2 V- NUMBER OF AMPLIFIERS C1 VS = ± 15V 16 14 12 10 8 6 4 2 0 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 VOSTC (µV/°C) SALLEN-KEY LOW PASS FILTER (10kHz) FIGURE 1. TYPICAL APPLICATION March 30, 2016 FN6632.12 1 FIGURE 2. VOS TEMPERATURE COEFFICIENT (VOSTC) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009-2012, 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28117, ISL28217, ISL28417, ISL28417SEH Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications ISL28117, ISL28217, ISL28417(VS ± 15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications ISL28117, ISL28217, ISL28417 (VS ± 5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Specifications ISL28417SEH (VS ±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Specifications ISL28417SEH (VS ±5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISL28117, ISL28217, ISL28417, ISL28417SEH SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . License Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 23 23 23 23 24 24 24 Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L8.3x3K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDP0027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M14.173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K14.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Submit Document Feedback 2 34 34 35 36 37 38 39 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Ordering Information . PART MARKING PART NUMBER ISL28117FBBZ (Notes 1, 4, 6) VOS (MAX) (µV) PACKAGE (RoHS Compliant) PKG. DWG. # 28117 FBZ 50 (B Grade) 8 Ld SOIC M8.15E ISL28117FBZ (Notes 1, 4, 6) 28117 FBZ -C 100 (C Grade) 8 Ld SOIC M8.15E ISL28117FUBZ (Notes 3, 4, 6) 8117Z 70 (B Grade) 8 Ld MSOP M8.118B ISL28117FUZ (Notes 3, 4, 6) 8117Z -C 150 (C Grade) 8 Ld MSOP M8.118B ISL28117FRTBZ (Notes 2, 4, 6) 8117 75 (B Grade) 8 Ld TDFN L8.3x3K ISL28117FRTZ (Notes 1, 4, 6) -C 8117 150 (C Grade) 8 Ld TDFN L8.3x3K ISL28217FBBZ (Notes 1, 4, 6) 28217 FBZ 50 (B Grade) 8 Ld SOIC M8.15E ISL28217FBZ (Notes 1, 4, 6) 28217 FBZ -C 100 (C Grade) 8 Ld SOIC M8.15E ISL28217FUZ (Notes 1, 4, 6) 8217Z -C 150 (C Grade) 8 Ld MSOP M8.118B ISL28217FRTBZ (Notes 1, 4, 6) 8217 70 (B Grade) 8 Ld TDFN L8.3x3K ISL28217FRTZ (Notes 1, 4, 6) -C 8217 150 (C Grade) 8 Ld TDFN L8.3x3K ISL28417FBBZ (Notes 1, 4, 6) 28417 FBZ 120 (B Grade) 14 Ld SOIC MDP0027 ISL28417FBZ (Notes 1, 4, 6) 28417 FBZ -C 200 (C Grade) 14 Ld SOIC MDP0027 ISL28417FVBZ (Notes 1, 4, 6) 28417 FVZ 120 (B Grade) 14 Ld TSSOP M14.173 ISL28417FVZ (Notes 1, 4, 6) 28417 FVZ-C 200 (C Grade) 14 Ld TSSOP M14.173 ISL28417SEHMF (Note 5) ISL28417SEHMF 110 (B Grade) 14 Ld Flatpack K14.A ISL28417SEHF/PROTO (Note 5) ISL28417SEHF/PROTO 110 (B Grade) 14 Ld Flatpack K14.A ISL28417SEHMX (Note 5) 110 (B Grade) DIE ISL28417SEHX/SAMPLE (Note 5) 110 (B Grade) DIE ISL28117SOICEVAL1Z Evaluation Board ISL28217SOICEVAL2Z Evaluation Board NOTES: 1. Add “-T13” suffix for 2.5k unit, -T7” suffix for 1k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. Add “-T13” suffix for 6k unit, -T7” suffix for 1k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 3. Add “-T13” suffix for 2.5k unit, -T7” suffix for 1.5k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 6. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217, ISL28417. For more information on MSL please see techbrief TB363. TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS PART NUMBER NUMBER OF DEVICES PACKAGE OPERATING TEMPERATURE RANGE ISL28117 1 8 Ld SOIC -40°C to +125°C ISL28217 2 8 Ld SOIC -40°C to +125°C ISL28417 4 14 Ld SOIC -40°C to +125°C ISL28417SEH 4 14 Ld Flatpack -55°C to +125°C Submit Document Feedback 3 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Pin Configurations ISL28117 (8 LD TDFN) TOP VIEW ISL28117 (8 LD SOIC, MSOP) TOP VIEW NC 1 8 NC -IN 2 7 V+ +IN 3 6 VOUT V- 4 5 NC - + NC 1 8 NC -IN 2 +IN 3 6 VOUT 5 NC V- 4 ISL28217 (8 LD TDFN) TOP VIEW ISL28217 (8 LD SOIC, MSOP) TOP VIEW VOUT_A 1 -IN_A 2 +IN_A 3 V- 4 8 V+ - + + - VOUT_A 1 7 VOUT_B -IN_A 2 6 -IN_B +IN_A 3 5 +IN_B V- 4 -IN_A 2 14 VOUT_D A - + D + - +IN_A 3 V+ 4 - + B 13 -IN_D -IN_A 2 12 +IN_D +IN_A V- + C 9 -IN_C 8 VOUT_C VOUT_B 7 Submit Document Feedback 1 10 +IN_C +IN_B 5 -IN_B 6 VOUT_A 11 4 8 V+ 7 VOUT_B - + 6 -IN_B + - 5 +IN_B ISL28417SEH (14 LD FLATPACK) TOP VIEW ISL28417 (14 LD SOIC, TSSOP) TOP VIEW VOUT_A 1 7 V+ - + 14 VOUT_D 13 -IN_D 3 12 +IN_D V+ 4 11 V- +IN_B 5 10 +IN_C 9 -IN_C 8 VOUT_C -IN_B 6 VOUT_B 7 A - + - + B D + - + C March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Pin Descriptions ISL28117 (8 Ld SOIC, MSOP, TDFN) ISL28217 (8 Ld SOIC, MSOP, TDFN) ISL28417/SEH (14 Ld SOIC, TSSOP) (14 Ld FLATPACK) PIN NAME EQUIVALENT CIRCUIT 3 - - +IN Circuit 1 Amplifier noninverting input - 3 3 +IN_A - 5 5 +IN_B - - 10 +IN_C - - 12 +IN_D 4 4 11 V- Circuit 3 Negative power supply 2 - - -IN Circuit 1 Amplifier inverting input - 2 2 -IN_A - 6 6 -IN_B - - 9 -IN_C - - 13 -IN_D 7 8 4 V+ Circuit 3 Positive power supply 6 - - VOUT Circuit 2 Amplifier output - 1 1 VOUT_A - 7 7 VOUT_B - - 8 VOUT_C - - 14 VOUT_D 1, 5, 8 - - NC - No internal connection PD PD - PD - Thermal Pad - TDFN package only. Connect thermal pad to ground or most negative potential. V+ 500Ω V+ 500Ω IN- IN+ Submit Document Feedback VCIRCUIT 2 5 V+ CAPACITIVELY COUPLED ESD CLAMP OUT V- CIRCUIT 1 DESCRIPTION V- CIRCUIT 3 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Supply Voltage ISL28417SEH (Note 13) . . . . . . . . . . . . . . . . 40V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Voltage (ISL28417SEH) . . . . . . . . . . . . . . 20V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or <V- . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . Indefinite ESD Rating Human Body Model ISL28117, ISL28417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV ISL28217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5kV ISL28217 MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5kV ISL28417SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Charged Device Model ISL28117, ISL28217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV ISL28217 (MSOP), ISL28417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV ISL28417SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model ISL28117, ISL28217 (MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V ISL28217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V ISL28417, ISL28417SEH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 8 Ld SOIC ISL28117 (Notes 7, 10) . . . . . . . 120 60 8 Ld SOIC ISL28217 (Notes 7, 10) . . . . . . . 105 50 8 Ld MSOP ISL28117 (Notes 7, 10) . . . . . . 155 50 8 Ld MSOP ISL28217 (Notes 7, 10) . . . . . . 160 55 8 Ld TDFN ISL28117 (Notes 8, 9). . . . . . . . 48 7 8 Ld TDFN ISL28217 (Notes 8, 9). . . . . . . . 43 2 14 Ld SOIC (Notes 8, 10) . . . . . . . . . . . . . . . 73 45 14 Ld TSSOP (Notes 7, 10) . . . . . . . . . . . . . 90 32 14 Ld Flatpack (Notes 11, 12) . . . . . . . . . . 105 15 Maximum Storage Temperature Range . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile (Non-Hermetic Packages Only) . . . . . see TB493 Recommended Operating Conditions Ambient Temperature Range (TA) ISL28117, ISL28217, ISL28417. . . . . . . . . . . . . . . . . . .-40°C to +125°C ISL28417SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 9. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 10. For JC, the “case temp” location is taken at the package top center. 11. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 12. For JC, the "case temp" location is the center of the ceramic on the package underside. 13. No destructive single-event effects at effective LET of 73.9MeV•cm2/mg up to a supply of ±20V. Reference manufacturers SEE report. Submit Document Feedback 6 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28117, ISL28217, ISL28417(VS ± 15V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. PARAMETER VOS DESCRIPTION Input Offset Voltage, SOIC, TSSOP Package TEST CONDITIONS ISL28x17 B Grade MIN (Note 14) TYP MAX (Note 14) UNIT -50 8 50 µV 110 µV 4 100 µV -110 ISL28x17 C Grade -100 -190 ISL28417 B Grade -70 10 -120 ISL28417 C Grade Input Offset Voltage, MSOP Package -110 10 160 µV µV ISL28117 B Grade -70 -10 -150 4 -150 10 ISL28117 B Grade -75 -10 -160 ISL28217 B Grade -70 10 -140 ISL28x17 C Grade -150 10 -250 IB IOS Input Offset Current Input Offset Current Temperature Coefficient µV 150 µV 250 µV 75 µV 160 µV 70 µV 140 µV 150 µV 250 µV 0.6 µV/°C 0.14 0.9 µV/°C ISL28417 B Grade -0.75 0.20 0.75 µV/°C ISL28417 C Grade -0.9 0.3 0.9 µV/°C ISL28117 B Grade -0.8 0.1 0.8 µV/°C ISL28117 C Grade -1 0.14 1 µV/°C ISL28217 C Grade -1 0.14 1 µV/°C ISL28117 B Grade -0.9 0.1 0.9 µV/°C ISL28217 B Grade -0.7 0.1 0.7 µV/°C ISL28x17 C Grade -1 0.1 1 µV/°C -1 0.08 -5 1 -1.50 0.08 ISL28417 SOIC, TSSOP B and C Grade 1 nA 1.5 nA 5 pA/°C 1.50 nA 1.85 nA -3 0.42 3 pA/°C -4.00 0.45 4.00 pA/°C Input Voltage Range Guaranteed by CMRR test -13 VCM = -13V to +13V 120 PSRR Power Supply Rejection Ratio VS = ±2.25V to ±20V 120 13 120 V 145 dB 145 dB 120 7 µV 0.14 Common-Mode Rejection Ratio Submit Document Feedback 150 250 -0.9 CMRR VCM µV -0.6 -1.85 TCIOS µV ISL28x17 C Grade -1.5 Input Bias Current Temperature Coefficient 70 150 ISL28x17 B Grade Input Bias Current TCIB µV 200 -250 Input Offset Voltage Temperature Coefficient; TDFN Package µV 110 -160 ISL28217 C Grade Input Offset Voltage Temperature Coefficient; MSOP Package 120 -200 -250 Input Offset Voltage Temperature Coefficient; SOIC, TSSOP Package µV TA = -40°C to +85°C ISL28117 C Grade TCVOS µV 70 TA = -40°C to +125°C -150 Input Offset Voltage, TDFN Package 190 dB dB March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28117, ISL28217, ISL28417(VS ± 15V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 14) TYP MAX (Note 14) UNIT AVOL Open-Loop Gain VO = -13V to +13V, RL = 10kΩ to ground 130 143 dB VOH Output Voltage High RL = 10kΩ to ground 13.5 13.7 V RL = 2kΩ to ground 13.30 13.55 V 13.2 V 13.1 VOL Output Voltage Low IS Supply Current/Amplifier ISC Short-Circuit VSUPPLY V RL = 10kΩ to ground -13.7 -13.5 -13.2 V RL = 2kΩ to ground -13.55 -13.30 V 0.44 -13.1 V 0.53 mA 0.68 mA 43 Supply Voltage Range Guaranteed by PSRR ±2.25 V mA ±20 V AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k, RL = 2kΩ 1.5 MHz enVp-p Voltage Noise VP-P 0.1Hz to 10Hz 0.25 µVP-P en in THD + N Voltage Noise Density f = 10Hz 10 nV/Hz f = 100Hz 8.2 nV/Hz f = 1kHz 8 nV/Hz f = 10kHz 8 nV/Hz Current Noise Density f = 1kHz 0.1 pA/Hz Total Harmonic Distortion 1kHz, G = 1, VO = 3.5VRMS, RL = 2kΩ 0.0009 % 1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ 0.0005 % TRANSIENT RESPONSE SR tr, tf, Small Signal ts tOL Slew Rate, VOUT 20% to 80% AV = 11, RL = 2kΩVO = 4VP-P 0.5 V/µs Rise Time 10% to 90% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩto VCM 130 ns Settling Time to 0.1% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 5kΩto VCM 21 µs Settling Time to 0.01% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 5kΩto VCM 24 µs Settling Time to 0.1% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩto VCM 13 µs Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩto VCM 18 µs Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩ to VCM 5.6 µs Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩ to VCM 10.6 µs Submit Document Feedback 8 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28117, ISL28217, ISL28417 (VS ± 5V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Note 14) TYP MAX (Note 14) UNIT -50 8 50 µV 110 µV MIN PARAMETER VOS DESCRIPTION Input Offset Voltage, SOIC, TSSOP Package TEST CONDITIONS ISL28x17 B Grade -110 ISL28x17 C Grade -100 4 -190 ISL28417 B Grade -70 10 -120 Input Offset Voltage, MSOP Package ISL28417 C Grade -110 TA = -40°C to +85°C -160 TA = -40°C to +125°C -200 ISL28117 B Grade -70 10 -10 -150 ISL28117 C Grade -150 4 -250 ISL28217 C Grade -150 10 -250 Input Offset Voltage, TDFN Package ISL28117 B Grade -75 -10 -70 -150 Input Offset Voltage Temperature Coefficient; SOIC, TSSOP Package Input Offset Voltage Temperature Coefficient; MSOP Package Input Offset Voltage Temperature Coefficient; TDFN Package IB IOS Input Offset Current VCM CMRR Input Offset Current Temperature Coefficient 9 160 µV 200 µV 70 µV 150 µV 150 µV 250 µV 150 µV 250 µV 70 µV 140 µV 10 150 µV 250 µV -0.60 0.14 0.60 µV/°C -0.90 0.14 0.90 µV/°C ISL28417 B Grade -0.75 0.20 0.75 µV/°C ISL28417 C Grade -0.9 0.3 0.9 µV/°C ISL28117 B Grade -0.8 0.1 0.8 µV/°C ISL28117 C Grade -1 0.14 1 µV/°C ISL28217 C Grade -1 0.14 1 µV/°C ISL28117 B Grade -0.9 0.1 0.9 µV/°C ISL28217 B Grade -0.7 0.1 0.7 µV/°C ISL28x17 C Grade -1 0.1 1 µV/°C -1 0.18 ISL28417 SOIC, TSSOP B and C Grade nA nA 1 5 pA/°C -1.5 0.3 1.5 nA 1.85 nA -3 0.42 3 pA/°C -4.00 0.45 4.00 pA/°C 3 V -3 VCM = -3V to +3V 1 1.5 -5 120 120 Submit Document Feedback µV ISL28x17 B Grade Input Voltage Range Common-Mode Rejection Ratio µV 110 10 -1.85 TCIOS 120 µV -1.5 Input Bias Current Temperature Coefficient µV ISL28x17 C Grade Input Bias Current TCIB 70 µV -250 TCVOS µV 75 -140 ISL28x17 C Grade µV 160 -160 ISL28217 B Grade 100 190 145 dB dB March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28117, ISL28217, ISL28417 (VS ± 5V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) MIN PARAMETER PSRR DESCRIPTION Power Supply Rejection Ratio TEST CONDITIONS VS = ±2.25V to ±5V (Note 14) TYP 120 145 MAX (Note 14) UNIT dB 120 dB AVOL Open-Loop Gain VO = -3.0V to +3.0V, RL = 10kΩ to ground 130 143 dB VOH Output Voltage High RL = 10kΩ to ground 3.5 3.7 V 3.2 RL = 2kΩ to ground 3.30 V 3.55 V 3.1 VOL IS ISC Output Voltage Low V RL = 10kΩ to ground -3.7 -3.5 -3.2 V RL = 2kΩ to ground -3.55 -3.30 V -3.1 V 0.53 mA 0.68 mA Supply Current/Amplifier 0.44 Short-Circuit 43 V mA AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k, RL = 2kΩ 1.5 MHz enp-p Voltage Noise 0.1Hz to 10Hz 0.25 µVP-P Voltage Noise Density f = 10Hz 12 nV/Hz f = 100Hz en in 8.6 nV/Hz f = 1kHz 8 nV/Hz f = 10kHz 8 nV/Hz f = 1kHz 0.1 pA/Hz AV=11, RL = 2kΩVO = 4VP-P 0.5 V/µs AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 ns Settling Time to 0.1% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM 12 µs Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM 19 µs Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P RL = 2kΩ to VCM 7 µs 5.8 µs Current Noise Density TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% tr, tf, Small Signal Rise Time 10% to 90% of VOUT ts tOL Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P RL = 2kΩ to VCM Submit Document Feedback 10 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28417SEH (VS ±15V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage Drift IIB Input Bias Current TA = +25°C, post radiation TCIOS VCM CMRR MAX (Note 14) UNIT 10 85 µV 110 µV 0.1 1 µV/°C 0.08 2.5 nA -5 5 nA -15 15 nA -2.5 TA = -55°C, +125°C IOS TYP Input Offset Voltage TCVOS TCIIB MIN (Note 14) Input Bias Current Temperature Coefficient Input Offset Current -5 1 5 pA/°C -2.50 0.08 2.50 nA TA = -55°C, +125°C -3 3 nA TA = +25°C, post radiation -6 6 nA 3 pA/°C 13 V Input Offset Current Temperature Coefficient -3 Input Voltage Range Guaranteed by CMRR test -13 Common-Mode Rejection Ratio VCM = -13V to +13V 120 0.42 145 dB 120 PSRR Power Supply Rejection Ratio VS = ±2.25V to ±20V 120 dB 145 dB 120 dB AVOL Open-Loop Gain VO = -13V to +13V, RL = 10kΩ to ground 3,000 14,000 V/mV VOH Output Voltage High RL = 10kΩ to ground 13.5 13.7 V 13.2 RL = 2kΩ to ground 13.30 V 13.55 V 13.0 VOL Output Voltage Low RL = 10kΩ to ground -13.7 RL = 2kΩ to ground IS ISC VSUPPLY -13.55 Supply Current/Amplifier 0.44 Short-Circuit Current Supply Voltage Range V -13.5 V -13.2 V -13.30 V -13.0 V 0.53 mA 0.68 mA 43 Guaranteed by PSRR ±2.25 mA ±20 V AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k, RL = 2kΩ 1.5 MHz enVp-p Voltage Noise VP-P 0.1Hz to 10Hz 0.25 µVP-P Voltage Noise Density f = 10Hz 10 nV/√Hz f = 100Hz 8.2 nV/√Hz f = 1kHz 8 nV/√Hz f = 10kHz 8 nV/√Hz en Submit Document Feedback 11 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28417SEH (VS ±15V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued) PARAMETER in THD + N DESCRIPTION CONDITIONS MIN (Note 14) TYP MAX (Note 14) UNIT Current Noise Density f = 1kHz 0.1 pA/√Hz Total Harmonic Distortion 1kHz, G = 1, VO = 3.5VRMS, RL = 2kΩ 0.0009 % 1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ 0.0005 % 0.5 V/µs TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% AV = 11, RL = 2kΩ, VO = 4VP-P 0.3 0.2 tr, tf, Small Signal V/µs Rise Time 10% to 90% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 450 625 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 600 ns 700 ns Settling Time to 0.1% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 5kΩ to VCM 21 µs Settling Time to 0.01% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 5kΩto VCM 24 µs Settling Time to 0.1% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM 13 µs Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM 18 µs tOL Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩ to VCM 5.6 µs Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩ to VCM OS+ Positive Overshoot ts OS- Negative Overshoot ns 10.6 µs AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩ to VCM 15 % AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩ to VCM 15 33 % % 33 % Electrical Specifications ISL28417SEH (VS ±5V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. PARAMETER VOS DESCRIPTION Offset Voltage Drift IIB Input Bias Current IOS MIN (Note 14) Input Offset Voltage TCVOS TCIIB TEST CONDITIONS -2.50 UNIT 10 150 µV 250 µV 0.1 1 µV/°C 0.18 2.50 nA -5 5 nA TA = +25°C, post radiation -15 15 nA Input Offset Current 12 MAX (Note 14) TA = -55°C, +125°C Input Bias Current Temperature Coefficient Submit Document Feedback TYP -5 1 5 pA/°C -2.5 0.3 2.5 nA 3 nA 6 nA TA = -55°C, +125°C -3 TA = +25°C, post radiation 6 0.42 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28417SEH (VS ±5V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued) MIN (Note 14) TYP MAX (Note 14) UNIT Input Offset Current Temperature Coefficient -3 0.42 3 pA/°C Input Voltage Range -3 3 V PARAMETER TCIOS VCM CMRR DESCRIPTION Common-Mode Rejection Ratio TEST CONDITIONS VCM = -3V to +3V 120 145 dB 120 PSRR Power Supply Rejection Ratio VS = ±2.25V to ±5V 120 dB 145 dB 120 dB AVOL Open-Loop Gain VO = -3.0V to +3.0V RL = 10kΩ to ground 3,000 14,000 V/mV VOH Output Voltage High RL = 10kΩ to ground 3.5 3.7 V 3.2 RL = 2kΩ to ground 3.300 V 3.550 V 3.0 VOL Output Voltage Low RL = 10kΩ to ground RL = 2kΩ to ground IS ISC Supply Current/Amplifier V -3.7 -3.55 0.44 Short-Circuit Current -3.5 V -3.2 V -3.30 V -3.0 V 0.53 mA 0.68 mA 43 mA AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k, RL = 2kΩ 1.5 MHz enp-p Voltage Noise 0.1Hz to 10Hz 0.25 µVP-P Voltage Noise Density f = 10Hz 12 nV/√Hz f = 100Hz 8.6 nV/√Hz f = 1kHz 8 nV/√Hz f = 10kHz 8 nV/√Hz f = 1kHz 0.1 pA/√Hz Slew Rate, VOUT 20% to 80% AV = 11, RL = 2kΩ, VO = 4VP-P 0.5 V/µs Rise Time 10% to 90% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM 130 ns Settling Time to 0.1% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM 12 µs Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM 19 µs en in Current Noise Density TRANSIENT RESPONSE SR tr, tf, Small Signal ts Submit Document Feedback 13 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Electrical Specifications ISL28417SEH (VS ±5V) VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued) PARAMETER tOL DESCRIPTION MIN (Note 14) TEST CONDITIONS TYP MAX (Note 14) UNIT Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P RL = 2kΩ to VCM 7 µs Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P RL = 2kΩ to VCM 5.8 µs OS+ Positive Overshoot AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩ to VCM 15 % OS- Negative Overshoot AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩ to VCM 15 % NOTE: 14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. 140 140 VS = ±5V ISL28217FBBZ 120 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 120 100 80 60 40 20 100 80 60 40 20 0 -50 -30 -10 10 VOS (µV) 30 0 -50 50 -30 -10 10 VOS (µV) 30 50 FIGURE 4. VOS DISTRIBUTION FOR GRADE B FIGURE 3. VOS DISTRIBUTION FOR GRADE B 300 300 VS = ± 15V ISL28217FBZ 200 150 100 VS = ± 5V ISL28217FBZ 250 NUMBER OF AMPLIFIERS 250 NUMBER OF AMPLIFIERS VS = ±15V ISL28217FBBZ 200 150 100 50 50 0 -100 -60 -20 20 VOS (µV) 60 FIGURE 5. VOS DISTRIBUTION FOR GRADE C Submit Document Feedback 14 100 0 -100 -60 -20 20 VOS (µV) 60 100 FIGURE 6. VOS DISTRIBUTION FOR GRADE C March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 100 18 VS = ± 15V NUMBER OF AMPLIFIERS 50 VOS (µV) VS = ± 15V 16 0 -50 14 12 10 8 6 4 2 -100 -50 0 50 100 0 150 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 VOSTC (µV/°C) TEMPERATURE (°C) FIGURE 7. VOS RANGE vs TEMPERATURE FIGURE 8. TCVOS vs NUMBER OF AMPLIFIERS 100 16 VS = ± 5V VS = ±5V 14 NUMBER OF AMPLIFIERS VOS (µV) 50 0 -50 12 10 8 6 4 2 -100 -50 0 50 TEMPERATURE (°C) 100 0 150 FIGURE 9. VOS RANGE vs TEMPERATURE -0.15 0 0.15 VOSTC (µV/°C) 0.30 0.45 70 VS = ± 15V 400 VS = ±15V 60 NUMBER OF AMPLIFIERS 300 200 IB+ (pA) -0.30 FIGURE 10. TCVOS vs NUMBER OF AMPLIFIERS 500 100 0 -100 -200 -300 50 40 30 20 10 -400 -500 -50 -0.45 0 50 100 TEMPERATURE (°C) FIGURE 11. IB+ RANGE vs TEMPERATURE Submit Document Feedback 15 150 0 -3.5 -2.5 -1.5 -0.5 0.5 1.5 IB+TC (pA/°C) 2.5 3.5 MORE FIGURE 12. TCIB+ vs NUMBER OF AMPLIFIERS March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 70 500 VS = ± 15V 400 VS = ±15V 60 NUMBER OF AMPLIFIERS 300 200 IB- (pA) 100 0 -100 -200 -300 40 30 20 10 -400 -500 -50 50 0 50 TEMPERATURE (°C) 100 0 150 500 NUMBER OF AMPLIFIERS 100 0 -100 -200 -300 3.5 VS = ±5V 60 50 40 30 20 0 50 100 0 150 -3.5 -2.5 -1.5 TEMPERATURE (°C) -0.5 0.5 1.5 2.5 3.5 IB+TC (pA/°C) FIGURE 15. IB+ RANGE vs TEMPERATURE FIGURE 16. TCIB+ vs NUMBER OF AMPLIFIERS 90 500 VS = ± 5V 400 VS = ±5V 80 NUMBER OF AMPLIFIERS 300 200 100 IB- (pA) 2.5 10 -400 0 -100 -200 -300 70 60 50 40 30 20 10 -400 -500 -50 -0.5 0.5 1.5 IB-TC (pA/°C) 70 200 IB+ (pA) -1.5 80 VS = ± 5V 300 -500 -50 -2.5 FIGURE 14. TCIB- vs NUMBER OF AMPLIFIERS FIGURE 13. IB- RANGE vs TEMPERATURE 400 -3.5 0 50 100 TEMPERATURE (°C) FIGURE 17. IB- RANGE vs TEMPERATURE Submit Document Feedback 16 150 0 -3.5 -2.5 -1.5 -0.5 0.5 1.5 IB-TC (pA/°C) 2.5 3.5 FIGURE 18. TCIB- vs NUMBER OF AMPLIFIERS March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 90 500 VS = ± 15V 400 NUMBER OF AMPLIFIERS 300 IOS (pA) 200 100 0 -100 -200 -300 70 60 50 40 30 20 10 -400 -500 -50 VS = ±15V 80 0 50 100 0 150 -3.5 -2.5 -1.5 FIGURE 19. IOS RANGE vs TEMPERATURE 1.5 2.5 3.5 100 VS = ± 5V 400 VS = ±5V 90 80 NUMBER OF AMPLIFIERS 300 200 IOS (pA) 0.5 FIGURE 20. IOSTC vs NUMBER OF AMPLIFIERS 500 100 0 -100 -200 -300 -400 -500 -50 -0.5 TCIOS (pA/°C) TEMPERATURE (°C) 70 60 50 40 30 20 10 0 50 100 0 150 -3.5 -2.5 -1.5 TEMPERATURE (°C) FIGURE 21. IOS RANGE vs TEMPERATURE -0.5 0.5 1.5 TCIOS (pA/°C) 2.5 3.5 FIGURE 22. IOSTC vs NUMBER OF AMPLIFIERS 20000 0.7 VO = ±13V ±15V ±2.25V AVOL (V/mV) ISUPPLY (mA) 0.6 0.5 15000 0.4 0.3 -50 0 50 TEMPERATURE (°C) 100 150 FIGURE 23. SUPPLY CURRENT PER AMPLIFIERS vs TEMPERATURE Submit Document Feedback 17 10000 -50 0 50 TEMPERATURE (°C) 100 150 FIGURE 24. AVOL vs TEMPERATURE March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves -140 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) -130 VS = ±2.25V TO ±20V VCM = ±13V -135 -145 CMRR (dB) PSRR (dB) -140 -150 -145 -150 -155 -155 -50 0 50 TEMPERATURE (°C) 100 -160 -50 150 FIGURE 25. PSRR vs TEMPERATURE 0 50 TEMPERATURE (°C) 60 ISC- AT ±15V 55 55 50 50 45 ISC- (mA) ISC+ (mA) ISC+ AT ±15V 40 40 35 30 30 50 TEMPERATURE (°C) 100 25 -50 150 FIGURE 27. POSITIVE SHORT-CIRCUIT CURRENT vs TEMPERATURE 50 TEMPERATURE (°C) 100 150 100 80 VS = ±15V VS = ±5V 80 +125°C 60 60 40 +125°C VOS (µV) 40 +25°C 20 0 20 +25°C 0 -40°C -40°C -20 -20 -40 -60 0 FIGURE 28. NEGATIVE SHORT-CIRCUIT CURRENT vs TEMPERATURE 100 VOS (µV) 45 35 0 150 FIGURE 26. CMRR vs TEMPERATURE 60 25 -50 100 -40 -15 -10 -5 0 5 10 VCM (V) FIGURE 29. INPUT VOS vs INPUT COMMON-MODE VOLTAGE, VS = ±15 Submit Document Feedback 18 15 -60 -5 -3 -1 1 3 5 VCM (V) FIGURE 30. INPUT VOS vs INPUT COMMON-MODE VOLTAGE, VS = ±5V March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves 14.4 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) -13.2 VS = ±15V RL = 10kΩ 14.2 -13.6 VOL (V) VOH (V) 14.0 13.8 -13.8 13.6 -14.0 13.4 -14.2 13.2 -50 0 50 TEMPERATURE (°C) 100 -14.4 -50 150 FIGURE 31. VOH vs TEMPERATURE 14.4 0 150 VS = ±15V RL = 2kΩ -13.4 VOL (V) -13.6 13.8 -13.8 13.6 -14.0 13.4 -14.2 13.2 -50 0 50 100 -14.4 -50 150 0 TEMPERATURE (°C) 50 100 150 TEMPERATURE (°C) FIGURE 33. VOH vs TEMPERATURE FIGURE 34. VOL vs TEMPERATURE 100 250 VS = ±18.2V AV = 1 200 150 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV) 100 -13.2 14.0 100 50 0 -50 -100 -150 V+ = 36.4V -200 Rg = 10, Rf = 100k -250 50 TEMPERATURE (°C) FIGURE 32. VOL vs TEMPERATURE, VS = ±15V RL = 2kΩ 14.2 VOH (V) VS = ±15V RL = 10kΩ -13.4 AV = 10,000 0 1 2 3 4 5 6 7 8 TIME (s) FIGURE 35. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz Submit Document Feedback 19 9 10 10 1 1 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 36. INPUT NOISE VOLTAGE SPECTRAL DENSITY March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 1 OPEN LOOP GAIN (dB)/PHASE (°) INPUT NOISE CURRENT (pA/√Hz) VS = ±18.2V AV = 1 0.1 1 10 100 1k 10k 100k 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m 1m 10m 100m PHASE GAIN 1 220 VS = ±5V 140 GAIN 120 VS = ±15V 100 80 60 40 20 1 10 100 1k RL = INF CL = 10pF SIMULATION 0 1m 10m 100m 1 10k 100k 1M 10M 100M 70 60 PSRR+ AND PSRR- VS = ±2.25V 70 RL = INF CL = 4pF 40 AV = +1 30 VCM = 1VP-P GAIN (dB) PSRR (dB) Rg = 100, Rf = 100k AV = 1000 Rg = 1k, Rf = 100k 50 80 20 40 30 20 0 PSRR+ AND PSRR- VS = ±15V 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M FIGURE 41. PSRR vs FREQUENCY, VS = ±5V, ±15V Submit Document Feedback 20 10M VS = ±20V CL = 4pF RL = 10k VOUT = 50mVP-P AV = 100 AV = 10 Rg = 10k, Rf = 100k 10 10 -10 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 40. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V 110 50 1M 10M 100M 160 120 60 10k 100k 180 PHASE FIGURE 39. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ CL = 100pF 90 1k VS = ±2.5V 200 FREQUENCY (Hz) 100 100 FIGURE 38. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ CL = 10pF CMRR (dB) OPEN LOOP GAIN (dB)/PHASE (°) FIGURE 37. INPUT NOISE CURRENT SPECTRAL DENSITY 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 100pF -60 SIMULATION -80 -100 0.1m 1m 10m 100m 10 FREQUENCY (Hz) FREQUENCY (Hz) AV = 1 -10 10 Rg = OPEN, Rf = 0 100 10k 100k FREQUENCY (Hz) 1k 1M 10M FIGURE 42. FREQUENCY RESPONSE vs CLOSED LOOP GAIN March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 4 2 Rf = Rg = 100k 2 0 0 Rf = Rg = 10k -2 -4 -1 Rf = Rg = 1k GAIN (dB) NORMALIZED GAIN (dB) RL = 10k 1 -6 Rf = Rg = 100 -8 VS = ±20V RL = 10k -10 CL = 4pF -12 AV = +2 -14 VOUT = 50mVP-P -16 10 -3 RL = 1k -4 VS = ±20V -5 AV = +1 -7 10k 100k 1M 2 VS = ±2.5V RL = 10k -1 GAIN (dB) CL = 0.01µF CL = 47pF 0 -2 -4 CL = 4pF CL = 470pF -6 CL = 1000pF 100 10k 1k 100k 1M VS = ±15V -2 -3 VS = ±20V -4 -5 CL = 4pF RL = 10k -6 AV = +1 -7 V OUT = 50mVP-P CL = 100pF CL = 270pF -8 10 VS = ±5V 0 4 2 -810 10M 100 1k FREQUENCY (Hz) FIGURE 45. GAIN vs FREQUENCY vs CL 2.4 160 2.0 VS = ±15V 80 RL-DRIVER CH. = OPEN 60 RL-RECEIVING CH. = 10k 0 10 LARGE SIGNAL (V) CROSSTALK (dB) 1.2 120 20 1M 10M 1.6 140 40 10k 100k FREQUENCY (Hz) FIGURE 46. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 180 100 10M VS = ±2.25V 1 AV = +1 VOUT = 50mVP-P 6 1M FIGURE 44. GAIN vs FREQUENCY vs RL 12 8 100k FREQUENCY (Hz) FIGURE 43. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE Rf/Rg 10 10k 1k 100 FREQUENCY (Hz) GAIN (dB) RL = 100 VOUT = 50mVP-P -8 10 10M RL = 499 CL = 4pF -6 1k 100 RL = 4.99k -2 CL = 4pF AV = +1 VSOURCE = 1VP-P 100 1k 0.4 0 VS = ±5V, RL = 2k, 10k -0.4 -0.8 CL = 4pF AV = +1 VOUT = 4VP-P -1.2 -1.6 -2.0 10k 100k FREQUENCY (Hz) FIGURE 47. CROSSTALK, VS = ±15V Submit Document Feedback VS = ±15V, RL = 2k, 10k 0.8 21 1M 10M -2.4 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 48. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±5V, ±15V March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) INPUT (V) RL = 10k CL = 4pF AV = +1 VOUT = 50mVP-P 20 10 -0.12 -0.16 -0.20 -0.24 -0.28 0 40 4 80 0.20 2 70 0 60 0.04 -6 0 -8 0 10 20 30 40 50 50 60 TIME (µs) 70 80 90 -2 100 VS = ±15V RL = 10k AV = 1 VOUT = 50mVP-P 50 O 40 30 20 INPUT OUTPUT AT VS = ±15V -0.04 40 - -4 30 T 0.08 -2 OUTPUT (V) RL = 2k CL = 4pF AV = -100 Rf = 100k, Rg = 1k VIN = 200mVP-P 0.12 OVERSHOOT (%) 0.24 OUTPUT AT VS = ±5V 20 FIGURE 50. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V, ±15V FIGURE 49. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V 0.16 10 O 35 + 30 T 20 25 TIME (µs) 0 SH O 15 2 VE R 10 4 O 5 6 OUTPUT AT VS= ±5V VE RS HO 0 8 RL = 2k CL = 4pF AV = -100 Rf = 100k, Rg = 1k VIN = 200mVP-P O SMALL SIGNAL (mV) 10 OUTPUT AT VS = ±15V -0.08 VS = ±15V 30 -0.08 12 -0.04 40 0 INPUT (V) INPUT 0 50 -10 14 0.04 OUTPUT (V) 60 60 70 80 90 -10 10 -12 100 0 1 10 TIME (µs) 100 1k CAPACITANCE (pF) 10k 100k FIGURE 52. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V FIGURE 51. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V, ±15V 100M INPUT RESISTANCE (kΩ) 10M 1M 100k 10k 1k 100 10 1 0.01 0.1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 53. COMMON-MODE INPUT IMPEDANCE Submit Document Feedback 22 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Applications Information V+ Functional Description The ISL28117, ISL28217, ISL28417 and ISL28417SEH are single, dual and quad, low noise precision op amps. Both devices are fabricated in a new precision 40V complementary bipolar DI process. A super-beta NPN input stage with input bias current cancellation provides low input bias current (180pA typical), low input offset voltage (13µV typical), low input noise voltage (8nV/Hz) and low 1/f noise corner frequency (~8Hz). These amplifiers also feature high open loop gain (18kV/mV) for excellent CMRR (145dB) and THD+N performance (0.0005% at 3.5VRMS, 1kHz into 2kΩ). A complimentary bipolar output stage enables high capacitive load drive without external compensation. Operating Voltage Range The devices are designed to operate over the 4.5V (±2.25V) to 40V (±20V) range and are fully characterized at 10V (±5V) and 30V (±15V). The Power Supply Rejection Ratio typically exceeds 140dB over the full operating voltage range and 120dB minimum over the -40°C to +125°C temperature range. The worst case common-mode input voltage range over-temperature is 2V to each rail. With ±15V supplies, CMRR performance is typically >130dB over-temperature. The minimum CMRR performance over the -40°C to +125°C temperature range is >120dB for power supply voltages from ±5V (10V) to ±15V (30V). Input Performance The super-beta NPN input pair provides excellent frequency response while maintaining high input precision. High NPN beta (>1000) reduces input bias current while maintaining good frequency response, low input bias current and low noise. Input bias cancellation circuits provide additional bias current reduction to <1nA and excellent temperature stabilization. Figures 11 through 18 show the high degree of bias current stability at ±5V and ±15V supplies that is maintained across the -40°C to +125°C temperature range. The low bias current TC also produces very low input offset current TC, which reduces DC input offset errors in precision, high impedance amplifiers. The +25°C maximum input offset voltage (VOS) for the “B” grade is 50µV and 100µV for the “C” grade. Input offset voltage temperature coefficients (VOSTC) are a maximum of ±0.6µV/°C for the “B” and ±0.9µV/°C for the “C” grade. Figures 3 through 6 show the typical gaussian-like distribution over the ±5V to ±15V supply range and over the full temperature range. The VOS temperature behavior is smooth (Figures 7 through 10) maintaining constant TC across the entire temperature range. Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, series connected 500Ω current limiting resistors and an anti-parallel diode pair across the inputs (Figure 54). - 500Ω VIN VOUT + 500Ω RL V- FIGURE 54. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN The series resistors limit the high feed-through currents that can occur in pulse applications when the input dv/dt exceeds the 0.5V/µs slew rate of the amplifier. Without the series resistors, the input can forward-bias the anti-parallel diodes causing current to flow to the output resulting in severe distortion and possible diode failure. Figure 48 provides an example of distortion free large signal response using a 4VP-P input pulse with an input rise time of <1ns. The series resistors enable the input differential voltage to be equal to the maximum power supply voltage (40V) without damage. In applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails, current limiting resistors may be needed at the input terminal to limit the current through the power supply ESD diodes to 20mA maximum. Output Current Limiting The output current is internally limited to approximately ±45mA at +25°C and can withstand a short-circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability. Figures 27 and 28 show the current limit variation with temperature. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28117, ISL28217, ISL28417 and ISL28417SEH are immune to output phase reversal, even when the input voltage is 1V beyond the supplies. Unused Channels The user must configure unused channel(s) to prevent them from oscillating. The unused channel(s) oscillates if the input and output pins are floating. This results in higher than expected supply currents and possible noise injection into the other channel(s) being used. The proper way to prevent this oscillation is to short the output to the inverting input and ground the positive input, as shown in Figure 55. - + FIGURE 55. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Submit Document Feedback 23 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Power Dissipation License Statement It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. (EQ. 1) T JMAX = T MAX + JA xPD MAXTOTAL Where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S I qMAX + V S - V OUTMAX ---------------------------R L (EQ. 2) Where: • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application ISL28117, ISL28217, ISL28417, ISL28417SEH SPICE Model Figure 56 shows the SPICE model schematic and Figure 57 shows the net list for the ISL28117, ISL28217, ISL28417 and ISL28417SEH SPICE model for a Grade “B” part. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC parameters are VOS, IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 7. The AVOL is adjusted for 155dB with the dominant pole at 0.02Hz. The CMRR is set (210dB, fcm = 10Hz). The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. Figures 58 through 68 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Closed Loop Gain vs RL, Large Signal Step Response, Open Loop Gain Phase and Simulated CMRR vs Frequency. Submit Document Feedback 24 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH . V++ V++ R3 R4 4.45k 4.45k 4 CASCODE 5 Q4 C4 2pF VIN- VIN- - + D1 3 SUPERB DX EOS 1 IOS MIRROR VCM + - 5E11 + - en Vmid 9 IEE 200E-6 R2 VC + - + - Q3 0.3nA 290 C5 2pF 8 7 5E11 C6 1.2pF R17 In+ VIN+ 5 6 R1 0.1V 25 4 Q1 Q2 24 DN CASCODE Q5 2 SUPERB V5 D12 IEE1 96E-6 + VOS - 13E-6 V-VCM Voltage Noise Input Stage V++ V++ 10 + - 4 5 D2 DX + V1 - 1.86V G3 13 + - R5 1 D4 DX + V3 - 1.86V 11 - V2 1.86V + D3 DX 1ST Gain Stage 14 - 17 Vc 1.99e10 V4 1.86V R10 2.1E3 C3 400pF Vg R12 1 G6 18 VCM D5 DX 2nd Gain Stage 15.9159E-3 R11 1 Vmid R8 L1 + - R9 2.1E3 C2 400pF 1.99e10 G4 + - 12 + V-VCM R6 1 G2 + R7 Vg VC Vmid G5 + - G1 Mid Supply Ref L2 15.9159E-3 V-- Common-Mode Gain Stage V++ E2 22 ISY 0.44mA Vg D6 DX 23 20 G7 + V5 1.12V V- V6 21 + DX - D7 1.12V G8 + + E3 V- V-- D10 DY + G9 + - R15 90 - + - D9 DX + + - D8 DX V+ D11 DY VOUT VOUT R16 90 + - V+ G10 Output Stage Supply Isolation Stage FIGURE 56. SPICE SCHEMATIC Submit Document Feedback 25 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH *ISL28117 Macromodel - covers following *Loading effects on closed loop frequency *products *response *ISL28117 *Input noise terms including 1/f effects *ISL28217 *Slew rate *ISL28417 and ISL28417SEH *Input and Output Headroom limits to I/O **Revision History: *Revision C, LaFontaine January 31, 2012 *Model for Noise, quiescent supply currents, *voltage swing *Supply current at nominal specified supply *voltages *CMRR 210dB, fcm=10Hz, AVOL 155dB ** *f=0.02Hz, SR = 0.5V/us, output voltage *clamp and short ckt current limit. *Device performance features NOT * *supported by this model: *Harmonic distortion effects *Copyright 2012 by Intersil Corporation Refer *to data sheet "LICENSE STATEMENT", Use *of this model indicates your acceptance with *the terms and provisions in the License *Statement. *Post Radiation effects *Disable operation (if any) *Thermal effects and/or over temperature *Intended use: *parameter variation *This Pspice Macromodel is intended to give *Limited performance variation vs. supply *typical DC and AC performance *voltage is modeled *characteristics under a wide range of *Part to part performance variation due to *external circuit configurations using *compatible simulation platforms - such as *iSim PE. *normal process parameter spread *Any performance difference arising from *different packaging ** *Device performance features supported by * source : *+input *this model *Typical, room temp., nominal power supply *|-input *voltages used to produce the following * | | |-Vsupply *characteristics: * | | | |output *Open and closed loop I/O impedances *||||| *Open loop gain and phase *Closed loop bandwidth and frequency *response * | | +Vsupply .subckt ISL28117 Vin+ Vin- V+ V- VOUT * source ISL28107subckt * *Voltage Noise E_En IN+ VIN+ 25 0 1 R_R17 25 0 290 D_D12 24 25 DN V_V7 24 0 0.1 * *Input Stage I_IOS IN+ VIN- DC 0.08E-9 C_C6 IN+ VIN- 1.2E-12 R_R1 VCM VIN- 5e11 R_R2 IN+ VCM 5e11 Q_Q1 2 VIN- 1 SuperB Q_Q2 3 8 1 SuperB Q_Q3 V-- 1 7 Mirror Q_Q4 4 6 2 Cascode Q_Q5 5 6 3 Cascode R_R3 4 V++ 4.45e3 R_R4 5 V++ 4.45e3 C_C4 VIN- 0 2e-12 C_C5 8 0 2e-12 D_D1 6 7 DX I_IEE 1 V-- DC 200e-6 I_IEE1 V++ 6 DC 96e-6 V_VOS 9 IN+ 8e-6 E_EOS 8 9 VC VMID 1 * *1st Gain Stage G_G1 V++ 11 4 5 8.129384e-2 G_G2 V-- 11 4 5 8.129384e-2 R_R5 11 V++ 1 R_R6 V-- 11 1 D_D2 10 V++ DX D_D3 V-- 12 DX V_V1 10 11 1.86 V_V2 11 12 1.86 * *2nd Gain Stage G_G3 V++ VG 11 VMID 2.83e-3 G_G4 V-- VG 11 VMID 2.83e-3 R_R7 VG V++ 1.99e10 R_R8 V-- VG 1.99e10 C_C2 VG V++ 4e-10 C_C3 V-- VG 4e-10 D_D4 13 V++ DX D_D5 V-- 14 DX V_V3 13 VG 1.86 V_V4 VG 14 1.86 * *Mid supply Ref R_R9 VMID V++ 2.1E3 R_R10 V-- VMID 2.1E3 I_ISY V+ V- DC 0.44E-3 E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 * *Common Mode Gain Stage with Zero G_G5 V++ VC VCM VMID 3.162277 G_G6 V-- VC VCM VMID 3.162277 R_R11 VC 17 1 R_R12 18 VC 1 L_L1 17 V++ 15.9159E-3 L_L2 18 V-- 15.9159E-3 FIGURE 57. SPICE NET LIST Submit Document Feedback 26 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Characterization vs Simulation Results 100 VS = ±18.2V AV = 1 INPUT NOISE VOLTAGE (nV/Hz) INPUT NOISE VOLTAGE (nV/Hz) 100 10 1 1 10 100 1k FREQUENCY (Hz) 10k 10 1.0 1.0 100k 60 100k Rg = 100, Rf = 100k AV = 1000 Rg = 1k, Rf = 100k VS = ±20V CL = 4pF RL = 10k VOUT = 50mVP-P AV = 100 30 20 40 AV = 10 20 AV = 10 Rg = 10k, Rf = 100k AV = 1 0 Rg = OPEN, Rf = 0 -10 10 100 VS = ±15V CL = 4pF RL = 10k VOUT = 50mVP-P AV = 100 Rg = 10k, Rf = 100k 10 0 Rg = 1k, Rf = 100k GAIN (dB) GAIN (dB) 10k FIGURE 59. SIMULATED INPUT NOISE VOLTAGE Rg = 100, Rf = 100k AV = 1000 50 10k 1k 100k 1M AV = 1 -10 10 10M Rg = OPEN, Rf = 0 100 FREQUENCY (Hz) FIGURE 60. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY 0 -1 -3 GAIN (dB) RL = 4.99k -2 RL = 1k -4 -7 -8 10 10M RL = 10k 0 -6 1.0M 1 RL = 10k 1 -5 1.0k 10k 100k FREQUENCY (Hz) FIGURE 61. SIMULATED CLOSED LOOP GAIN vs FREQUENCY 2 GAIN (dB) 1.0k 70 70 40 100 FREQUENCY (Hz) FIGURE 58. CHARACTERIZED INPUT NOISE VOLTAGE 60 10 VS = ±20V RL = 499 RL = 1k -2 -4 VS = ±15V CL = 4pF CL = 4pF -6 A = +1 V AV = +1 RL = 100 VOUT = 50mVP-P 100 RL = 4.99k 1k 10k 100k VOUT = 50mVP-P 1M FREQUENCY (Hz) FIGURE 62. CHARACTERIZED CLOSED LOOP GAIN vs RL Submit Document Feedback 27 10M -8 10 100 RL = 499 RL =100 1.0k 10k 100k FREQUENCY (Hz) 1.0M 10M FIGURE 63. SIMULATED CLOSED LOOP GAIN vs RL March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Characterization vs Simulation Results (Continued) 3 2.4 2.0 2 1.6 INPUT VS = ±15V, RL =10k 0.8 0.4 0 -0.4 -0.8 CL = 4pF AV = +1 VOUT = 4VP-P -1.2 -1.6 -2.0 -2.4 0 10 20 30 40 -1 50 60 TIME (µs) 70 80 90 -3 100 CL = 4pF AV = +1 VOUT = 4VP-P 0 20 40 60 80 100 TIME (µs) FIGURE 65. SIMULATED LARGE SIGNAL 10V STEP RESPONSE 200 OPEN LOOP GAIN (dB)/PHASE (°) OPEN LOOP GAIN (dB)/PHASE (°) 0 -2 FIGURE 64. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±15V 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m 1m 10m 100m OUTPUT 1 LARGE SIGNAL (V) LARGE SIGNAL (V) 1.2 PHASE GAIN 1 10 100 1k 10k 100k 1M 10M 100M 160 PHASE 120 80 40 GAIN 0 -40 1.0m 10m 0.1 1 FREQUENCY (Hz) 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 66. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY FIGURE 67. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY 250 CMRR (dB) 200 150 100 50 1m 10m 0.1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 68. SIMULATED CMRR vs FREQUENCY Submit Document Feedback 28 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Metallization Mask Layout -IN_A VOUT_A -IN_D VOUT_D +IN_A +IN_D PLACE HOLDER V+ V- +IN_B +IN_C -IN_B -IN_C VOUT_C VOUT_B TABLE 2. DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD VOUT_A 3 -256 1152 70 70 1 -IN_A 4 -661 1152 70 70 1 +IN_A 5 -867.5 948.5 70 70 1 V+ 9 -880.5 0 70 70 1 +IN_B 13 -867.5 -948.5 70 70 1 -IN_B 14 -661 -1152 70 70 1 VOUT_B 15 -256 -1152 70 70 1 VOUT_C 16 256 -1152 70 70 1 -IN_C 17 661 -1152 70 70 1 +IN_C 18 867.5 -948.5 70 70 1 V- 22 880.5 0 70 70 1 +IN_D 26 867.5 948.5 70 70 1 -IN_D 1 661 1152 70 70 1 VOUT_D 2 256 1152 70 70 1 NOTE: Origin of coordinates is the center of die. Submit Document Feedback 29 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE March 30, 2016 FN6632.12 Removed Note that references SMD for the ISL28417SEH from ordering information table on page 3 and removed ISL28417SEH from MSL note due to not applicable. March 16, 2016 FN6632.11 -Added the ISL28417SEH throughout the datasheet. -Updated POD L8.3x3k to most recent revision with change as follows: Tiebar Note 5 updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). -Added about Intersil verbiage -Electrical Specifications Table Title on page 7: Added ISL28117, ISL28217, ISL28417 (VS ± 15V). -Electrical Specifications Table Title on page 9: Added ISL28117, ISL28217, ISL28417 (VS ± 5V). September 11, 2012 FN6632.10 Feature on page 1: Added No phase reversal. Removed from ordering information QFN parts ISL28417FRZ (not release part) on Page 3. Removed all instances of QFN through document (front page, table of contents, thermal information, pin description and POD. Added to the typical performance curves table figure 53 on page 22: Common-mode input impedance. February 23, 2012 FN6632.9 “Ordering Information” on page 2: Removed “Coming soon” from ISL28417FVZ and changed Part Marking column from "28417 FVZ" to 28417 FVZ-C". Changed "-40 to +125" to "200 C-grade” Added new Part Number ISL28417 FVBZ Electrical Spec changes: VOS Description Section: page 7 & page 9: Changed “Input Offset Voltage; SOIC Package” to Input Offset Voltage; SOIC, TSSOP Package” TCVOS Description section: page 7 & page 9: Changed;Input Offset Voltage Temperature Coefficient; SOIC Package to Input Offset Voltage Temperature Coefficient; SOIC, TSSOP Package TCIOS Conditions section: page 7 & page 9: Changed "ISL28417 SOIC B and C Grade” to "ISL28417 SOIC, TSSOP B and C Grade”. “Ordering Information” on page 3: Updated Pkg. Dwg. # for ISL28117FUBZ, ISL28117FUZ, ISL28217FUBZ & ISL28217FUZ from M8.118 to M8.118B Updated Pkg. Dwg. # for ISL28117FRTBZ, ISL28117FRTZ, ISL28217FRTBZ & ISL28217FRTZ from L8.3x3A to L8.3x3K Updated Pkg. Dwg. # for ISL28417FRZ from L16.4x4 to L16.4x4E “Thermal Information” on page 6: Added JA and JC for 16 Ld QFN and 14 Ld TSSOP Figure 52, “% OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V” on page 22: X-Axis (Capacitance pF) values 1k and 10k were shifted 1 decade to the right. Shifted 1 decade to the left and added new label "100k" at the extreme right (where the "10k" value was located). Added dual and quad to the “SPICE NET LIST” on page 26. “Package Outline Drawing” on page 35: Changed from M8.118 to M8.118B Top View: Package width & height changed from 3.0±0.05 to 3.0±0.1 Package height from lead to lead changed from 4.9±0.15 to 4.9±0.2 Side View 2: Lead thickness changed from 0.09-0.20 to 0.15±0.05mm Side View 1: Package height changed from 0.85±0.10 to 0.86±0.05 Changed lead width from 0.25-0.036 to 0.23-0.36 Detail X: Foot of lead length changed from 0.55±0.15 to 0.53±0.10 “Package Outline Drawing” on page 36: Changed from L8.3x3A to L8.3x3K Bottom View: Changed lead height from 0.3±0.1 to 0.4±0.05 Changed lead width from 0.30±0.05 to 0.25±0.05 Land Pattern: Changed lead width from 0.30 to 0.25 Submit Document Feedback 30 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION October 11, 2011 FN6632.8 CHANGE Figure 27 added “Positive” to Short-Circuit Current title Figure 28 added “Negative” to Short-Circuit Current title Figure 36 y axis label units changed from (nV/√Hz) to (nV/√Hz) Figure 37 y axis label units changed from pA/√hz to pA/√Hz Figure 31, 33 changed from VOUT vs Temperature to VOH vs Temperature Figure 32, 34 changed from VOUT vs Temperature to VOL vs Temperature Table of Contents on page 5 updated to list all package outline drawings Changed POD M14.15 to MDP0027 Changed TCIos for ISL28417 SOIC grade B and C on pages 7 and 9 from ±3.5pA/C to ±4.0pA/C 1. Pg 2 Ordering Information: a.Added ordering information rows for ISL28417FBBZ (B grade) and ISL28417FBZ (C grade). b. Add Table of Contents 2. Pg 5 Abs Max and Thermal Information Tables: a. Added HBM, MM and CDM ESD levels for the ‘417 b. Added JA and JC values for the 14 Ld SOIC 3. Pg 6 ±15V electrical Specs a. Added ISL28417 B & C grade VOS and limits b. Added ISL28417 B & C grade TCVOS and limits c. Added ISL28417 B & C grade TCIOS and limits 4. Pg 7 a. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV typ to 130dB and 143dB respectively 5. Pg 8 ±5V electrical Specs a. Added ISL28417 B & C grade VOS and limits 6. Pg 9 a. Added ISL28417 B & C grade TCVOS and limits b. Added ISL28417 B & C grade TCIOS and limits c. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV Typ to 130dB and 143dB respectively 7. Pg 17 Applications Information a. Added Unused Channels paragraph and Figure 54. July 12, 2011 FN6632.7 1. Releasing ISL28217FUZ MSOP Grade C package. Remove 'Coming Soon' from Order Information Table 2. Page 5, added: Machine Model (ISL28217 MSOP only). . . . . 300V 3. Under Electrical Spec ±15V and ±5V tables, changed Typical Rise Time and Fall Time from: Rise Time 100ns, Fall Time 120ns, to: Rise Time 130ns, Fall Time 130ns. 4. Under Electrical Spec ±15V and ±5V table for Vos and TCVos, added in row for ISL28217 MSOP Grade C package. Added Vos and TCVos limits for 25C and Full Temp. 5. For Typical performance curves for Vos Histograms, added note that histogram is based on ISL28217FBBZ for Grade B figures and ISL28217FBZ for Grade C figures. (Figures 3-6, added part number label to graph below Vs) 6. Under Electrical Spec ±15V and ±5V tables, changed TYP for Open Loop Gain from 18,000V/mV to 14,000V/mV December 2, 2010 FN6632.6 1. Updated “Ordering Information” table on page 3. Removed Coming Soon for ISL28117FRTBZ and ISL28117FUBZ parts. Added in the Vos (MAX) numbers in those rows (75 and 70 respectively). 2. Corrected part marking in “Ordering Information” table on page 3 for ISL28117FRTZ from 8117 -C to -C 8117 3. Corrected part marking in “Ordering Information” table on page 3 for ISL28217FRTZ from 8217 -C to -C 8217 4. Updated Tape & Reel note in “Ordering Information” table on page 3 from “Add "-T7", "-T7A" or "-T13" suffix for tape and reel." to new standard "Add "-T*" suffix for tape and reel." The "*" covers all possible tape and reel options 5. Updated “Electrical Specifications” Table for “VOS” on page 7 and “TCVOS” on page 7 a. Added data row for Offset Voltage; MSOP Grade B Package; ISL28117 b. Added data row for Offset Voltage; TDFN Grade B Package; ISL28117 c. Added data row for Input Offset Voltage Temperature Coefficient; MSOP Grade B Package; ISL28117 d. Added data row for Input Offset Voltage Temperature Coefficient; TDFN Grade B Package; ISL28117 6. Removed "Temperature data established by characterization" from common conditions of spec table. Removed note "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." from Min Max columns of spec table. Replaced with new standard note in Min Max columns, “Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.” Submit Document Feedback 31 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE August 31, 2010 FN6632.5 1. General changes: a. Added in Quad devices to the datasheet for SOIC, TSSOP and QFN packages. b. Added in TDFN packages for single and dual devices. c. Added in new VOS and TCVOS limits for TDFN packages d. Added Tja and Tjc Notes for TDFN Package which are “direct attach (Tja) ” and “bottom (Tjc)” 2. Specific changes: a. Added in ISL28417 to title and front page info on page 1 b. Added in ISL28117FRTZ, ISL28117FRTBZ, ISL28217FRTZ, ISL28217FRTBZ, ISL28417FBZ, ISL28417FVZ and ISL28417FRZ packages to Ordering information on page 3 and page 3. Added in -T7 and -T7A tape and reel extensions where applicable. c. Added in TDFN, 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN to pin configurations on page 4 and page 3. d. Updated Pin Descriptions tables with new added in packages on page 5. e. Abs Max Table added in thermal packaging info for TDFN packages on page 6. f. Electrical Specifications Table - Added two new line items for VOS spec. TDFN package ISL28217 Grade B limits ±70uV 25C and ±140uV full temp. TDFN package ISL28x17 Grade C limits ±150uV 25C and ±250uV full temp on page 7 and page 9. g. Electrical Specifications Table - Added two new line items for TCVOS spec. TDFN package ISL28217 Grade B limits ±0.7uV/C full temp. TDFN package ISL28x17 Grade C limits ±1uV/C on page 7 and page 9. h. Added in PODs for L8.3x3A, M14.15, M14.173 and L16.4x4 March 18, 2010 FN6632.4 1. Updated “Ordering Information” on page 3 by adding two rows for MSOP packages ISL28117FUBZ and ISL28117FUZ, which are scheduled to release Q2 2010. Added Pinout accordingly. 2. Added POD for MSOP M8.118 to the end of datasheet 3. In “Ordering Information” on page 3, Separated each part number with it's own specific -T7 and -T13 suffix and removed “Add “-T7” or “-T13” suffix for Tape and Reel.” from Note 1. 4. Updated ±15 and ±5V Electrical Specification table with the following edits: A) Separated VOS specs for SOIC and MSOP Grade C packages. Added new VOS specs for MSOP Grade C package. B) Separated TCVOS specs for SOIC and MSOP Grade C packages. Added new TCVOS specs for MSOP Grade C package. 5. Added “Thermal Information” on page 6 for ISL28117 MSOP package. Added page1. Added Evaluation Boards to “Ordering Information” on page 3. Added Theta JC values to “Thermal Information” on page 6. Added applicable Theta JC Note 7. Updated Theta JA for ISL28217 8 Ld SOIC from 115°C/W to 105°C/W. Part marking in “Ordering Information” on page 3 changed as follows: ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ" ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C" ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ" ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C" On page 14: Changed label in Figure 3 from “VS = +5V” to “VS = ±5V” On page 14: Changed label in Figure 4 from “VS = +15V” to “VS = ±15V” Changed Typical VOS spec from “13” to “8” (B Grade), “19” to “4” (C Grade), IB from “0.18” to “0.08, IOS from “0.3” to “0.08”. Edited Spice Schematic - L1 from “95.4957” to “15.9159E”, R1 from “6k” to 1, R9 from “1” to “2.1E3”, R10 from “1” to “2.1E3, R12 from “6k” to “1”, L2 from “95.4957” to “15.9159E”. Edited Spice Net List - Changed Revision from “A” to “B”, Date change from “October 29th 2009” to “November 20th 2009”, added after AOL “SR = 0.5V/µsec, Input Stage changed in I_IOS from “0.3E-9” to 0.08E-9”, V_VOS “13e-6” to “8e-6”, Mid supply Ref R_R9 and R_R10 changed “1” to “2.1E3”, Common-Mode Gain Stage with Zero change in G_G5 and G_G6 “5.27046e-15” to “3.162277”, R_R11 and R_R12 “6.3” to “1”, L_L1 and L_L2 “95.4957” to “15.9159E-3” November 12, 2009 FN6632.3 Submit Document Feedback 32 Updated Typical Performance Curves Figure 5, 7, 9, 11, 13, 15, 17 and 19. Added Spice Model and license statement. Replaced typical application schematic. March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE October 16, 2009 FN6632.2 On page 3 “Ordering Information”, changed the following: a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B". Corrected part marking for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B" B) Updated package outline drawing to most recent revision (no changes were made to package dimensions; land pattern was added and dimensions were moved from table onto drawing) c) Added "Add “-T7” or “-T13” suffix for tape and reel." to the tape and reel Note 1. d) added Note 3 callout to all parts (Note 3 reads: “For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217. For more information on MSL please see techbrief TB363.") e) removed "Coming Soon" from ISL28117FBBZ, ISL28117FBZ & ISL28217FBBZ devices October 8, 2009 FN6632.1 1. Removed “very” from “...low noise..” 1st sentence, page 1. 2. Removed “Low” from 6th bullet under features, page 1. 3. Modified typical characteristics curves to show conservative performance. Specific channel designations removed. On temperature curves, changed formatting to indicate range from typical value. Changes include: a. Removed former Figures 1, 3, 5, 7, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34, 37 & 38 (all Channel A curves) b. Replaced former Figures 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39 & 40 with new Figures 9 thru 20 (all “conservative channels”) c. Added Figures 30, 31, 32 4. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same graphic) 5. Added temp labels to Figures 28 & 29 September 3, 2009 FN6632.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 33 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 34 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Package Outline Drawing M8.118B 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 3/12 3.0±0.10mm 5 A D 8 4.9±0.20mm DETAIL "X" 3.0±0.10mm 5 1.10 MAX 0.15±0.05mm PIN# 1 ID SIDE VIEW 2 1 2 B 0.65mm BSC TOP VIEW 0.95 REF 0.86±0.05mm H GAUGE PLANE C 0.25 SEATING PLANE 0.23 - 0.36mm 0.08 M C A-B D 0.10 ± 0.05mm 3°±3° 0.10 C 0.53 ± 0.10mm SIDE VIEW 1 DETAIL "X" (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 35 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Package Outline Drawing L8.3x3K 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 5/15 2X 1.95 3.00 6X 0.65 A B 1 PIN #1 INDEX AREA 3.00 6 6 PIN 1 INDEX AREA (4X) 1.50 ±0.10 0.15 8 TOP VIEW 8X 0.25 ±0.05 0.40 ± 0.05 4 0.10 M C A B 2.30 ±0.10 BOTTOM VIEW SEE DETAIL "X" C 0.10 C 0.75 ±0.05 0 . 203 REF 5 C 0 . 02 NOM. 0 . 05 MAX. 0.08 C SIDE VIEW DETAIL "X" ( 2.30) ( 1.95) NOTES: ( 8X 0.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured (1.50) ( 2.90 ) between 0.15mm and 0.20mm from the terminal tip. PIN 1 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be (6x 0.65) ( 8 X 0.25) either a mold or mark feature. TYPICAL RECOMMENDED LAND PATTERN 7. Submit Document Feedback 36 Compliant to JEDEC MO-229 WEEC-2 except for the foot length. March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Package Outline Drawing Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C L b 0.010 M C A B 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL20) SO24 (SOL24) SO28 (SOL28) TOLERANCE NOTES 0.104 0.104 0.104 0.104 MAX - A 0.068 0.068 0.068 A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 14 16 16 20 24 28 Reference N 8 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 Submit Document Feedback 37 March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 14 SEE DETAIL "X" 8 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 38 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. March 30, 2016 FN6632.12 ISL28117, ISL28217, ISL28417, ISL28417SEH Package Outline Drawing Ceramic Metal Seal Flatpack Packages (Flatpack) K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B) 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A e INCHES A SYMBOL PIN NO. 1 ID AREA -A- D -B- S1 b E1 0.004 M H A-B S Q D S 0.036 M H A-B S D S C E -D- A -C- -HE2 L E3 SEATING AND BASE PLANE c1 L E3 LEAD FINISH BASE METAL (c) b1 M M (b) MIN MILLIMETERS MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.390 - 9.91 3 E 0.235 0.260 5.97 6.60 - E1 - 0.290 - 7.11 3 E2 0.125 - 3.18 - - E3 0.030 - 0.76 - 7 2 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 L 0.270 0.370 6.86 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 M - 0.0015 - 0.04 - N 14 14 Rev. 0 5/18/94 SECTION A-A NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 39 March 30, 2016 FN6632.12