40V Precision Single Supply Rail-to-Rail Output Low Power Operational Amplifiers ISL28108, ISL28208, ISL28408 Features The ISL28108, ISL28208 and ISL28408 are single, dual and quad low power precision amplifiers optimized for single supply applications. These devices feature a common mode input voltage range extending to 0.5V below the V- rail, a rail-to-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which make them ideal for single supply applications where input operation at ground is important. • Single or dual supply, rail-to-rail output and below ground (V-) input capability Added features include low offset voltage, and low temperature drift making them the ideal choice for applications requiring high DC accuracy. The output stage is capable of driving large capacitive loads from rail-to-rail for excellent ADC driving performance. The devices can operate for single or dual supply from 3V (±1.5V) to 40V (±20V) and are fully characterized at ±5V and ±15V. The combination of precision, low power, and small footprint provide the user with outstanding value and flexibility relative to similar competitive parts. • Low noise current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80fA/√Hz Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply control, and industrial control. • Rail-to-rail input differential voltage range for comparator applications • Single supply range . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V • Low current consumption (VS = ±5V). . . . . . . . . . . . . . . 165µA • Low noise voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 15.8nV/√Hz • Low input offset voltage (ISL28108) . . . . . . . . . . . . . . 150µV • Superb temperature drift - Voltage offset TC . . . . . . . . . . . . . . . . . . . . . . 0.1µV/°C, Typ • Low input bias current . . . . . . . . . . . . . . . . . . . . . . . . -13nA Typ • Operating temperature range. . . . . . . . . . . .-40°C to +125°C • No phase reversal Applications • Precision instruments The ISL28108 single is offered in 8 Ld TDFN, MSOP and SOIC packages. The ISL28208 dual amplifier is offered in 8 Ld TDFN, MSOP, and SOIC packages. The ISL28408 is offered in 14 Ld SOIC package. All devices are offered in standard pin configurations and operate over the extended temperature range of -40°C to +125°C. • Medical instrumentation • Data acquisition • Power supply control • Industrial process control Related Literature • AN1658, “ISL28208SOICEVAL2Z Evaluation Board User Guide” RF IN- 10kΩ RIN+ IN+ 10kΩ - +3V to 40V V+ ISL28108 V- + GAIN = 10 VS = ±15V 300 VOUT 200 RREF+ 100kΩ 100 -40°C +25°C +125°C 0 -100 -200 -300 VREF -400 -500 -16 SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER 1 -15.5 -15 -14.5 -14 13 13.5 14 14.5 15 INPUT COMMON MODE VOLTAGE (V) FIGURE 1. TYPICAL APPLICATION CIRCUIT March 4, 2014 FN6935.5 400 VOS (µV) RINRSENSE 500 100kΩ LOAD FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LCC 2011, 2013, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28108, ISL28208, ISL28408 Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications, VS ±15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications, VS ±5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Stage Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISL28108, ISL28208, ISL28408 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 21 21 22 22 22 Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outline Drawing, M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package Outline Drawing, L8.3x3K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outline Drawing, M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing, M14.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Submit Document Feedback 2 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL28108FBZ 28108 FBZ -40 to +125 8 Ld SOIC M8.15E ISL28108FRTZ 108Z -40 to +125 8 Ld TDFN L8.3x3K Coming soon ISL28108FUZ 8108Z -40 to +125 8 Ld MSOP M8.118B ISL28208FBZ 28208 FBZ -40 to +125 8 Ld SOIC M8.15E ISL28208FRTZ 208F -40 to +125 8 Ld TDFN L8.3x3K ISL28208FUZ 8208Z -40 to +125 8 Ld MSOP M8.118B ISL28408FBZ 28408 FBZ -40 to +125 14 Ld SOIC M14.15 ISL28208SOICEVAL2Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to Tech Brief TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28108, ISL28208, ISL28408. For more information on MSL please see Tech Brief TB363. Submit Document Feedback 3 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Pin Configurations ISL28108 (8 LD MSOP, SOIC) TOP VIEW ISL28108 (8 LD TDFN) TOP VIEW NC 1 NC 1 7 V+ -IN 2 6 VOUT +IN V- 8 NC -IN 2 - + +IN 3 PAD V- 4 5 NC 1 -IN_A 2 +IN_A 3 V- PAD + - 4 7 V+ 3 6 VOUT 4 5 NC VOUT _A 1 -IN_A 2 6 -IN_B +IN_A 3 5 +IN_B V- 4 8 V+ 7 VOUT_B - + NC - + ISL28208 (8 LD MSOP, SOIC) TOP VIEW ISL28208 (8 LD TDFN) TOP VIEW VOUT_A 8 8 V+ 7 VOUT_B - + + - 6 -IN_B 5 +IN_B ISL28408 (14 LD SOIC) TOP VIEW VVOUT_A OUT_A 1 -IN_A 2 -IN_A 14 V VOUT_A OUT_D A - + D + - +IN_A 3 +IN_A +IN_D 12 +IN _D V 11 V- V V+ + 4 +IN_C 10 +IN_C +IN_B 5 +IN_B -IN_B 6 - IN_B VVOUT_B OUT_B 7 Submit Document Feedback 4 IN _D 13 --IN_D - + B + C -IN_CC 9 -IN_ 8 V VOUT_C O UT_C FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Pin Descriptions ISL28108 (8 Ld SOIC, MSOP, TDFN) ISL28208 (8 Ld SOIC, MSOP, TDFN) ISL28408 (14 Ld SOIC) PIN NAME EQUIVALENT CIRCUIT 3 - - +IN Circuit 1 Amplifier non-inverting input - 3 3 +IN_A - 5 5 +IN_B - - 10 +IN_C - - 12 +IN_D 4 4 11 V- Circuit 3 Negative power supply 2 - - -IN Circuit 1 Amplifier inverting input - 2 2 -IN_A - 6 6 -IN_B - - 9 -IN_C - - 13 -IN_D 7 8 4 V+ Circuit 3 Positive power supply 6 - - VOUT Circuit 2 Amplifier output - 1 1 VOUT_A - 7 7 VOUT_B - - 8 VOUT_C - - 14 VOUT_D 1, 5, 8 - - NC - No internal connection PAD PAD - PAD - Thermal Pad - TDFN package only. Connect thermal pad to ground or most negative potential. IN- V+ V+ IN+ OUT V- VCIRCUIT 2 CIRCUIT 1 Submit Document Feedback 5 DESCRIPTION V+ CAPACITIVELY TRIGGERED ESD CLAMP V- CIRCUIT 3 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Voltage . . . . . . . 42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . Indefinite ESD Tolerance (ISL28208, ISL28408) Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 6kV Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 400V Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV ESD Tolerance (ISL28108) Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 5.5kV Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV ESD Tolerance (ISL28108 MSOP package only) Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld SOIC Package (208, Notes 4, 7). . . . . . . 120 55 8 Ld SOIC Package (108, Notes 4, 7) . . . . . . . 120 60 8 Ld TDFN Package (208, Notes 5, 6) . . . . . . 47 6 8 Ld TDFN Package (108, Notes 5, 6) . . . . . . 45 3.5 8 Ld MSOP Package (208, Notes 4, 7). . . . . . 150 50 8 Ld MSOP Package (108, Notes 4, 7). . . . . . 165 57 14 Ld SOIC Package (408, Notes 4, 7). . . . . . 71 37 Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . -40°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . +150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V (±1.5V) to 40V (±20V) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For θJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications, VS ±15 VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface entries apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. PARAMETER VOS DESCRIPTION Input Offset Voltage CONDITIONS ISL28208 ISL28408 ISL28108 SOIC, TDFN MIN (Note 8) TYP -230 25 -330 -150 10 -270 TCVOS ΔVOS Input Offset Voltage Temperature Coefficient Input Offset Voltage Match (ISL28208 only) Input Bias Current Input Bias Current Temperature Coefficient Submit Document Feedback 6 230 µV 330 µV 150 µV 270 µV 0.1 1.1 µV/°C ISL28208 MSOP -40°C to +125°C 0.2 1.5 µV/°C ISL28208 TDFN ISL28408 -40°C to +125°C 0.2 1.4 µV/°C ISL28108 SOIC, TDFN -40°C to +125°C 0.2 1.2 µV/°C 5 300 µV -400 400 µV -420 420 µV ISL28208 SOIC, TDFN -300 -43 -13 -63 TCIB UNIT ISL28208 SOIC -40°C to +125°C ISL28208 MSOP IB MAX (Note 8) nA nA 0.07 nA/°C FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Electrical Specifications, VS ±15 VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface entries apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) PARAMETER IOS DESCRIPTION Input Offset Current CONDITIONS ISL28208 MIN (Note 8) TYP MAX (Note 8) UNIT -3 0 3 nA 4 nA 4 nA 5 nA -4 ISL28108 SOIC, TDFN ISL28408 CMRR Common-Mode Rejection Ratio 0 -5 VCM = V- -0.5V to V+ -1.8V 119 dB VCM = V- -0.2V to V+ -1.8V 123 dB VCM = V- to V+ -1.8V Common Mode Input Voltage Range Guaranteed by CMRR test PSRR Power Supply Rejection Ratio VS = 3V to 40V, VCMIR = Valid Input Voltage AVOL Open-Loop Gain VO = -13V to +13V, RL = 10kΩ to ground VCMIR -4 102 dB 105 123 dB 102 115 dB V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V 110 128 dB 109 124 dB 117 126 dB 100 VOL VOH IS Output Voltage Low, VOUT to V- RL = 10kΩ Output Voltage High, V+ to VOUT RL = 10kΩ Supply Current/Amplifier RL = Open dB 52 85 mV 145 mV 110 mV 150 mV 185 250 µA 270 350 µA 70 ISC+ Output Short Circuit Source Current RL = 10Ω to V- 19 mA ISC- Output Short Circuit Sink Current RL = 10Ω to V+ 30 mA VSUPPLY Supply Voltage Range Guaranteed by PSRR 3 40 V AC SPECIFICATIONS GBWP Gain Bandwidth Product ACL = 101, VO = 100mVP-P, RL = 2kΩ 1.2 MHz enp-p Noise Voltage 0.1Hz to 10Hz; VS = +18V 580 nVP-P en Noise Voltage Density f = 10Hz; VS = +18V 18 nV/√Hz en Noise Voltage Density f = 100Hz; VS = +18V 16 nV/√Hz en Noise Voltage Density f = 1kHz; VS = +18V 15.8 nV/√Hz en Noise Voltage Density f = 10kHz; VS = +18V 15.8 nV/√Hz in Noise Current Density f = 10kHz; VS = +18V 80 fA/√Hz THD + N Total Harmonic Distortion + Noise 1kHz, AV = 1, VO = 3.5VRMS, RL =10kΩ 0.00042 % TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩ, VO = 10VP-P 0.45 V/µs tr, tf, Small Signal Rise Time, VOUT 10% to 90% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 264 ns Fall Time, VOUT 90% to 10% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 254 ns Settling Time to 0.01% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, Rg = Rf =10k, RL = 2kΩ to VCM 27 µs ts Submit Document Feedback 7 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Electrical Specifications, VS ±5V VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface entries apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. PARAMETER VOS DESCRIPTION Input Offset Voltage CONDITIONS ISL28208 ISL28408 ISL28108 SOIC, TDFN MIN (Note 8) TYP -230 25 -330 -150 10 -270 TCVOS ΔVOS IB Input Offset Voltage Temperature Coefficient MAX (Note 8) UNIT 230 µV 330 µV 150 µV 270 µV ISL28208 SOIC -40°C to +125°C 0.1 1.1 µV/°C ISL28208 MSOP -40°C to +125°C 0.2 1.5 µV/°C ISL28208 TDFN ISL28408 -40°C to +125°C 0.2 1.4 µV/°C ISL28108 SOIC, TDFN -40°C to +125°C 0.2 1.2 µV/°C 3 300 µV 400 µV Input Offset Voltage Match (ISL28208 only) -300 -400 Input Bias Current -43 -15 nA -63 TCIB Input Bias Current Temperature Coefficient -40°C to +125°C IOS Input Offset Current ISL28208 nA -3 0 -4 ISL28108 SOIC, TDFN ISL28408 CMRR VCMIR PSRR AVOL Common-Mode Rejection Ratio nA/°C -0.067 -4 0 -5 3 nA 4 nA 4 nA 5 nA VCM = V- -0.5V to V+ -1.8V 101 dB VCM = V- -0.2V to V+ -1.8V 123 dB 89 dB VCM = V- to V+ -1.8V ISL28108, ISL28208 105 123 dB 100 112 dB VCM = V- to V+ -1.8V ISL28408 105 123 dB 97 112 dB Common Mode Input Voltage Range Guaranteed by CMRR test Power Supply Rejection Ratio VS = 3V to 10V, VCMIR = Valid Input Voltage All except ISL28208 MSOP 110 126 dB 109 123 dB ISL28208 MSOP VS = 3V to 10V, VCMIR = Valid Input Voltage 109 126 dB 107 123 dB VO = -3V to +3V, RL = 10kΩ to ground 117 124 dB Open-Loop Gain V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V 99 VOL VOH Output Voltage Low, VOUT to V- RL = 10kΩ Output Voltage High, V+ to VOUT RL = 10kΩ Submit Document Feedback 8 dB 23 30 38 mV 48 mV 65 mV 70 mV FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Electrical Specifications, VS ±5V VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface entries apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) PARAMETER IS DESCRIPTION Supply Current/Amplifier CONDITIONS RL = Open MIN (Note 8) TYP MAX (Note 8) UNIT 165 250 µA 240 350 µA ISC+ Output Short Circuit Source Current RL = 10Ω to V- 14 mA ISC- Output Short Circuit Sink Current 22 mA RL = 10Ω to V+ AC SPECIFICATIONS GBW Gain Bandwidth Product ACL = 101, VO = 100mVP-P, RL = 2kΩ 1.2 MHz enp-p Noise Voltage 0.1Hz to 10Hz 600 nVP-P en Noise Voltage Density f = 10Hz 18 nV/√Hz en Noise Voltage Density f = 100Hz 16 nV/√Hz en Noise Voltage Density f = 1kHz 15.8 nV/√Hz en Noise Voltage Density f = 10kHz 15.8 nV/√Hz in Noise Current Density f = 10kHz 90 fA/√Hz TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩ, VO = 4VP-P 0.4 V/µs tr, tf, Small Signal Rise Time, VOUT 10% to 90% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 264 ns Fall Time, VOUT 90% to 10% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 254 ns Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, Rg = Rf =10k, RL = 2kΩ to VCM 14.4 µs ts NOTE: 8. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. Submit Document Feedback 9 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 400 VOS (µV) FIGURE 3. ISL28408 SOIC INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V 140 160 120 80 100 60 40 300 VS = ±15V VS = ±5V 250 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS VOS (µV) FIGURE 4. ISL28408 SOIC INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V 300 200 150 100 50 0 250 200 150 100 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 0 VOS (µV) FIGURE 5. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V VOS (µV) FIGURE 6. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V 200 200 VS = ±15V VS = ±5V NUMBER OF AMPLIFIERS 150 100 50 0 150 100 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 0 VOS (µV) FIGURE 7. ISL28108 SOIC INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V Submit Document Feedback 10 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 NUMBER OF AMPLIFIERS 0 160 140 120 80 100 60 40 0 20 -20 -40 -60 -80 0 -100 0 -120 50 -140 50 20 100 -20 100 150 -40 150 200 -60 200 250 -80 250 300 -100 300 VS = ±5V 350 -120 NUMBER OF AMPLIFIERS 350 -160 VS = ±15V -160 NUMBER OF AMPLIFIERS 400 VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. -140 Typical Performance Curves VOS (µV) FIGURE 8. ISL28108 SOIC INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 25 25 NUMBER OF AMPLIFIERS 20 15 10 5 0 20 15 10 5 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 0 VOS (µV) FIGURE 9. ISL28108 TDFN INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V VOS (µV) FIGURE 10. ISL28108 TDFN INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V 30 25 VS = ±5V NUMBER OF AMPLIFIERS 20 15 10 5 25 20 15 10 5 0 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS VS = ±15V 0 VS = ±5V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS VS = ±15V TCVOS (µV/C) TCVOS (µV/C) VS = ±15V 24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±5V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS 24 22 20 18 16 14 12 10 8 6 4 2 0 FIGURE 12. ISL28408 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS FIGURE 11. ISL28408 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V TCVOS (µV/C) TCVOS (µV/C) FIGURE 13. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V Submit Document Feedback 11 FIGURE 14. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±5V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VS = ±15V NUMBER OF AMPLIFIERS 24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS Typical Performance Curves TCVOS (µV/C) FIGURE 15. ISL28208 TDFN AND MSOP TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V TCVOS (µV/C) FIGURE 16. ISL28208 TDFN AND MSOP TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V VS = ±5V 25 20 15 10 5 0 25 20 15 10 5 0 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS 30 30 VS = ±15V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS 35 TCVOS (µV/C) FIGURE 17. ISL28108 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V TCVOS (µV/C) FIGURE 18. ISL28108 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V 14 14 VS = ±5V 12 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS VS = ±15V 10 8 6 4 2 0 12 10 8 6 4 2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 TCVOS (µV/C) TCVOS (µV/C) FIGURE 19. ISL28108 TDFN TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V Submit Document Feedback 12 FIGURE 20. ISL28108 TDFN TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 70 60 VS = ±2.25V 50 40 VS = ±5V 30 20 10 0 VS = ±15V -10 VS = ±20V -20 -30 -40 -50 -40 -20 0 20 40 60 80 TEMPERATURE (°C) VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 0 VS = ±21V -5 -20 100 -40°C 100 +25°C 200 -100 -300 -400 -400 -14.5 -14 13 13.5 14 14.5 INPUT COMMON MODE VOLTAGE (V) FIGURE 23. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V 15 -500 CHANNEL-B +125°C -5.5 3.5 4 4.5 -5 -4.5 -4 3 INPUT COMMON MODE VOLTAGE (V) 5 VS = ±5V CHANNEL-B 125 120 CMRR (dB) CMRR (dB) +25°C FIGURE 24. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±5V 125 CHANNEL-A 115 110 105 100 -40 -6 130 VS = ±15V 120 0 -200 130 100 -100 -300 -15 -40°C 100 -200 -15.5 20 40 60 80 TEMPERATURE (°C) 300 +125°C 0 -500 -16 0 VS = ±5V 400 VOS (µV) VOS (µV) 200 -20 VS = ±1.5V FIGURE 22. IBIAS vs TEMPERATURE vs SUPPLY 500 300 VS = ±2.25V -25 -40 120 VS = ±15V 400 VS = ±5V -15 FIGURE 21. VOS vs TEMPERATURE 500 VS = ± 15V -10 IBIAS (nA) VOS (µV) Typical Performance Curves 120 CHANNEL-A 115 110 105 -20 0 20 40 60 80 TEMPERATURE (°C) 100 FIGURE 25. CMRR vs TEMPERATURE, VS = ±15V Submit Document Feedback 13 120 100 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 26. CMRR vs TEMPERATURE, VS = ±5V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Typical Performance Curves 120 110 100 PSRR (dB) CMRR (dB) 150 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 27. CMRR vs FREQUENCY, VS = ±15V 90 PSRR+ 80 70 60 50 VS = ±5V, ±15V 40 AV = 1 30 CL = 4pF 20 RL = 10k PSRR10 VSOURCE = 1VP-P 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 28. PSRR vs FREQUENCY, VS = ±5V AND ±15V 140 140 VS = ±15V VS = ±5V 135 PSRR (dB) PSRR (dB) 135 130 125 130 125 120 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -40 120 FIGURE 29. PSRR (DC) vs TEMPERATURE, VS = ±15V 1 -20 0 20 40 60 80 TEMPERATURE (°C) 1 VS = ±5V and ±15V 0.1 VS = ±5V and ±15V 0.1 VOL - V- (V) +25°C +25°C 0.01 -40°C 0.01 0.1 1 LOAD CURRENT (mA) -40°C 10 FIGURE 31. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT, VS = ±5V AND ±15V Submit Document Feedback 14 120 125°C 0.01 0.001 0.001 100 FIGURE 30. PSRR (DC) vs TEMPERATURE, VS = ±5V 125°C V+ - VOH (V) 10M 0.001 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 FIGURE 32. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, VS = ±5V AND ±15V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 15 5 14 4 13 +125°C 12 -40°C 10 -10 3 +125°C -12 -13 -14 0 2 4 6 VOL(V) +25°C VS = ±15V AV = 2 RF = RG = 100k VIN = ±7.5VDC +75°C 8 -40°C 1 -1 0°C -11 -15 +75°C 2 11 VOL(V) VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) VOH(V) VOH(V) Typical Performance Curves 10 12 14 16 18 20 22 -5 24 0°C -2 VS = ±5V A =2 -3 RV = R = 100k F G -4 VIN = ±2.5VDC 0 2 4 6 +25°C 8 10 FIGURE 33. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±15V VOH AND VOL (mV) VOH AND VOL (mV) VS = ±5V 90 R = 10k L 80 VOH (V+ TO VOUT) 70 60 50 40 VOL (VOUT TO V-) 30 20 22 24 50 40 30 10 10 0 20 40 60 80 TEMPERATURE (°C) 100 0 -40 120 VOH (V+ TO VOUT) 60 20 FIGURE 35. VOUT HIGH AND LOW vs TEMPERATURE, VS = ±15V, RL = 10k VOL (VOUT TO V-) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 36. VOUT HIGH AND LOW vs TEMPERATURE, VS = ±5V, RL = 10k 50 50 VS = ±15V 45 R = 10k L 40 VS = ±5V 45 R = 10k L 40 ISC-SINK 35 35 30 Isc (mA) Isc (mA) 18 70 20 25 20 15 ISC-SINK 30 25 20 15 10 10 ISC-SOURCE 5 0 -40 16 100 VS = ±15V 90 R = 10k L 80 -20 14 FIGURE 34. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±5V 100 0 -40 12 I-FORCE (mA) I-FORCE (mA) -20 0 20 40 60 5 80 100 120 TEMPERATURE (°C) FIGURE 37. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±15V Submit Document Feedback 15 0 -40 ISC-SOURCE -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 38. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±5V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 1k VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) VS = ±15V AV = 1 INPUT AND OUTPUT (V) VOUT (VP-P) Typical Performance Curves 10k 100k FREQUENCY (Hz) 1M 6 V = ±5V 5 S VIN = ±5.9V 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0 FIGURE 39. MAX OUTPUT VOLTAGE vs FREQUENCY 110 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) ISUPPLY PER AMPLIFIER (µA) FIGURE 41. AVOL vs TEMPERATURE 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 VSUPPLY (V) FIGURE 43. SUPPLY CURRENT vs SUPPLY VOLTAGE Submit Document Feedback 16 6 8 10 12 TIME (ms) 14 16 18 20 200 180 160 140 120 100 80 60 40 20 0 GAIN -20 V = ±15V -40 S -60 RL = 1MΩ -80 SIMULATION -100 0.1 1 10 100 PHASE 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G FIGURE 42. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V 70 60 RF = 10kΩ, RG = 10Ω ACL = 1001 RF = 10kΩ, RG = 100Ω 50 GAIN (dB) AVOL (dB) VS = ±5V GAIN (dB), PHASE (°) VS = ± 15V 120 4 OUTPUT FIGURE 40. NO PHASE REVERSAL 140 130 2 INPUT 40 VS = ±5V, ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 101 30 20 ACL = 10 RF = 10kΩ, RG = 1.1kΩ 10 0 ACL = 1 -10 100 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 44. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 -2 -3 RL = OPEN, 100k, 10k -4 RL = 1k -5 RL = 499 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = 100 RL = 49.9 10k 100k 1M 10M -2 -3 RL = OPEN, 100k, 10k -4 RL = 1k -5 -6 VS = ±5V -7 CL = 4pF AV = +1 -8 VOUT = 100mVp-p -9 1k 100 1 10k 100k 1M 10M 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RL = 49.9 FIGURE 46. GAIN vs FREQUENCY vs RL, VS = ±5V FIGURE 45. GAIN vs FREQUENCY vs RL, VS = ±15V -2 -3 -4 VOUT = 10mVP-P -5 VOUT = 50mVP-P VS = ±5V CL = 4pF AV = +1 RL = INF -6 -7 -8 -9100 VOUT = 100mVP-P VOUT = 500mVP-P VOUT = 1VP-P 1k 10k 100k 1M -2 -3 VS = ±2.5V -4 VS = ±5V -5 -9 100 10M VS = ±15V -6 CL = 4pF R = 10k -7 L AV = +1 -8 VOUT = 100mVP-P 1k VS = ±20V 10k FREQUENCY (Hz) 100k 1M 10M FREQUENCY (Hz) FIGURE 47. GAIN vs FREQUENCY vs OUTPUT VOLTAGE FIGURE 48. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 100 100 VS = ±15V VS = ±5V G = 10 10 ZOUT (Ω) G = 100 1 0.10 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 49. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V Submit Document Feedback 17 1 0.10 G=1 1 G = 10 10 G = 100 ZOUT (Ω) RL = 100 FREQUENCY (Hz) FREQUENCY (Hz) 0.01 RL = 499 0.01 1 G=1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 50. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 10 INPUT NOISE VOLTAGE 1 1 INPUT NOISE CURRENT 0.1 0.1 0.01 0.1 1 10 100 1k FREQUENCY (Hz) 10k 0.01 100k FIGURE 51. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±18V VS = ±5V 10 1 0.01 0.1 1 10 100 1k FREQUENCY (Hz) 0.01 100k 10k 1000 600 400 200 0 -200 -400 -600 -800 0 1 2 3 4 5 6 TIME (s) 7 8 9 160 100 80 RL_TRANSMIT = ∞ RL_RECEIVE = 10k 60 40 RL_TRANSMIT = 2k 20 0 10 200 0 -200 -400 -600 -800 0 1 2 200 3 4 5 6 TIME (s) 7 8 9 120 12 OUTPUT 80 8 40 4 RL_RECEIVE = 10k 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 55. ISL28208 CHANNEL SEPARATION vs FREQUENCY, VS = ±5V, ±15V Submit Document Feedback 18 10 20 VS = ±15V AV = 100 RL = 10k 16 VIN = 100mVP-P OVERDRIVE = 1V INPUT 160 INPUT (mV) 120 400 FIGURE 54. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V VS = ±15V CL = 4pF VTX = 1VP-P 140 600 -1000 10 VS = ±5V AV = 10k 800 0 0 20 40 60 80 100 120 TIME (µs) 140 160 180 OUTPUT (V) VS = ±18V AV = 10k 800 INPUT NOISE VOLTAGE (nV) INPUT NOISE VOLTAGE (nV) 0.1 FIGURE 52. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±5V FIGURE 53. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V CROSSTALK (dB) 1 INPUT NOISE CURRENT 0.1 1000 -1000 10 INPUT NOISE VOLTAGE INPUT NOISE CURRENT (pA/√Hz) 10 100 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V INPUT NOISE CURRENT (pA/√Hz) 100 100 0 200 FIGURE 56. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 0 -4 -80 -8 -12 -160 INPUT -200 0 20 40 60 80 100 120 TIME (µs) VS = ±15V AV = 100 RL = 10k -16 VIN = 100mVP-P OVERDRIVE = 1V -20 140 160 180 200 INPUT (mV) -10 -40 -4 0 20 40 60 80 100 120 TIME (µs) VS = ±5V AV = 100 RL = 10k -5 VIN = 50mVP-P OVERDRIVE = 1V -6 140 160 180 200 80 100 120 TIME (µs) 140 160 180 0 200 40 AV = -1 30 AV = 1 AV = 10 20 0.010 0.100 1 10 100 6 VS = ±15V AV = 1 4 R = 2k L CL = 4pF 2 AV = -1 AV = 10 20 0 -2 10 0 0.001 60 FIGURE 60. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V 40 AV = 1 40 VS = ±15V VOUT = 100mVP-P 0 0.001 VS = ±5V VOUT = 100mVP-P 30 20 10 VOUT (V) OVERSHOOT (%) 50 0 LOAD CAPACITANCE (nF) FIGURE 59. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V 60 1 50 -3 -60 10 -1 -30 -50 2 60 OUTPUT INPUT 20 0 -2 -20 3 OUTPUT FIGURE 58. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V OUTPUT (V) 0 30 0 FIGURE 57. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V INPUT 40 OVERSHOOT (%) OUTPUT -120 50 INPUT (mV) -40 6 VS = ±5V AV = 100 5 RL = 10k VIN = 50mVP-P OVERDRIVE = 1V 4 60 OUTPUT (V) INPUT (mV) 0 OUTPUT (V) Typical Performance Curves -4 0.010 0.100 1 10 LOAD CAPACITANCE (nF) FIGURE 61. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V Submit Document Feedback 19 100 -6 0 100 200 TIME (µs) 300 400 FIGURE 62. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Typical Performance Curves 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 100 VS = ±5V AV = 1 RL = 2k CL = 4pF VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 60 40 VOUT (mV) VOUT (V) 2.4 2.0 1.6 1.2 0.8 VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 20 0 -20 -40 -60 -80 0 100 200 TIME (µs) 300 400 FIGURE 63. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V Submit Document Feedback 20 -100 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 FIGURE 64. SMALL SIGNAL TRANSIENT RESPONSE VS = ±5V, ±15V FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Applications Information Functional Description The ISL28108, ISL28208, and ISL28408 are single, dual and quad, 1.2MHz, single supply rail-to-rail output amplifiers with a common mode input voltage range extending to a range of 0.5V below the V- rail. Their input stages are optimized for precision sensing of ground referenced signals in low voltage, single supply applications. The input stage has the capability of handling large input differential voltages without phase inversion making them suitable for high voltage comparator applications. Their bipolar design features high open loop gain and excellent DC input and output temperature stability. These op amps feature low quiescent current of 165µA, and a maximum temperature drift ranging from 1.1µV/°C for the ISL28208 and ISL28408 in the SOIC package to 1.4µV/°C for the ISL28208 in the TDFN package and the ISL28408 in the SOIC package (see Figures 11 through 20). All devices are fabricated in a new precision 40V complementary bipolar DI process and immune from latch-up. Operating Voltage Range The devices are designed to operate over the 3V (±1.5V) to 40V (±20V) range and are fully characterized at ±5V and ±15V. Both DC and AC performance remain virtually unchanged over the ±5V to ±15V operating voltage range. Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 10. Input Stage Performance The PNP input stage has a common mode input range extending up to 0.5V below ground at +25°C (see Figures 23 and 24). Full amplifier performance is guaranteed down to ground (V-) over the -40°C to +125°C temperature range. For common mode voltages down to -0.5V the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance and DC accuracy when amplifying low level ground referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage (max 42V) and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. V+ VINVIN+ RIN- - RIN+ + RG RF RL V- FIGURE 65. INPUT ESD DIODE CURRENT LIMITING Output Drive Capability The bipolar rail-to-rail output stage features low saturation levels that enable an output voltage swing to less than 10mV when the total output load (including feedback resistance) is held below 50µA (Figures 31 and 32). With ±15V supplies this can be achieved by using feedback resistor values >300kΩ. The low input bias and offset currents (-43nA and ±3nA +25°C max respectively) minimize DC offset errors at these high resistance values. For example, a balanced 4 resistor gain circuit (Figure 65) with 1MΩ feedback resistors (RF, RG) generates a worst case input offset error of only ±3mV. Furthermore, the low noise current reduces the added noise associated with high feedback resistance. The output stage is internally current limited. Output current limit over-temperature is shown in Figures 37 and 38. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only one amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well driving capacitive loads (Figures 60 and 61). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth, but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 30% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. These devices are immune to output phase reversal, out to 0.5V beyond the rail (VABS MAX) limit (see Figure 40). In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see Figure 65, RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. Submit Document Feedback 21 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Unused Channels ISL28108, ISL28208, ISL28408 SPICE Model If the application requires only one channel, the user must configure any unused channel to prevent it from oscillating. Unused channels can oscillate if the input and output pins are floating. This will result in higher-than-expected supply currents and possible noise injection into the channel being used. The proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input (Figure 66). Figure 67 shows the SPICE model schematic and Figure 68 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flat band noise voltage, Slew Rate, CMRR, Gain and Phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page 6. The AVOL is adjusted for 122dB with the dominant pole at 1Hz. The CMRR is set 128dB, f = 6kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. + FIGURE 66. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------RL (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application Figures 69 through 83 show the characterization vs simulation results for the Noise Voltage, Open Loop Gain Phase, Closed Loop Gain vs Frequency, Gain vs Frequency vs RL, CMRR, Large Signal 10V Step Response, Small Signal 0.05V Step and Output Voltage Swing ±15V supplies. LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. • RL = Load resistance Submit Document Feedback 22 FN6935.5 March 4, 2014 V++ DX D3 G1 + R5 13 GAIN = 0.477 12e-6 I2 6E-6 I3 6E-6 Vin- 1 9 V1 -6.74 0.1 Q7 7 DN 23 DN R2 D13 0 PNP_LATERAL 5 Q8 PNP_input CinDif 1.21e-12 Q9 D2DBREAK PNP_input 14 PNP_LATERAL 12 EOS ++ -E Vc Vmid GAIN = 1 8 IOS 3e-9 R1 5e11 2 11 V2 -6.76 R3 0 R4 15 G2 6250 6250 Vin+ 6 GAIN = 0.3 R6 1 GAIN = 0.477 Cin1 4.19e-12 V-- DX Cin2 4.19e-12 V-- Input Stage DX 0 Vmid GAIN = 261.74e-6 -6.74 V++ L1 L3 1.59E-08 1.59E-08 G5 G7 + + 18 21 GAIN = 0.6 R9 GAIN = 0.6 1e-3 R11 1e-3 19 C1 R7 2.31e-11 7.62e9 V3 Vg V++ R19 R13 3.183e3 3.183e3 G15 G9 + + GAIN = 314.15e-6 GAIN = 314.15e-6 28 Vc G13 D11 GAIN = 12.5e-3 R15 80 V5 D7 C3 DX 10e-12 C5 10e-12 D10 DX 16 V+ E2 ++ - GAIN = 1 1st Gain Stage DX G3 + - D5 D4 24 -0.4 23 26 VOUT 27 Vmid + DX GAIN = 0.6 L2 1.59E-08 GAIN = 0.6 V-- 22 FN6935.5 March 4, 2014 Mid Supply ref V G10 C4 10e-12 GAIN = 314.15e-6 GAIN = 314.15e-6 L4 R14 1.59E-08 R20 3.183e3 3.183e3 G11 + D9 GAIN = 12.5e-3 -0.4 G12 + - D12 GAIN = 12.5e-3 V-V- 2nd Gain Stage V6 25 DY G8 G16 DY G6 + - GAIN = 261.74e-6 20 C2 2.31e-11 R8 7.62e9 + - 17 R12 1e-3 + - Vmid R10 1e-3 + - G4 V4 D8 DX -6.76 C6 10e-12 E4 ++ -GAIN = 0.5 Common Mode Gain Stage with Zero E3 ++ -GAIN = 1 0 FIGURE 67. SPICE MODEL SCHEMATIC Output Stage Correction Current Sources G14 + - ISY 185e-6 GAIN = 12.5e-3 R16 80 ISL28108, ISL28208, ISL28408 + + - 1150 D14 10 + - V7 1 D1DBREAK Q6 + - Submit Document Feedback V++ I1 ISL28108, ISL28208, ISL28408 *ISL28108_208 Macromodel - covers following *products *ISL28108 *ISL28208 *ISL28408 * *Revision History: * Revision B, LaFontaine January 22 2014 * Model for Noise, supply currents, CMRR *128dB f=6kHz ,AVOL 122dB f=1Hz * SR = 0.45V/us, GBWP 1.2MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet "LICENSE STATEMENT" *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages. * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging source, *Load current reflected into the power supply *current. * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | .subckt ISL28108_208 Vin+ Vin-V+ V- VOUT * source ISL28118_218_subckt_check_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 R_R17 2 0 1150 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 12e-6 I_I2 V++ 7 DC 6E-6 I_I3 V++ 10 DC 6E-6 I_IOS 6 VIN- DC 3e-9 D_D1 7 10 DBREAK D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 6250 R_R4 V-- 11 6250 C_Cin1 V-- VIN- 4.19e-12 C_Cin2 V-- 6 4.19e-12 C_CinDif 6 VIN- 1.21E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.4779867 G_G2 V-- 14 8 11 0.4779867 V_V1 13 14 -6.74 V_V2 14 15 -6.76 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 261.748e-6 G_G4 V-- VG 14 VMID 261.748e-6 V_V3 16 VG -6.74 V_V4 VG 17 -6.76 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 7.62283e9 R_R8 V-- VG 7.62283e9 C_C1 VG V++ 2.31e-11 C_C2 V-- VG 2.31e-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 185E-6 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 0.6 G_G6 V-- 19 5 VMID 0.6 G_G7 V++ VC 19 VMID 0.6 G_G8 V-- VC 19 VMID 0.6 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 1.59159E-08 L_L2 20 V-- 1.59159E-08 L_L3 21 V++ 1.59159E-08 L_L4 22 V-- 1.59159E-08 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Stage G_G15 V++ 28 VG VMID 314.15e-6 G_G16 V-- 28 VG VMID 314.15e-6 R_R19 28 V++ 3.18319e3 R_R20 V-- 28 3.18319e3 C_C5 28 V++ 10e-12 C_C6 V-- 28 10e-12 * G_G9 V++ 23 28 VMID 314.15e-6 G_G10 V-- 23 28 VMID 314.15e-6 R_R13 23 V++ 3.18319e3 R_R14 V-- 23 3.18319e3 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28108_208 FIGURE 68. SPICE NET LIST Submit Document Feedback 24 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Characterization vs Simulation Results 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 10 0.1 1 10 100 1k 10k 100k 10 0.1 1 10 150 GAIN (dB), PHASE (°) PHASE 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 60 GAIN (dB) 30 20 ACL = 10 RF = 10kΩ, RG = 1.1kΩ 10 0 50 0 GAIN V = ±15V -50 RS = 1MΩ L SIMULATION -100 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω 50 VS = ±5V, ±15V CL = 4pF RL = 2k VOUT = 100mVP-P 40 30 20 10 ACL = 1 -10 100 100 60 VS = ±5V, ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 101 PHASE 70 RF = 10kΩ, RG = 100Ω 50 40 100k FIGURE 72. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY RF = 10kΩ, RG = 10Ω ACL = 1001 10k 200 FIGURE 71. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY 70 1k FIGURE 70. SIMULATED INPUT NOISE VOLTAGE GAIN (dB) GAIN (dB), PHASE (°) FIGURE 69. CHARACTERIZED INPUT NOISE VOLTAGE 200 180 160 140 120 100 80 60 40 20 0 GAIN -20 V = ±15V -40 S -60 RL = 1MΩ -80 SIMULATION -100 0.1 1 10 100 100 FREQUENCY (Hz) FREQUENCY (Hz) RF = 10kΩ, RG = 1.1kΩ 0 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 73. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY Submit Document Feedback 25 -10 100 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 74. SIMULATED CLOSED LOOP GAIN vs FREQUENCY FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Characterization vs Simulation Results (Continued) 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 -2 -3 -4 RL = OPEN, 100k, 10k RL = 1k -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M -2 -3 RL = OPEN, 100k, 10k -4 RL = 1k -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 CMRR (dB) CMRR (dB) 10M 50 6 2 0 0 -2 -2 -4 -4 300 400 FIGURE 79. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE 26 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VS = ±15V AV = 1 RL = 2k CL = 4pF 4 200 TIME (µs) 1 FIGURE 78. SIMULATED CMRR vs FREQUENCY VOUT (V) VOUT (V) 1M 100 0 1m 0.01 0.1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VS = ±15V AV = 1 4 R = 2k L CL = 4pF 2 Submit Document Feedback 100k VS = ±15V SIMULATION 6 100 10k 150 FIGURE 77. CHARACTERIZED CMRR vs FREQUENCY 0 RL = 49.9 FIGURE 76. SIMULATED GAIN vs FREQUENCY vs RL FIGURE 75. CHARACTERIZED GAIN vs FREQUENCY vs RL -6 RL = 100 FREQUENCY (Hz) FREQUENCY (Hz) 150 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 RL = 499 -6 0 100 200 TIME (µs) 300 400 FIGURE 80. SIMULATED LARGE SIGNAL 10V STEP RESPONSE FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Characterization vs Simulation Results (Continued) 100 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 60 VOUT (mV) 40 20 60 40 0 -20 20 0 -20 -40 -40 -60 -60 -80 -80 -100 -100 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 VOUT (mV) 80 4.0 FIGURE 81. CHARACTERIZED SMALL SIGNAL TRANSIENT RESPONSE 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 FIGURE 82. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE OUTPUT VOLTAGE SWING (V) 20 VOH = 14.93V 10 0 -10 VOL = -14.94V -20 0 0.5 1.0 TIME (m s) 1.5 2.0 FIGURE 83. SIMULATED OUTPUT VOLTAGE SWING Submit Document Feedback 27 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION March 4, 2014 FN6935.5 CHANGE Updated absolute Maximum Ratings table on page 6, by adding ISL28108 MSOP value to ESD tolerance. Updated Spice model netlisl on page 24. January 22, 2013 FN6935.4 • Added ISL28208 MSOP specifications. Moved Table of Contents to page 2. Removed “Coming Soon” from ISL28208FUZ entry in “Ordering Information” table on page 3. page 6, removed package indicators on Vos entries for ISL28208 and ISL28408; added ISL28208 MSOP entries for TCVos and deltaVos. page 7, removed package indicators on Ios entries for ISL28208 and ISL28408. page 8, removed package indicators on Vos and Ios entries for ISL28208 and ISL28408; added ISL28208 MSOP entries for TCVos, and added “ISL28108, ISL28208” to 4th and 5th rows of CMRR parameter. page 8, added ISL28208 MSOP entries for PSRR. page 10, added “+25°C” to “default” info at top of page. page 12, added “MSOP” to titles of Figures 15 and 16. October 19, 2011 FN6935.3 • On page 6, ±15V Electrical Specifications table, added the following parameters: - VOS ISL28108 SOIC, TDFN - TCVOS ISL28108 SOIC, TDFN - IOS ISL28108 SOIC, TDFN • On page 6 and 6, ±15V Electrical Specifications table, changed the following in Conditions column: - VOS: changed “ISL28208 SOIC, TDFN” to “ISL28208 SOIC, TDFN; ISL28408 SOIC” - TCVOS: changed “ISL28208 TDFN” to”ISL28208 TDFN, ISL28408 SOIC” - IOS: changed “ISL28108 SOIC, TDFN” to “ISL28108 SOIC, TDFN; ISL28408 SOIC” • On page 8, ±5V Electrical Specifications table, added the following: - VOS ISL28108 SOIC, TDFN - TCVOS ISL28108 SOIC, TDFN - IOS ISL28108 SOIC, TDFN • On page 8, ±5V Electrical Specifications table, changed the following in Conditions column: - VOS: changed “ISL28208 SOIC, TDFN” to “ISL28208 SOIC, TDFN; ISL28408 SOIC” - TCVOS: changed “ISL28208 TDFN” to”ISL28208 TDFN, ISL28408 SOIC” - IOS: changed “ISL28108 SOIC, TDFN” to “ISL28108 SOIC, TDFN; ISL28408 SOIC” • On page 10 through page 12, added the following to Typical Performance Curves: - Figures 3, 4: ISL28408 SOIC Input Offset Distribution Voltage, ±15V and ±5V - Figures 7, 8: ISL28108 SOIC ±15V VOS distribution, and ±5V VOS distribution - Figures 9, 10: ISL28108 TDFN ±15V VOS distribution, and ±5V VOS distribution - Figures 11, 12: ISL28408 SOIC TCVOS vs. number of Amplifiers ±15V and ±5V - Figures 17, 18: ISL28108 SOIC ±15V TCVOS distribution, and ±5V TCVOS distribution - Figures 19, 20: ISL28108 TDFN ±15V TCVOS distribution, and ±5V TCVOS distribution • On page 21, Applications: minor edits to re-align figures with curves • On page 22: changed heading from “Using Only One Amplifier to “Unused Channels” and edited for clarity. • On page 32: changed Package Outline Drawing L8.3x3A to L8.3x3K • On page 33: changed Package Outline Drawing M8.118 to M8.118B • On page 34: added Package Outline Drawing M14.15 • On page 1, Features: changed Low Input Offset Voltage from 230µV to (ISL28108)……150µV. Added Related Literature section with AN1658, "ISL28208SOICEVAL2Z Evaluation Board User Guide". • On page 3, Ordering Information: added ISL28208SOICEVAL2Z evaluation board. Removed "Coming Soon" from ISL28408FBZ. Corrected Package Dwg. # for TDFN package from L8.3x3A to L8.3x3K. Corrected Package Dwg. # for MSOP package from M8.118 to M8.118B. • On page 6, Absolute Maximum Ratings, changed “ESD Tolerance (ISL28208)” to “ESD Tolerance (ISL28208, ISL28408)”. Added ESD information for ISL28108 as follows: ESD Tolerance (ISL28108) Human Body Model (Tested per JESD22-A114F).....5.5kV Machine Model (Tested per JESD22-A115-C).....300V Charged Device Model (Tested per JESD22-C110D).....2kV Submit Document Feedback 28 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION October 19, 2011 FN6935.3 CHANGE • On page 6, Thermal Information, changed package temperatures from: 8 Ld SOIC Package (108, 208, Notes 4, 7), θJA = 120, θJC = 55 8 Ld TDFN Package (108, 208, Notes 5, 6), θJA = 47, θJC = 6 8 Ld MSOP Package (108, 208, Notes 4, 7), θJA = 150, θJC = 45 14 Ld SOIC Package (408, Notes 4, 7), θJA = -, θJA = To: 8 Ld SOIC Package (208, Notes 4, 7), θJA = 120, θJC = 55 and 8 Ld SOIC Package (108, Notes 4, 7), θJA = 120, θJC = 60 8 Ld TDFN Package (208, Notes 5, 6), θJA = 47, θJC = 6 and 8 Ld TDFN Package (108, Notes 5, 6), θJA = 45, θJC = 3.5 8 Ld MSOP Package (208, Notes 4, 7), θJA = 150, θJC = 50 and 8 Ld MSOP Package (108, Notes 4, 7), θJA = 165, θJC = 57 14 Ld SOIC Package (408, Notes 4, 7), θJA = 71, θJC = 37 • April 20, 2011 FN6935.2 • Added discussion of ISL28408 throughout datasheet. • On page 3 in “Ordering Information”: Added new part, “ISL28408FBZ”. Corrected part marking for ISL28208FRTZ from 208Z to 208F. Added “ISL28408” to Note 3. Under” Pin Configurations,” added ISL28408 (14 Ld SOIC) pin configuration diagram. • On page 5: in Pin Descriptions table, added column for ISL28408 14Ld SOIC. Corrected schematic for Circuit 2. • On page 6: under “Thermal Information” added "14 Ld SOIC Package (408, Notes 4, 7)" and added ISL28108 to 8 Ld TDFN and 8 Ld MSOP. Changed θJA and θJC for 8 Ld TDFN Package from 48 and 5.5 to 47 and 6. Added Note 6 regarding θJC “case temp” measurement, and applied it to 8 Ld TDFN Package. • On page 6: in Electrical Specifications table, changed TYP spec for TCIB from 70 pA/° C to 0.07nA/° C. On page 8, changed TYP spec for TCIB from -67 pA/° C to -0.067nA/° C. These are not spec changes since the values are the same. • On page 14, Figs. 31 and 32: changed y axis units label from (mV) to (V); changed x axis units label from (µA) to (mA). • On page 21, under “Output Drive Capability,” para 2, changed "The output stage can swing at moderate levels of output current (Figures 21 and 22) and the output stage is internally current limited. Output current limit over-termperature..." to "The output stage is internally current limited. Output current limit over-temperature..." March 11, 2011 FN6935.1 • On page 1, in the first paragraph - added the following after V-rail: "a rail-to-rail differential input voltage range for use as a comparator,…" • On page 1 in “Features: - Added bullet - “Rail-to-rail input differential voltage range for comparator applications” - Changed Low Noise Current from "100fA/sq.root Hz" to "80fA/sq.root Hz" • On page 3 in “Ordering Information” - Removed "coming soon" from ISL28208FRTZ part since it is releasing. • On page 6, changed “ESD Tolerance (ISL28208, ISL28408)” as follows: - Human Body Model changed from "3kV" to "6kV" - Machine Model changed from "300V" to "400V" - Added JEDEC Test information for all ESD ratings • On page 6 and page 8, added test conditions for SOIC TCVos specs. Added TCVos specs for TDFN. • On page 7 changed “Noise Current Density” Typical from "100" to "80" • On page 21, updated Applications Information Functional Description • On page 21 Updated Input Stage Performance Section • On page 21 Updated Output Drive Capability Section • On page 22 Added ISL28108 AND ISL28208 SPICE MODEL and License Agreement section • On page 23 Added SPICE NET LIST • On page 25 Added Characterization vs Simulation Results curves February 16, 2011 FN6935.0 Initial Release Submit Document Feedback 29 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 30 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Package Outline Drawing, M8.15E M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 31 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Package Outline Drawing, L8.3x3K L8.3x3K 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 9/11 2X 1.95 3.00 6X 0.65 A B 1 PIN #1 INDEX AREA 3.00 6 6 PIN 1 INDEX AREA (4X) 1.50 ±0.10 0.15 8 TOP VIEW 8X 0.25 ±0.05 0.40 ± 0.05 4 0.10 M C A B 2.30 ±0.10 BOTTOM VIEW SEE DETAIL "X" C 0.10 C 0.75 ±0.05 0 . 203 REF 5 C 0 . 02 NOM. 0 . 05 MAX. 0.08 C SIDE VIEW DETAIL "X" ( 2.30) ( 1.95) NOTES: ( 8X 0.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured (1.50) ( 2.90 ) between 0.15mm and 0.20mm from the terminal tip. PIN 1 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. (6x 0.65) ( 8 X 0.25) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 32 FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Package Outline Drawing, M8.118B M8.118B 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 3/12 3.0±0.10mm 5 A D 8 4.9±0.20mm DETAIL "X" 3.0±0.10mm 5 1.10 MAX 0.15±0.05mm PIN# 1 ID SIDE VIEW 2 1 2 B 0.65mm BSC TOP VIEW 0.95 REF 0.86±0.05mm H GAUGE PLANE C 0.25 SEATING PLANE 0.23 - 0.36mm 0.08 M C A-B D 0.10 ± 0.05mm 3°±3° 0.10 C 0.53 ± 0.10mm SIDE VIEW 1 DETAIL "X" (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 33 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. FN6935.5 March 4, 2014 ISL28108, ISL28208, ISL28408 Package Outline Drawing, M14.15 M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 8.65 A 3 4 0.10 C A-B 2X 6 14 DETAIL"A" 8 0.22±0.03 D 6.0 3.9 4 0.10 C D 2X 0.20 C 2X 7 PIN NO.1 ID MARK 5 0.31-0.51 B 3 (0.35) x 45° 4° ± 4° 6 0.25 M C A-B D TOP VIEW 0.10 C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.10-0.25 1.27 SIDE VIEW (1.27) DETAIL "A" (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. (1.50) 6. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 34 FN6935.5 March 4, 2014