IDTQS3389 LAST VALUE LATCH 20 ACTIVE TERMINATORS (BUS HOLD) COMMERCIAL TEMPERATURE RANGE QUICKSWITCH® PRODUCTS LAST VALUE LATCH 20 ACTIVE BUS TERMINATORS (BUS HOLD) FEATURES: • • • • • DESCRIPTION: Active termination pulls bus pins to rails Holds last value of input signal Ideal replacement for resistive termination µ A DC quiescent current Ultra low 3µ Bus-hold eliminates floating bus lines and reduces static power consumption Low power QCMOS technology Operates over 2.7V to 5.5V Vcc range TTL-compatible input and output levels No added noise or ground bounce 20 independent terminator circuits Available in QSOP package • • • • • • IDTQS3389 The QS3389 provides a set of 20 active termination circuits which pull data bus signals to the voltage rails. This feature prevents bus signals from floating in the threshold region of standard TTL I/O devices. The QS3389 can replace resistor termination solutions which add DC power dissipation and increase component count. Input clamp diodes help to reduce reflections and undershoot in transmission line environments. Importantly, the terminator circuits pull signals to whichever logic state the signal previously held (high or low). For this reason, this device is also referred to as a last value latch. This device is appropriate for data bus applications where interfacing devices have CMOS inputs with low input currents. These terminators provide sufficient drive to overcome leakage currents and drive corresponding signals away from the TTL threshold region. The QS3389 is characterized for operation at 0°C to +70°C. APPLICATIONS: • Bus termination • Extend data hold time FUNCTIONAL BLOCK DIAGRAM T0 7K Ω T 19 7K Ω The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE DECEMBER 1999 1 c 1999 Integrated Device Technology, Inc. DSC-5733/1 IDTQS3389 LAST VALUE LATCH 20 ACTIVE TERMINATORS (BUS HOLD) COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit Supply Voltage to Ground –0.5 to +7 V VCC 1 24 VCC VTERM(3) DC Switch Voltage VS –0.5 to +7 V T0 2 23 T10 VAC AC Input Voltage (pulse width ≤20ns) –3 V T1 3 22 T11 IOUT DC Output Current 120 mA T12 Maximum Power Dissipation (TA = 85°C) 4 21 PMAX T2 TSTG Storage Temperature T3 5 20 T13 T4 6 19 T14 T5 7 18 T15 T6 8 17 T16 T7 9 16 T17 T8 10 15 T18 T9 11 14 T19 GND 12 13 GND 0.5 W –65 to +150 °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC . CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V, VOUT = 0V) QSOP TOP VIEW Pins Typ. Max. (1) Unit T19 - T0 3 4 pF NOTE: 1. This parameter is guaranteed but not production tested. 2 IDTQS3389 LAST VALUE LATCH 20 ACTIVE TERMINATORS (BUS HOLD) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5V ± 5% Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit VIH Input HIGH Voltage Guaranteed Logic HIGH for Control Pins 2 — — V VIL Input LOW Voltage Guaranteed Logic LOW for Control Pins — — 0.8 V VT Threshold Voltage — 1.5 — V IIN Input Leakage Current (2) VIN = Vcc or GND — — ±5 µA IBH Input Current (5) Vcc = Max., VIN = 0V or Vcc — — ±20 µA Vcc = Max., 0.8V < VIN < 2V — — ±500(4) Input HIGH or LOW Bus Hold Inputs (2,3) IBHH Bus Hold Sustaining Current (6,7) Vcc = Min., VIN = 2V –60 — — µA IBHL Bus Hold Inputs Vcc = Min., VIN = 0.8V +60 — — µA RT Terminator Resistance — 7k — Ω NOTES: 1. Typical values are at VCC = 5.0V, TA = 25°C. 2. Trip current definition (see Functional Block Diagram): An external driver must source at least ITL to switch the node from LOW to HIGH. An external driver must sink at least ITH to switch the node from HIGH to LOW. 3. Hold current definition (see Functional Block Diagram): IHH is the Maximum Curent the QS3389 can sink without raising the node above VIL max. IHL is the Maximum Curent the QS3389 can source without lowering the node below VIH min. 4. An external driver must provide at least IBH during transition to guarantee that the Bus-Hold input will change states. 5. IBH is the magnitude of the input current specified under two conditions: a) Input voltage at GND or Vcc. This indicates the input current under steady-state condition. b) Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The driver connected to the input must overcome this current requirement in order to switch the logic state of the bus-hold circuit. 6. IBHL is the minimum sustaining “sink” current at the input for VIN = 0.8V. This parameter signifies the latching capability of the bus-hold circuit in logic LOW state. 7. IBHH is the minimum sustaining “source” current at the input for VIN = 2V. This parameter signifies the latching capability of the bus-hold circuit in logic HIGH state. POWER SUPPLY CHARACTERISTICS Symbol ICCQ Parameter Quiescent Power Supply Current Test Conditions(1) VCC = Max., VIN = GND or VCC, f = 0 NOTE: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 3 Max. Unit 1.5 mA IDTQS3389 LAST VALUE LATCH 20 ACTIVE TERMINATORS (BUS HOLD) COMMERCIAL TEMPERATURE RANGE ACTIVE TERMINATOR OR ‘BUS-HOLD’ CIRCUIT The Active Terminator circuit, also known as the Bus-hold circuit, is configured as a “weak latch” with positive feedback. When connected to a TTL or CMOS input port, the Bus-hold circuit holds the last logic state at the input when the input is “disconnected” from the driver. When the output of a device connected to such an input attempts a logic level transition, it will over-drive the Bus-hold circuit. The primary benefit of this circuit is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to VCC or GND to prevent bus floating, because the Bus-hold circuit does not consume any static power. V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT IBH +500 Sinking Current (+) IBHL +60 +20 IBH +60 IBHL Voltage VT +20 IBH – 20 IBH – 20 IBHH Sourcing Current (–) IBH – 60 IBHH – 60 – 500 VIL Vcc VIH 0.8V 2V VT ≡ Threshold Voltage ≈ 1.5V VIL ≈ .8 VIH ≈ 2V The figure above shows the input V-I characteristics of a Bus-hold implementation. The input characteristics resemble a resistor. As the input voltage is increased from 0 volts, the ‘sink’ current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the latch changes the logic state due to positive feedback and the direction of current is reversed. As the voltage is further increased towards V CC, the input ‘source’ current begins to decrease, reaching the lowest level at VIN = VCC. 4 IDTQS3389 LAST VALUE LATCH 20 ACTIVE TERMINATORS (BUS HOLD) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDTQS XXXXX Device Type XX Package X Process Blank Commercial (0°C to +70°C) Q Quarter Size Outline Package 3389 Last Value Latch 20 Active Terminators (Bus Hold) CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 5 for Tech Support: [email protected] (408) 654-6459