ISL59117 ® Data Sheet September 21, 2006 FN6278.0 Triple Channel Video Driver with LPF Features The ISL59117 is a triple channel reconstruction filter with a -3dB roll-off frequency of 9MHz. Operating from single supplies ranging from +2.5V to +3.6V and drawing only 3.9mA quiescent current, the ISL59117 is ideally suited for low power, battery-operated applications. Additionally, enable pins shut the part down in under 14ns. • 3rd order 9MHz reconstruction filter The ISL59117 is designed to meet the needs for very low power and bandwidth required in battery-operated communication, instrumentation, and modern industrial applications such as video on demand, cable set-top boxes, MP3 players, and HDTV. The ISL59117 is offered in a space-saving chipscale package guaranteed to a 0.57mm maximum height constraint and specified for operation from -40°C to +85°C temperature range. • Rail-to-rail output Pinout • Communications devices 2 • Low supply current = 3.9mA • Power-down current less than 1µA • Supplies from 2.5V to 3.6V • CSP package • Pb-free plus anneal available (RoHS compliant) Applications • Video amplifiers • Portable and handheld products • Video on demand ISL59117 (WLCSP) TOP VIEW 1 • 40V/µs slew rate • Cable set-top boxes • Satellite set-top boxes 3 • MP3 players A • HDTV CIN GND • Personal video recorder COUT Block Diagram B CVBSIN EN CVBSOUT + 9MHz 65mV - + x2 YOUT 9MHz 65mV - + x2 COUT 9MHz 65mV - + x2 CVBSOUT C YIN YIN VDD 5µA YOUT 500mV CIN + CVBSIN 5µA EN BIASING & CONTROL Ordering Information PART NUMBER (Note) ISL59117IIZ-T7 PART MARKING 117Z TAPE AND REEL TEMP. RANGE (°C) 7” -40 to +85 PACKAGE (Pb-Free) WLCSP PKG. DWG. # W3x3.9A NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59117 Absolute Maximum Ratings (TA = +25°C) ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage from VDD to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VDD +0.3V to GND -0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VDD = 3.3V, TA = +25°C, RL = 150Ω to GND, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 3.6 V INPUT CHARACTERISTICS VDD Supply Voltage Range 2.5 IDD Quiescent Supply Current VIN = 500mV, EN = VDD, no load 3.9 6.5 mA IDD_OFF Shutdown Supply Current EN = 0V 0.1 0.5 µA VY_CLAMP Y Input Clamp Voltage IY = -100µA -30 -15 10 mV IY_DOWN Y Input Clamp Discharge Current VY = 0.5V 3 5 7 µA IY_UP Y Input Clamp Charge Current VY = -0.1V -3.4 -2.5 mA RY Y Input Resistance 0.5V < VY < 1V 10 VCVBS_CLAMP CVBS Input Clamp Voltage IY = -100µA -30 -15 10 mV ICVBS_DOWN CVBS Input Clamp Discharge current VCVBS = 0.5V 3 5 7 µA ICVBS_UP CVBS Input Clamp Charge current VCVBS = -0.1V -3.4 -2.5 mA RCVBS CVBS Input Resistance 0.5V < VCVBS < 1V 10 VC_CLAMP C Input Clamp Voltage VY = 0.05V, IC = 0A 500 550 700 mV RC C Input Resistance VY = 0.05V, 0.25V < VC < 0.75V 2.0 2.6 3.0 kΩ IC C Input Bias Current VY = 0.3V VY_SYNC Y Input Sync Detect Voltage VOLS Output Level Shift Voltage VIN = 0V, no load AV Voltage Gain RL = 150Ω ∆AV_CY MΩ MΩ 10 pA 100 150 200 mV 60 140 200 mV 1.95 1.99 2.04 V/V C-Y Channel Gain Mismatch -1.75 ±0.5 1.75 % ∆AV_CVBS C/Y-CVBS Channel Gain Mismatch -2.0 ±0.5 2.0 % PSRR DC Power Supply Rejection VDD = 2.5V to 3.6V VOH Output Voltage High Swing VIN = 2V, RL = 150Ω to GND ISC Output Short-Circuit Current IENABLE Enable Input Current VIL Disable Threshold VIH Enable Threshold ROUT Shutdown Output Impedance 60 dB 2.85 3.2 V VIN = 2V, to GND through 10Ω 100 145 mA 0V < VEN < 3.3V -0.2 0 µA 0.8 V 2.0 EN = 0V DC EN = 0V, f = 4.5MHz 2 +0.2 5 V 7 3.4 8 kΩ kΩ FN6278.0 September 21, 2006 ISL59117 Electrical Specifications PARAMETER VDD = 3.3V, TA = +25°C, RL = 150Ω to GND, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW0.1dB ±0.1dB Bandwidth RL = 150Ω, CL = 5pF 5 MHz BW3dB -3dB Bandwidth RL = 150Ω, CL = 5pF 9 MHz Normalized Stopband Gain f = 27MHz -24.2 dB dG Differential Gain NTSC and PAL 0.10 % dP Differential Phase NTSC and PAL 0.5 ° D/DT Group Delay Variation f = 100kHz, 5MHz 5.4 ns SNR Signal To Noise Ratio 100% white signal 65 dB TON Enable Time VIN = 500mV, VOUT to 1% 200 ns TOFF Disable Time VIN = 500mV, VOUT to 1% 14 ns +SR Positive Slew Rate 20% to 80%, VIN = 1V step 30 40 60 V/µs -SR Negative Slew Rate 80% to 20%, VIN = 1V step -30 -40 -60 V/µs tF Fall Time 2.5VSTEP, 80% - 20% 25 ns tR Rise Time 2.5VSTEP, 20% - 80% 22 ns Connection Diagram 3.3V 0.1µF V DD + S-VIDEO CABLE 65mV YIN Y (LUMINANCE) 9MHz - + YOUT YOUT x2 0.1µF 75 5µA 75 500mV 65mV CIN C (CHROMINANCE) 9MHz - + COUT COUT x2 0.1µF 75 75 + 65mV CVBSIN CVBS (COMPOSITE) 9MHz 0.1µF 5µA BIASING & µC OR TIE TO 3.3V EN 3 - + CVBSOUT CVBSOUT x2 75 75 CONTROL FN6278.0 September 21, 2006 ISL59117 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION A1 CIN A2 GND Ground A3 COUT Chrominance output B1 CVBSIN B2 EN B3 CVBSOUT C1 YIN Luminance Input C2 VDD Positive power supply C3 YOUT Chrominance input Composite Video input Enable Composite Video output Luminance output Typical Performance Curves 5 3 5 0 VDD = +3.3V RL = 150Ω 2 1 -0.1dB BW @ 3.8MHz 0 -1 -2 -3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 1M 10M FREQUENCY (Hz) 100M FIGURE 1. GAIN vs FREQUENCY -0.1dB 5 3 CL = 27pF 0 -4 -5 100k -30 3.0 CL = 10pF -1 -3 -25 3.5 2 -2 -20 4.0 VDD = +3.3V RL = 150Ω 1 40M 10M 1.5 1.0 0.5 0.0 100M FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD VDD = +3.3V RL = 150Ω FIN = 100kHz 2.0 CL = 1000pF 4 1M FREQUENCY (Hz) 2.5 CL = 470pF 1M 10M FREQUENCY (Hz) -3dB BW @ 9MHz -30dB BW @ 27MHz -15 FIGURE 2. GAIN vs FREQUENCY -3dB POINT VOUT (VP-P) NORMALIZED GAIN (dB) 4 -5 -10 -35 -40 100k -4 -5 100k VDD = +3.3V RL = 150Ω 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VIN (VP-P) FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT MAGNITUDE FN6278.0 September 21, 2006 ISL59117 Typical Performance Curves (Continued) 270 180 -20 VDD = +3.3V RL = 150Ω VDD = +3.3V -30 -40 PSRR (dB) PHASE (°) 90 0 -90 -50 -60 -70 -80 -180 -270 -90 100k 1M 10M FREQUENCY (Hz) -100 100k 100M FIGURE 5. PHASE vs FREQUENCY 1M 10M FREQUENCY (Hz) 100M FIGURE 6. PSRR vs FREQUENCY -40 VDD = +3.3V -50 YIN to COUT PSRR (dB) -60 -70 -80 -90 CIN to YOUT -100 -110 100k 1M 10M 50M FREQUENCY (Hz) FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 8. ISOLATION vs FREQUENCY 8 VDD = +3.3V FIN = 1MHz SUPPLY CURRENT (mA) 7 NO LOAD NO INPUT 6 5 4 3 2 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE 5 FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE FN6278.0 September 21, 2006 ISL59117 Typical Performance Curves (Continued) 2.2 0.4 AMPLITUDE (V) 1.7 AMPLITUDE (V) 0.5 VDD = +3.3V RL = 150Ω VOUT = 1VP-P 1.2 TRISE = 10.46ns 0.7 TFALL = 26.81ns 0.2 -0.3 -100 0 100 200 300 TIME (ns) 400 0.2 500 AMPLITUDE (V) ENABLE SIGNAL 0.5 0.0 -0.5 0 50 TIME (ns) 100 150 200 1.0 0.5 OUTPUT SIGNAL 0.0 -10 -30 HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) 600 THD -40 2nd THD -50 3rd THD -60 -70 4M 5M 6M 7M FREQUENCY (Hz) 8M 9M 10M FIGURE 15. HARMONIC DISTORTION vs FREQUENCY 6 0 10 TIME (ns) 20 30 FIGURE 14. DISABLE TIME VDD = +3.3V RL = 150Ω VOUT = 2VP-P 3M 500 1.5 FIGURE 13. ENABLE TIME 2M 400 DISABLE SIGNAL -0.5 VDD = +3.3V RL = 150Ω -1.0 -20 -10 OUTPUT SIGNAL -80 1M 200 300 TIME (ns) 2.0 1.0 -20 100 2.5 1.5 -10 0 FIGURE 12. SMALL SIGNAL STEP RESPONSE VDD = +3.3V 2.0 RL = 150Ω AMPLITUDE (V) TFALL = 27.92ns 0 -100 600 2.5 -50 TRISE = 27.85ns 0.1 FIGURE 11. LARGE SIGNAL STEP RESPONSE -1.0 -100 VDD = +3.3V RL = 150Ω VOUT = 200mVP-P 0.3 -20 VDD = +3.3V RL = 150Ω FIN = 500kHz -30 -40 THD -50 3rd THD 2nd THD -60 -70 -80 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOUT (VP-P) FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE FN6278.0 September 21, 2006 ISL59117 Typical Performance Curves (Continued) 16 -3dB BANDWIDTH (MHz) VDD = +3.3V RL = 150Ω VDD = +3.3V RL = 150Ω 14 12 10 8 6 4 2 20 FIGURE 17. GROUP DELAY vs FREQUENCY 45 POSITIVE SLEW RATE SLEW RATE (V/µs) 180 260 340 INPUT RESISTANCE (Ω) 420 500 FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE 50 40 100 VOUT = 2VP-P RL = 150Ω NEGATIVE SLEW RATE 35 30 25 20 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V) 4.0 FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE NOISE FLOOR ( nV/ Hz ) 100 10 2 4 10kHz 6 8 1 100kHz 2 4 6 8 1 1MHz 2 4 4.2MHz FREQUENCY (Hz) FIGURE 20. UNWEIGHTED NOISE FLOOR 7 FN6278.0 September 21, 2006 ISL59117 Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 0.9 POWER DISSIPATION (W) POWER DISSIPATION (W) 1 0.8 0.7 0.6 0.5 462mW WLCSP (3x3 BUMP) 0.4 θJA=216°C/W 0.3 0.2 0.1 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 952mW 1 WLCSP (3x3 BUMP) 0.8 θJA=105°C/W 0.6 0.4 0.2 0 0 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Application Information The Sallen Key Low Pass Filter The ISL59117 is a single-supply rail-to-rail triple (one s-video channel and one composite channel) video amplifier with internal sync tip clamps, a typical -3dB bandwidth of 9MHz and slew rate of about 40V/µs. This part is ideally suited for applications requiring high composite and s-video performance with very low power consumption. As the performance characteristics and features illustrate, the ISL59117 is optimized for portable video applications. The Sallen Key is a classic low pass configuration. This provides a very stable low pass function, and in the case of the ISL59117, a three-pole roll-off at 9MHz. The three-pole function is accomplished with an RC low pass network placed in series with and before the Sallen Key. The first pole is formed by an RC network, with poles two and three generated with a Sallen Key, creating a nice three-pole roll-off at 9MHz. Internal Sync Clamp The ISL59117 can be AC or DC coupled to its output. When AC coupling, a 220µF coupling capacitor is recommended to ensure that low frequencies are passed, preventing video “tilt” or “droop” across a line. Embedded video DACs typically use ground as their most negative supply. This places the sync tip voltage at a minimum of 0V. Presenting a 0V input to most single supply amplifiers will saturate the output stage of the amplifier resulting in a clipped sync tip and degraded video image. The ISL59117 features an internal sync clamp and offset function that level shifts the entire video signal to the optimum level before it reaches the amplifiers’ input stage. These features also help avoid saturation of the output stage of the amplifier by setting the signal closer to the best voltage range. The simplified block diagram on the front page shows the basic operation of the ISL59117’s sync clamp. The Y and CVBS inputs’ AC-coupled video sync signal is pulled negative by a current source at the input. When the sync tip goes below the comparator threshold, the comparator output goes high, pulling up on the input through the diode, forcing current into the coupling capacitor until the voltage at the input is again 0V, and the comparator turns off. This forces the sync tip clamp to always be 0V, setting the offset for the entire video signal. The C channel is slaved to the Y channel and clamped to a 500mV level. 8 Output Coupling The ISL59117’s internal sync clamp makes it possible to DC couple the output to a video load, eliminating the need for any AC coupling capacitors, saving board space, cost, and eliminating any “tilt” or offset shift in the output signal. The trade off is larger supply current draw, since the DC component of the signal is now dissipated in the load resistor. Typical load current for AC coupled signals is 5mA compared to 10mA for DC coupling. Output Drive Capability The ISL59117 does not have internal short circuit protection circuitry. If the output is shorted indefinitely, the power dissipation could easily overheat the die or the current could eventually compromise metal integrity. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnect. Note that for transient short circuits, the part is robust. Short circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. In video applications this would be a 75Ω resistor and will provide adequate short circuit protection to the device. Care should still be taken not to stress the device with a short at the output. FN6278.0 September 21, 2006 ISL59117 Power Dissipation With the high output drive capability of the ISL59117, it is possible to exceed the +125°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------Θ JA Where: TJMAX = Maximum junction temperature Power Supply Bypassing Printed Circuit Board Layout As with any modern operational amplifier, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. Printed Circuit Board Layout For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. TAMAX = Maximum ambient temperature ΘJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing: V OUT PD MAX = V S × I SMAX + ( V S – V OUT ) × ---------------R L for sinking: PD MAX = V S × I SMAX + ( V OUT – V S ) × I LOAD Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current 9 FN6278.0 September 21, 2006 ISL59117 Wafer Level Chip Scale Package (WLCSP) W3x3.9A 3x3 ARRAY 9 BALL WAFER LEVEL CHIP SCALE PACKAGE (For ISL59116, ISL59117 Only) E SYMBOL MILLIMETERS NOTES A 0.62 +0.05 -0.08 - A1 0.24 ±0.025 - A2 0.38 REF. - b 0.32 ±0.03 - bb θ 0.30 REF. - D 1.45 ±0.05 - D1 1.00 BASIC - E 1.45 ±0.05 - E1 1.00 BASIC - PIN A1 ID AREA D TOP VIEW bb A2 A A1 b e 0.50 BASIC - SD 0.00 BASIC - N 9 3 Rev. 1 6/06 SIDE VIEW NOTES: 1. Dimensions are in Millimeters. E1 2. Dimensioning and tolerancing conform to ASME 14.5M-1994. 3. Symbol “N” is the actual number of solder balls. C 4. Reference JEDEC MO-211-C, variation DD. SD D1 B A 1 2 3 b BOTTOM VIEW All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6278.0 September 21, 2006