DATASHEET

X9241A
Quad Digital Controlled Potentionmeters (XDCP™)
Data Sheet
August 17, 2015
FN8164.7
Non-Volatile/Low Power/2-Wire/64 Taps
Features
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
• Four potentiometers in one package
• 2-wire serial interface
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Register oriented format
- Direct read/write/transfer of wiper positions
- Store as many as four positions per potentiometer
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
• Low power CMOS
• High Reliability
- Endurance–100,000 data changes per bit per register
- Register data retention–100 years
• 16-bytes of nonvolatile memory
• 3 resistor array values
- 2k10k50kor combination
- Cascadable for values of 4kto 200k
• Resolution: 64 taps each pot
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages
• Pb-free available (RoHS compliant)
Block Diagram
VCC
VSS
R0 R1
R2 R3
VH0/RH0
WIPER
COUNTER
REGISTER
(WCR)
VL0/RL0
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 2
VW0/RW0
VH2/
RH2
VL2/RL2
VW2/RW2
SCL
SDA
A0
A1
INTERFACE
AND
CONTROL
CIRCUITRY
8
A2
A3
DATA
VH1/RH1
R0 R1
R2 R3
1
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 1
VL1/RL1
VW1/RW1
VH3/RH3
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 3
VL3/RL3
VW3/RW3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2006, 2007, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9241A
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(k)
TEMP RANGE
(°C)
5 ±10%
2/10/50
0 to +70
20 Ld PDIP***
-40 to +85
20 Ld PDIP***
PACKAGE
(RoHS Compliant)
X9241AMPZ (Note)
(No longer available,
recommended
replacement:
X9241AMSZT1)
X9241AMPZ
X9241AMPIZ (Note)
(No longer available,
recommended
replacement:
X9241AMSZT1)
X9241AMPIZ
X9241AMSZ* (Note)
X9241AMS Z
0 to +70
20 Ld SOIC
X9241AMSIZ* (Note)
X9241AMSI Z
-40 to +85
20 Ld SOIC
X9241AMVZ (Note)
X9241AM VZ
0 to +70
20 Ld TSSOP
X9241AMVIZ* (Note)
X9241AM VIZ
-40 to +85
20 Ld TSSOP
Pot 0 = 2k
Pot 1 = 10k
Pot 2 = 10k
Pot 3 = 50k
X9241AWPIZ (Note)
X9241AWPIZ
X9241AWSZ* (Note)
X9241AWS Z
X9241AWSIZ* (Note)
X9241AWSI Z
X9241AWVZ* (Note)
X9241AW VZ
X9241AWVIZ* (Note)
X9241AW VIZ
X9241AYPZ (Note)
(No longer available,
recommended
replacement: X9241AYSIZ)
X9241AYPZ
X9241AYSZ* (Note)
X9241AYS Z
X9241AYSIZ* (Note)
X9241AYSI Z
X9241AYVZ (Note)
(No longer available,
recommended
replacement: X9241AYVIZ)
X9241AY VZ
0 to +70
20 Ld PDIP
Pot 0 = 10k
0 to +70
20 Ld SOIC
Pot 1 = 10k
-40 to +85
20 Ld SOIC
10
Pot 2 = 10k
Pot 3 = 10k
2
0 to +70
20 Ld TSSOP
-40 to +85
20 Ld TSSOP
0 to +70
20 Ld PDIP***
0 to +70
20 Ld SOIC
-40 to +85
20 Ld SOIC
Pot 0 = 2k
Pot 1 = 2k
X9241AYVIZ* (Note)
X9241AY VIZ
X9241AUPZ (Note)
X9241AUPZ
X9241AUPIZ (Note)
Pot 2 = 2k
Pot 3 = 2k
0 to +70
20 Ld TSSOP
-40 to +85
20 Ld TSSOP
50
0 to +70
20 Ld PDIP***
X9241AUPIZ
Pot 0 = 50k
-40 to +85
20 Ld PDIP***
X9241AUSZ* (Note)
X9241AUS Z
Pot 1 = 50k
0 to +70
20 Ld SOIC
X9241AUSIZ* (Note)
X9241AUSI Z
Pot 2 = 50k
-40 to +85
20 Ld SOIC
X9241AUVZ* (Note)
(No longer available,
recommended
replacement:
X9241AUSZT1)
X9241AU VZ
X9241AUVIZ* (Note)
X9241AU VIZ
5 ±10%
Pot 3 = 50k
0 to +70
20 Ld TSSOP
-40 to +85
20 Ld TSSOP
*Add "T1" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2
FN8164.7
August 17, 2015
X9241A
Pin Descriptions
Pin Names
Host Interface Pins
SYMBOL
DESCRIPTION
Serial Clock (SCL)
VH0/RH0 to VH3/RH3,
VL0/RL0 to VL3/RL3
Potentiometer Pins (terminal equivalent)
The SCL input is used to clock data into and out of the
X9241A.
VW0/RW0 to VW3/RW3 Potentiometer Pins (wiper equivalent)
Serial Data (SDA)
Principles of Operation
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wireORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.
The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Address
The Address inputs are used to set the least significant
4-bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9241A.
Potentiometer Pins
VH/RH(VH0/RH0 TO VH3/RH3), VL/RL (VL0/RL0 TO VL3/RL3)
Serial Interface
The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9241A will be
considered a slave device in all applications.
Clock and Data Conventions
The RH and RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
Data states on the SDA line can change only during SCL
LOW periods (tLOW). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
VW/RW (VW0/RW0 TO VW3/RW3)
Start Condition
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Pinout
X9241A
(20 LD DIP, SOIC, TSSOP)
TOP VIEW
Stop Condition
VW0/RW0
1
20
VL0/RL0
2
19
VW3/RW3
VH0/RH0
3
18
VL3/RL3
A0
4
17
VH3/RH3
A2
5
16
A1
VW1/RW1
6
15
A3
VL1/RL1
7
14
SCL
VH1/RH1
8
13
VW2/RW2
SDA
9
12
VL2/RL2
VSS
10
11
VH2/RH2
X9241A
VCC
Pin Names
SYMBOL
SCL
SDA
A0 to A3
DESCRIPTION
Serial Clock
Serial Data
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (tHIGH). The X9241A continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8-bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8-bits of data. See Figure 7.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9241A will
respond with a final acknowledge.
Address
3
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X9241A
Array Description
Flow 1. ACK Polling Sequence
The X9241A is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (VH/RH
and VL/RL inputs).
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (VW/RW)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 6 least significant bits of
the WCR are decoded to select, and enable, 1 of 64
switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ACK
RETURNED?
ISSUE STOP
NO
YES
NO
FURTHER
OPERATION?
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
4-bits of the slave address are the device type identifier
(refer to Figure 1). For the X9241A, this is fixed as 0101[B].
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
DEVICE TYPE
IDENTIFIER
0
1
0
1
A3
A2
A1
A0
Instruction Structure
DEVICE ADDRESS
FIGURE 1. SLAVE ADDRESS
The next 4-bits of the slave address are the device address.
The physical device address is defined by the state of the A0
to A3 inputs. The X9241A compares the serial data stream
with the address input state; a successful compare of all 4
address bits is required for the X9241A to respond with an
acknowledge.
The next byte sent to the X9241A contains the instruction
and register pointer information. The 4 most significant bits
are the instruction. The next 4-bits point to one of four pots
and when applicable they point to one of four associated
registers. The format is in Figure 2.
POTENTIOMETER
SELECT
I3
I2
I1
I0
P1
P0
R1
R0
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command,
the X9241A initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241A is still busy with the write operation, no ACK will be
returned. If the X9241A has completed the write operation,
an ACK will be returned and the master can then proceed
with the next operation.
4
INSTRUCTIONS
REGISTER
SELECT
FIGURE 2. INSTRUCTION BYTE FORMAT
The 4 high order bits define the instruction. The next 2-bits
(P1 and P0) select which one of the four potentiometers is to
be affected by the instruction. The last 2-bits (R1 and R0)
select one of the four registers that are to be acted upon
when a register oriented instruction is issued.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 3.
These two-byte instructions exchange data between the WCR
and one of the data registers. A transfer from a Data Register
to a WCR is essentially a write to a static RAM. The response
FN8164.7
August 17, 2015
X9241A
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.
of the wiper to this action will be delayed tSTPWV. A transfer
from WCR current wiper position to a Data Register is a write
to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it may
occur globally, wherein the transfer occurs between all four of
the potentiometers and one of their associated registers.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
VH/RH terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed illustration
of the sequence and timing for this operation is shown in
Figures 5 and 6 respectively.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1
P0
R1
A
C
K
R0
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1 P0
R1 R0
A
C
K
CM DW D5 D4
D3
D2
D1 D0
A
C
K
S
T
O
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1
P0
X
X
R1
R0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
5
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X9241A
INC/DEC
CMD
ISSUED
tCLWV
SCL
SDA
VOLTAGE OUT
VW/RW
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 1. INSTRUCTION SET
INSTRUCTION FORMAT
INSTRUCTION
I3
I2
I1
I0
R1
R0
OPERATION
Read WCR
1
0
0
1
X
X
Read the contents of the Wiper Counter Register pointed to by P1 to P0
Write WCR
1
0
1
1/0
X
X
Write new value to the Wiper Counter Register pointed to by P1 to P0
Read Data
Register
1
0
1/0
1/0
1/0
1/0
Read the contents of the Register pointed to by P1 to P0 and R1 to R0
Write Data
Register
1
0
1/0
1/0
1/0
1/0
Write new value to the Register pointed to by P1 to P0 and R1 to R0
XFR Data
Register to WCR
0
1
1/0
1/0
1/0
1/0
Transfer the contents of the Register pointed to by P1 to P0 and R1 to
R0 to its associated WCR
1
1
0
1/0
1/0
1/0
1/0
Transfer the contents of the WCR pointed to by P1 to P0 to the Register
pointed to by R1 to R0
0
0
0
1
X
X
1/0
1/0
Transfer the contents of the Data Registers pointed to by R1 to R0 of all
four pots to their respective WCR
Global XFR
WCR to Data
Register
1
0
0
0
X
X
1/0
1/0
Transfer the contents of all WCRs to their respective data Registers
pointed to by R1 to R0 of all four pots
Increment/
Decrement
Wiper
0
0
1
0
1/0
1/0
X
X
P1
P0
1/0
1/0
0
1/0
1
1
1
0
1
1
XFR WCR to
Data Register
1
Global XFR
Data Register to
WCR
(Note 1)
(Note 2)
Enable Increment/decrement of the WCR pointed to by P1 to P0
NOTES:
1. 1/0 = data is one or zero
2. X = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical).
6
FN8164.7
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X9241A
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
STAR T
ACKNOWLEDGE
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
7
FN8164.7
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X9241A
The WCR is a volatile register; that is, its contents are lost
when the X9241A is powered-down. Although the register is
automatically loaded with the value in DR0 upon power-up, it
should be noted this may be different from the value present
at power-down.
Detailed Operation
All four XDCP potentiometers share the serial interface and
share a common architecture. Each potentiometer is
comprised of a resistor array, a Wiper Counter Register and
four Data Registers. A detailed discussion of the register
organization and array operation follows.
Data Registers
Each potentiometer has four nonvolatile Data Registers.
These can be read or written directly by the host and data
can be transferred between any of the four Data Registers
and the WCR. It should be noted all operations changing
data in one of these registers is a nonvolatile operation and
will take a maximum of 10ms.
Wiper Counter Register
The X9241A contains four volatile Wiper Counter Registers
(WCR), one for each XDCP potentiometer. The WCR can be
envisioned as a 6-bit parallel and serial load counter with its
outputs decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
WCR instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
increment/decrement instruction; finally, it is loaded with the
contents of its Data Register zero (DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be used
as regular memory locations that could possibly store
system parameters or user preference data.
SERIAL DATA PATH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
VH/RH
REGISTER 1
8
6
REGISTER 2
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
REGISTER 3
2
INC/DEC
LOGIC
IF WCR = 00[H] THEN VW/RW = VL/RL
UP/DN
IF WCR = 3F[H] THEN VW/RW = VH/RH
MODIFIED SCL
C
O
U
N
T
E
R
D
E
C
O
D
E
UP/DN
VL/RL
CLK
DW
CASCADE
CONTROL
LOGIC
VW/RW
CM
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM
8
FN8164.7
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X9241A
When operating in cascade mode VH/RH, VL/RL and the
wiper terminals of the cascaded arrays must be electrically
connected externally. All but one of the wipers must be
disabled. The user can alter the wiper position by writing
directly to the WCR or indirectly by transferring the contents
of the Data Registers to the WCR or by using the
Increment/Decrement command.
Cascade Mode
The X9241A provides a mechanism for cascading the
arrays. That is, the sixty-three resistor elements of one array
may be cascaded (linked) with the resistor elements of an
adjacent array. The VL/RL of the higher order array must be
connected to the VH/RH of the lower order array (See
Figure 9).
When using the Increment/Decrement command the wiper
position will automatically transition between arrays. The
current position of the wiper can be determined by reading
the WCR registers; if the DW bit is “0”, the wiper in that array
is active. If the current wiper position is to be maintained on
power-down a global XFR WCR to Data Register command
must be issued to store the position in NV memory before
power-down.
Cascade Control Bits
The data byte, for the three-byte commands, contains 6-bits
(LSBs) for defining the wiper position plus 2 high order bits,
CM (Cascade Mode) and DW (Disable Wiper, normal
operation).
The state of the CM bit (bit 7 of WCR) enables or disables
cascade mode. When the CM bit of the WCR is set to “0” the
potentiometer is in the normal operation mode. When the
CM bit of the WCR is set to “1” the potentiometer is
cascaded with its adjacent higher order potentiometer. For
example; if bit 7 of WCR2 is set to “1”, pot 2 will be cascaded
to pot 3.
It is possible to connect three or all four potentiometers in
cascade mode. It is also possible to connect POT 3 to POT 0
as a cascade. The requirements for external connections of
VL/RL, VH/RH and the wipers are the same in these cases.
The state of DW enables or disables the wiper. When the
DW bit (bit 6 of the WCR) is set to “0” the wiper is enabled;
when set to “1” the wiper is disabled. If the wiper is disabled,
the wiper terminal will be electrically isolated and float.
POT 0
WCR0
VL0/RL0
VH0/RH0
VW0/RW0
POT 1
WCR1
VL1/RL1
VH1/RH1
VW1/RW1
POT 2
WCR2
VL2/RL2
VH2/RH2
VW2/RW2
POT 3
WCR3
=
EXTERNAL
CONNECTION
VL3/RL3
VH3/RH3
VW3/RW3
FIGURE 9. CASCADING ARRAYS
9
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X9241A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) Limits
X9241A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Max Wiper Current for 2k RTOTAL . . . . . . . . . . . . . . . . . . . . . . ±4mA
Max Wiper Current for 10k and 50k RTOTAL . . . . . . . . . . . . . . ±3mA
Voltage on SCK, SCL or any address
input with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage on any VH/RH, VW/RW or VL/RL
referenced to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V/-4V
V = |VH/RH - VL/RL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
Temperature under bias. . . . . . . . . . . . . . . . . . . . . . . . -65 to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Analog Specifications
(Over recommended operating conditions unless otherwise stated).
LIMITS
SYMBOL
RTOTAL
RW
VTERM
PARAMETER
End to end resistance
TYP
MAX
(Note 11)
UNIT
+20
%
130

+5
V
-20
Wiper resistance
Wiper Current = (VH - VL)/RTOTAL
40
Voltage on any VH/RH, VW/RW or VL/RL Pin
-3.0
Noise
Ref: 1kHz (Note 7)
Resolution
(Note 7)
Absolute linearity (Note 3)
Rw(n)(actual) - Rw(n)(expected)
Relative linearity (Note 4)
Rw(n + 1) - [Rw(n) + MI]
120
dBV
1.6
%
±1
MI (Note 5)
±0.2
MI (Note 5)
Temperature coefficient of RTOTAL
(Note 7)
±300
ppm/°C
Ratiometric temperature coefficient
(Note 7)
±20
ppm/C
15/15/25
pF
CH/CL/CW Potentiometer capacitances
lAL
MIN
(Note 11)
TEST CONDITION
See Circuit #3 and (Note 7)
RH, RI, RW leakage current
DC Electrical Specifications
VIN = VTERM. Device is in stand-by mode.
0.1
1
µA
(Over recommended operating conditions unless otherwise stated.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
3
mA
lCC
Supply current (active)
ISB
VCC current (standby)
SCL = SDA = VCC, Addr. = VSS
500
µA
ILI
Input leakage current
VIN = VSS to VCC
10
µA
ILO
Output leakage current
VOUT = VSS to VCC
10
µA
VIH
Input HIGH voltage
VIL
Input LOW voltage
VOL
Output LOW voltage
fSCL = 100kHz, Write/Read to WCR,
Other Inputs = VSS
200
2
IOL = 3mA
V
0.8
V
0.4
V
NOTES:
3. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
4. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
5. MI = RTOT/63 or (RH – RL)/63, single pot
6. Max = all four arrays cascaded together, Typical = individual array resolutions.
10
FN8164.7
August 17, 2015
X9241A
Endurance and Data Retention
PARAMETER
Minimum endurance
MIN
UNIT
100,000
Data changes per bit per register
100
Years
Data retention
Capacitance
SYMBOL
PARAMETER
TEST CONDITION
TYP
UNIT
CI/O (Note 7)
Input/output capacitance (SDA)
VI/O = 0V
19
pF
CIN (Note 7)
Input capacitance (A0, A1, A2, A3 and SCL)
VIN = 0V
12
pF
Power-up Timing
SYMBOL
PARAMETER
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
tPUR (Note 8)
Power-up to initiation of read operation
1
ms
tPUW (Note 8)
Power-up to initiation of write operation
5
ms
50
V/ms
tRVCC
VCC Power up ramp rate
0.2
Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that Vcc reach 90% of its
final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or
slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V.
NOTES:
7. Limits should be considered typical and are not production tested.
8. Limits established by characterization and are not production tested.
9. Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
10. Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that
is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device.
11. Parts are 100% tested at either +70°C or +85°C. Over temperature limits established by characterization and are not production tested.
Symbol Table
AC Conditions of Test
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing levels
VCC x 0.5
Input pulse levels
VCC x 0.1 to VCC x 0.9
11
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8164.7
August 17, 2015
X9241A
Equivalent AC Test Circuit
Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors
5V
120
1533
RMIN =
RESISTANCE (k)
100
SDA OUTPUT
100pF
VCC MAX
TR
RMAX =
80
=1.8k
IOL MIN
CBUS
MAXIMUM
RESISTANCE
60
40
20
0
MIN.
RESISTANCE
0
20
40
60
80
100
120
BUS CAPACITANCE (pF)
Circuit #3 SPICE Macro Model
DCP Wiper Current De-rating Curve
MAXIMUM DCP WIPER CURRENT
MACRO MODEL
RTOTAL
RH
RL
CL
CH
15pF
CW
15pF
25pF
RW
7
6
5
4
3
2
1
0
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (°C)
tHIGH
tLOW
tF
tR
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA
(DATA IN)
tBUF
FIGURE 10. INPUT BUS TIMING
AC Electrical Specifications
(Over recommended operating conditions unless otherwise stated).
LIMITS
SYMBOL
PARAMETER
MIN
(Note 11)
MAX
(Note 11)
UNIT
REFERENCE
FIGURE
NUMBER(S)
0
100
kHz
10
fSCL
SCL clock frequency
tLOW
Clock LOW period
4700
ns
10
tHIGH
Clock HIGH period
4000
ns
10
tR
SCL and SDA rise time
1000
ns
10
tF
SCL and SDA fall time
300
ns
10
Noise suppression time constant (glitch filter)
20
ns
10
Ti, (Note 11)
tSU:STA
Start condition setup time (for a repeated start condition)
4000
ns
10 and 12
tHD:STA
Start condition hold time
4000
ns
10 and 12
12
FN8164.7
August 17, 2015
X9241A
AC Electrical Specifications
(Over recommended operating conditions unless otherwise stated). (Continued)
LIMITS
SYMBOL
MIN
(Note 11)
PARAMETER
MAX
(Note 11)
UNIT
REFERENCE
FIGURE
NUMBER(S)
tSU:DAT
Data in setup time
250
ns
10
tHD:DAT
Data in hold time
0
ns
10
ns
11
30
ns
11
Stop condition setup time
4000
ns
10 and 12
tBUF
Bus free time prior to new transmission
4700
ns
10
tWR
Write cycle time (nonvolatile write operation)
10
ms
13
Wiper response time from stop generation
500
µs
13
Wiper response from SCL LOW
1000
µs
6
tAA
SCL LOW to SDA data out valid
tDH
Data out hold time
tSU:STO
tSTPWV
tCLWV
3500
SCL
tAA
SDAOUT
SDA
tDH
(ACK)
SDAOUT
SDAOUT
FIGURE 11. OUTPUT BUS TIMING
START CONDITION
STOP CONDITION
SCL
tSU:STA
tHD:STA
tSU:STO
SDA
(DATA IN)
FIGURE 12. START STOP TIMING
SCL
CLOCK 8
CLOCK 9
STOP
START
tWR
tSTPWV
SDA
SDAIN
ACK
WIPER
OUTPUT
FIGURE 13. WRITE CYCLE AND WIPER RESPONSE TIMING
13
FN8164.7
August 17, 2015
X9241A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 17, 2015
FN8164.7
CHANGE
- Ordering Information Table on page 2.
- Added Revision History beginning with Rev 1.
- Added About Intersil Verbiage.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at
www.intersil.com/support
14
FN8164.7
August 17, 2015
X9241A
Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B
D
MDP0044
A
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
0.20 C B A
1
(N/2)
B
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
15
FN8164.7
August 17, 2015
X9241A
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
16
FN8164.7
August 17, 2015
X9241A
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8164.7
August 17, 2015