AN1974 Introduction to USB Power Delivery Over the USB Type-C™ Cable Author: Andrew Rogers & Josh Averyt Microchip Technology Inc. INTRODUCTION The USB Power Delivery revision 2.0 specification details how the Power Delivery (PD) protocol truly “unlocks” the advanced features of the USB Type-C™ cable. Power Delivery protocol allows port-to-port communication that provides mechanisms for: negotiating power roles, negotiating power sourcing and consumption levels, performing active cable identification, exchanging vendor specific sideband messaging, and performing Alternate Mode negotiation allowing 3rd party communication protocols to be routed onto the USB Type-C cable’s reconfigurable pins. If you are not yet familiar with the USB Type-C, please refer to Application Note AN1953 “Introduction to USB TypeC™” before reading this document. SECTIONS Section 1.0, General Information Section 2.0, USB PD Protocol Layer Section 3.0, PD Physical Layer Section 4.0, Cable Identification Section 5.0, Power and Data Negotiation Section 6.0, Alternate Modes REFERENCES This document is an introduction to USB Power Delivery 2.0 and is not intended to be a replacement to the official specification. Consult the following specifications for technical details not described in this document. • • • • • • USB Type-C™ Specification USB Power Delivery 2.0 Specification USB 2.0 Specification USB 3.0 Specification USB 3.1 Specification USB Battery Charging BC1.2 GLOSSARY DFP - “Downstream Facing Port”. A USB host-side port or hub downstream port. UFP - “Upstream Facing Port”. A USB device-side port or hub upstream connection. DRP - “Dual Role Port”. A USB port that may operate as either a DFP or a UFP. Source - The provider of VBUS power in a USB connection. Sink - The consumer of VBUS power in a USB connection. USB PD - Abbreviation of USB Power Delivery. SOP* - The Start of Frame field in a USB Power Delivery packet indicates the intended recipient of the packet. VCONN - the dedicated power supply rail for cables and accessories. USB-IF - USB Implementers Forum. A non-profit corporation found by the group of companies that developed USB. 2015 Microchip Technology Inc. DS00001974A-page 1 AN1974 1.0 GENERAL INFORMATION The USB Type-C cable is a reversible 24-pin interconnect created by the USB-IF. The USB Type-C™ specification was first released in August 2014. Power Delivery revision 2.0 is a overhaul of the specification to provide compatibility for the new USB Type-C™ specification. Power Delivery revision 2.0 protocol is what truly unlocks the advanced capabilities of the USB Type-C. These features include: • • • • • • Elevated VBUS voltage and current capability. Dynamic power contract renegotiation. Dynamic power role swapping Dynamic Data Role Swapping Electronically Marked Cable Identification Alternate Modes 1.1 Elevated VBUS Voltage and Current Capability A standard USB Type-C connection allows for up to 15W (5V at 3A) of power without USB Power Delivery messaging. If Power Delivery messaging is implemented, power levels provided across the cable can be extended beyond the 15W. By default all passive USB Type-C cables support up to 60W of power (20V at 3A). This can be extended up to 100W (20V at 5A) with electronically marked cables that are identified as either an active cable or one that is capable of extended current capability. See Section 5.0, Power and Data Negotiation for additional details. 1.2 Dynamic Power Contract Renegotiation USB Power Delivery messaging can be used to dynamically change the power negotiation to any values in the ranges 5V-20V and 0A-5A at any time during a USB Type-C connection. See Section 5.0, Power and Data Negotiation for additional details. 1.3 Dynamic Power Role Swapping The roles of power source and power sink may also be changed dynamically via USB Power Delivery messaging. A Source or a Sink may request at any time to change roles. See Section 5.0, Power and Data Negotiation for additional details. 1.4 Dynamic Data Role Swapping Either a DFP or UFP may request a data role swap at any time over USB Power Delivery messaging. If the request is accepted by the port partner, the data roles will be reversed. Note that the power role (source/sink) is not affected by a data role swap. See Section 5.0, Power and Data Negotiation for additional details. 1.5 Electronically-Marked Cable Identification USB Type-C cables may or may not be electronically marked. Electronically marked cables may also send and receive USB Power Delivery messages to communicate specific attributes. See Section 4.0, Cable Identification for additional details. 1.6 Alternate Mode The USB Type-C™ specification allows for additional independently defined and organized specifications which allow for alternate protocols to be transmitted on the USB Type-C cable. There are no specific limitations on Alternate Modes provided the USB Type-C cable can support it and a USB2.0 and USB Power Delivery connection is maintained. See Section 6.0, Alternate Modes for additional details. DS00001974A-page 2 2015 Microchip Technology Inc. AN1974 2.0 USB PD PROTOCOL LAYER The general anatomy of a USB Power Delivery packet is shown in Figure 1 below. FIGURE 1: Preamble POWER DELIVERY PROTOCOL PACKET FORMAT SOP* Header Byte 0 Byte 1 Byte n-1 Byte n CRC EOP Provided by Protocol Layer Provided by Physical Layer, 4b5b encoded Provided by Physical Layer, not encoded 2.1 Preamble Every USB Power Delivery packet begins with a 64-bit sequence of alternating 0s and 1s. This preamble is used to train the receiver and achieve lock. 2.2 Start of Packet (SOP*) Signaling The Start of Packet field typically also indicates the intended recipient. Some fundamental commands can also be sent through the SOP* field. These addresses/commands are collectively called SOP*. Table 1 below defines the SOP signaling. TABLE 1: SOP* SIGNALING DEFINITIONS Name Value Use SOP 11000 11000 11000 10001 Communication to UFP SOP’ 11000 11000 00110 00110 Communication to USB Type-C Plug Side A SOP’’ 11000 00110 11000 00110 Communication to USB Type-C Plug Side B Hard Reset 00111 00111 00111 11001 Resets logic in all connected PD devices (UFP and/or Active/Electronically Marked Cable) Cable Reset 00111 11000 00111 00110 Reset for only Active/Electronically Marked Cable. SOP’_Debug 11000 11001 11001 00110 Used for debug of USB Type-C Plug Side A SOP’’_Debug 11000 11001 00110 10001 Used for debug of USB Type-C Plug Side B 2015 Microchip Technology Inc. DS00001974A-page 3 AN1974 FIGURE 2: SOP* SIGNALING DFP UFP ELECTRONICALLY MARKED CABLE CABLE PLUG CABLE PLUG SOP’ SOP’’ SOP Note: 2.3 SOP’ is assigned to one plug of the cable while SOP’’ is assigned to the other. The cable plugs cannot tell which side that they are connected to, just that one end may respond to SOP’ addressed messages and the other may respond SOP’’ addressed messages. Header Every USB Power Delivery message begins with a 16-bit header. The header contains basic information including the length of the data to follow. The header may also be used as a standalone control message if the data length field is zero. DS00001974A-page 4 2015 Microchip Technology Inc. AN1974 3.0 PD PHYSICAL LAYER Every USB Power Delivery device must have a PD physical layer that contains both a transmitter and a receiver. All power delivery communication occurs at half duplex over the CC (Configuration Channel) wire on the USB Type-C cable. The DFP is the Bus Master and initiates all communication. 3.1 Transmitter The transmitter performs the following: 1. 2. 3. 4. Receive raw (non-encoded) packet data from protocol layer. Calculate a CRC and append to end of data packet. Encode the whole packet (with CRC) in 4b5b encoding. Transmit the entire packet (preamble, SOP*, data payload, CRC, and EOP) FIGURE 3: PD TRANSMITTER Packet From Protocol Layer 3.2 4b5b Encoder CRC Generator To CC Wire Transmitter Receiver The receiver performs the following: 1. 2. 3. 4. Recovers clock from the packet preamble. Detect SOP* Decode from 4b5b to raw data (included CRC) Detect EOP and validate CRC. If valid, delver packet to protocol layer. If invalid, flush data. FIGURE 4: From CC Wire 3.3 PD RECEIVER Receiver SOP* Detect 4b5b Decoder EOP Detect + CRC Check CRC = Good CRC = Bad To Protocol Layer Flush Data BMC Signaling All messages are Biphase Mark Coding (BMC), a modification of Manchester coding where a ‘zero’ has one transition and a ‘one’ has two transitions. All messages occur at a 300k Baud rate. The signaling is effectively DC balanced with a nominal voltage swing of 1.125V. 2015 Microchip Technology Inc. DS00001974A-page 5 AN1974 FIGURE 5: Data In BMC SIGNALING 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 Before Encoding BMC DS00001974A-page 6 2015 Microchip Technology Inc. AN1974 4.0 CABLE IDENTIFICATION The USB Type-C™ specification introduced VCONN, the dedicated power supply rail for cables and accessories with electronic marker ICs embedded within. Cables which contain electronic markers must terminate their VCONN line with value Ra (1 kΩ) in order to allow the USB Type-C Source (which is also the default DFP upon initial connection) to detect that an electronic marker is present, and source VCONN power in addition to VBUS power. In particular, active cables (those that include signal conditioning electronics) and cables supporting VBUS currents in excess of 3A are required to include the electronic marker, for storing vendor and other feature details of these cables. Collectively, these details are called the “Identity”. If the USB Type-C Source is USB PD-enabled, then before any power negotiation begins, the Source should discover the cable’s Identity as described by the following sequence: 1. 2. 3. Source sends Discover Identity command message to SOP’ (see Section 2.2, Start of Packet (SOP*) Signaling), directing the message to the cable’s electronic marker. The SOP’ device responds with GoodCRC to confirm proper receipt of the Discover Identity command. The SOP’ device then sends a Discover Identity ACK response back to the Source, with its Identity information enclosed. This message contains a header and 160 bits of description data for the cable. Note: 4. The exact detail of this Discover Identity data is beyond the scope of this application note but to summarize, the data contains fields describing the following: - USB Vendor ID and Product ID - USB Test ID (for USB certification traceability) - Product Hardware & Firmware Revisions - Interconnect Type (USB Type-C Plug or Receptacle) - Cable Latency (specified in nanoseconds) - Cable Terminations - SuperSpeed Data Directionality - VBUS Current Handling Capability (3 or 5 Amps) - USB SuperSpeed Signaling Capability (Gen 1/Gen 2) - Modes Supported? (Boolean, can prompt further Discovery queries) The Source responds with GoodCRC and then evaluates the contents of the Identity. Not all USB Power Delivery-capable ports are necessarily sensitive to all the details returned by an active cable. However, ports designed to be able to supply more than 3 A of current must confirm the cable is designated with the 5 A current capability. Based upon that evaluation, the USB Power Delivery port knows whether or not to “advertise” any power profiles to its port partner which exceed 3 A. Note: By USB Type-C™ specification, if there is no electronic marker detected and/or no response from the cable, then it must be assumed that the cable is only capable of supporting current up to 3 A. 2015 Microchip Technology Inc. DS00001974A-page 7 AN1974 5.0 POWER AND DATA NEGOTIATION In classic USB, the DFP was always the Source and the UFP was always the Sink. However, products which implement USB Power Delivery protocol can dynamically negotiate the following: • Increasing/decreasing voltage - Sink may request & sink power from the Source at voltages ranging 5-20 V if both the Source and Sink support it. • Increasing/decreasing current - Sink may request & sink power from the Source at currents ranging 0-5 A if the Source, Sink, and cable support it. Note: The above voltage and current range allows for up to a 100 W power connection between two USB PD products. • Power Role Swap (PR_SWAP) - Original Source (for VBUS) may “swap” to Sink role, and vice versa. When a power role swap occurs, VBUS is discharged to 0 V by the old Source, prior to the new Source driving VBUS, in order to prevent unsafe power scenarios. • Data Role Swap (DR_SWAP) - Original DFP/Host may “swap” to UFP/Device role, and vice versa. The partner with the DFP role becomes the USB PD bus master, in addition to the assumed role as USB Host. • VCONN Swap (VCONN_SWAP) - Original Source may “swap” its VCONN source responsibility with the Sink. After the default power and data roles are designated upon USB Type-C connection between two port partners [refer to Application Note (AN 1953) “Introduction to USB Type-C™” for further clarification], these additional power and data negotiations may take place over USB PD protocol when both partners are USB PD-capable, and an explicit power contract has been established between them. To determine if the default Sink device is USB PD-capable, the default Source attempts to enter an explicit USB PD power contract with the Sink as the following sequence describes: 1. 2. 3. The Source sends a Source_Capabilities USB PD message to the Sink which includes a menu of available VBUS power supply options (the first option must be the 5 V default VBUS supply, but may also include up to 6 additional power options). A USB PD-capable Sink will respond first with a GoodCaRC message to confirm proper receipt of the Source_Capabilities. The Sink replies with a Request message indicating which of the power supply options it prefers to use. Note: 4. 5. 6. 7. 8. At this point in the transaction, the Source knows the Sink is USB PD-capable and continues with the explicit contract negotiation. The Source responds with a GoodCRC message and verifies the Request is valid. The Source sends an Accept message to the Sink. The Sink replies with GoodCRC The Source transitions its power supply to the requested voltage level and current limit. When the power supply is transitioned, the Source sends a PS_RDY (power supply ready) message to the Sink. The Sink replies with GoodCRC and begins to sink power under the explicit contract’s voltage and current allocation. Note: This example describes the USB PD communications between port partners in terms of Source and Sink because no Power Role Swap or Data Role Swap have previously occurred in the session and are therefore still in their default USB Type-C roles. Therefore we can equate the Source as the DFP, and the Sink as the UFP. DS00001974A-page 8 2015 Microchip Technology Inc. AN1974 6.0 ALTERNATE MODES Alternate Modes allow the USB Type-C cable to be reconfigured to support 3rd party (e.g. standards groups or vendors) protocols. This feature is enabled only if both ports support the USB Power Delivery protocol and are both compatible with the specific Alternate Mode. As long as the cable can support the 3rd party protocol signaling while maintaining a USB2.0 connection and USB Power Delivery connection, then the Alternate Mode can be implemented. The USB Type-C and USB Power Delivery specifications do not define any Alternate Modes themselves; Each 3rd party must maintain its own USB Type-C Alternate Mode specification. Alternate Mode negotiation is performed via USB Power Delivery protocol between port partners after Alternate mode compatibility is realized using the Discovery messages (Discover Identity, Discover SVIDs, and Discover Modes). 6.1 Reconfigurable Pins All Alternate Modes must minimally maintain a USB2.0 and USB Power Delivery connection. The following pins/wires may be reconfigured for the use with the Alternate Mode. FIGURE 6: RECONFIGURABLE PINS ON A FULL FEATURED CABLE A12 A11 A10 A9 A8 GND RX2+ RX2- VBUS SBU1 A7 D- A6 D+ GND TX2+ TX2- VBUS VCONN B1 FIGURE 7: B2 B3 B4 B5 A4 A3 A2 A1 CC VBUS TX1- TX1+ GND SBU2 VBUS RX1- RX1+ GND B6 B7 B8 B9 B10 B11 B12 RECONFIGURABLE PINS ON A DIRECT CONNECT APPLICATION A12 A11 A10 A9 A8 GND RX2+ RX2- VBUS SBU1 A7 D- A6 D+ GND TX2+ TX2- VBUS VCONN B1 6.2 A5 B2 B3 B4 B5 A5 A4 A3 A2 A1 CC VBUS TX1- TX1+ GND SBU2 VBUS RX1- RX1+ GND B6 B7 B8 B9 B10 B11 B12 Alternate Mode Example: DisplayPort DisplayPort was one of the first 3rd party standards (as defined by VESA) to be specified as a USB Type-C Alternate Mode. The DisplayPort Alternate Mode supports the following modes of operation: • (2) DisplayPort lanes + (1) USB3.1 lane • (4) DisplayPort lanes FIGURE 8: (2) DISPLAY PORT LANES + (1) USB3.1 LANE EXAMPLE A12 A11 A10 A9 A8 GND DP1- DP0+ VBUS AUX+ A7 D- A6 D+ GND DP1+ DP0- VBUS VCONN B1 B2 2015 Microchip Technology Inc. B3 B4 B5 A5 A4 A3 A2 A1 CC VBUS TX1- TX1+ GND AUX- VBUS RX1- RX1+ GND B6 B7 B8 B9 B10 B11 B12 DS00001974A-page 9 AN1974 6.2.1 STRUCTURED VENDOR DEFINED MESSAGES (SVDM) FOR DISPLAYPORT Structured Vendor Defined Messages or SVDMs are a class of USB Power Delivery messages which enable nonpower-related messages to be communicated between port partners. These messages serve a variety of use-cases including discovery of port partner and cable identity (as described in Section 4.0, Cable Identification), the discovery of supported Alternate Modes (by use of similar Discover SVIDs (Standards/Vendor ID) and Discover Modes commands), and exchange of messages specific to Alternate Modes, once those modes are explicitly negotiated. DisplayPort’s Alternate Mode specification defines three primary SVDMs: • DisplayPort Capabilities This message contains what the UFP’s DisplayPort capabilities are (number of DisplayPort lanes supported), USB support, connector type (plug/receptacle), and pin assignments supported. • DisplayPort Configure This message is a command which tells the UFP to reconfigure for a specific DisplayPort pin assignment, reconfigure to operate as a DisplayPort Source or DisplayPort Sink, and which signaling type to use (USB 3.1 Gen 2 vs. DisplayPort v1.3) • DisplayPort Status This message is used to convey: DisplayPort connection state, DisplayPort Hot Plug Detect (HPD) state (High/ Low/IRQ), USB mode enabled/disabled, DisplayPort mode enabled/disabled, DisplayPort adapter power status, and whether there is a pending request to exit DisplayPort Alternate Mode. The HPD state feature of this DisplayPort Status SVDM is worth noting because in classic DisplayPort, HPD is a dedicated signal that is connected through the DisplayPort cable between the DisplayPort Source and Sink. However, there were not enough reconfigurable pins in the USB Type-C cable to accommodate this signal. Therefore, the DisplayPort specification committee designed this Alternate Mode so that the HPD signal would be bridged between the DisplayPort Source and Sink via USB Power Delivery protocol. The DisplayPort Sink drives the HPD pin, and the UFP’s USB Power Delivery controller detects that state, encodes it in a DisplayPort Status message for receipt by the DFP. The DFP then regenerates the HPD pin state locally for the DisplayPort Source, therefore completing a virtual circuit which is backward compatible with legacy DisplayPort ASICs. DS00001974A-page 10 2015 Microchip Technology Inc. AN1974 APPENDIX A: TABLE A-1: APPLICATION NOTE REVISION HISTORY REVISION HISTORY Revision Level & Date Note: Section/Figure/Entry Correction AN1974, Revision A replaces the previous SMSC version. 2015 Microchip Technology Inc. DS00001974A-page 11 AN1974 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support DS00001974A-page 12 2015 Microchip Technology Inc. AN1974 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-649-5 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2015 Microchip Technology Inc. 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