DATASHEET Micropower Voltage Reference with Comparator ISL21440 Features The ISL21440 is a micropower, FGA™ reference and comparator on a single chip. Drawing less than 5µA supply current over the full operating temperature range, the ISL21440 operates from a single 2V to 11V supply and can also be used with split bipolar supplies. • 5µA supply current over full temperature range The ISL21440’s on-board reference provides a 1.182V ±0.5% output. It features programmable hysteresis and TTL/CMOS compatible outputs that sink and source current. Low bias currents permit high value divider resistors for typical circuit current drains of <2.5µA. • Temperature range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C The low supply current makes the ISL21440 ideal for battery powered devices in battery level or low voltage monitor circuits. The ISL21440 is a pin-compatible, performance upgrade of both the LTC1440, LTC1540, MAX921 and MAX931. • Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . 2V to 11V • Precision 1.182V ±0.5% voltage reference • Comparator with user programmable hysteresis • 8 Ld MSOP and 8 Ld TDFN packages • Pin compatible upgrade to MAX921 and LTC1440 Applications • Low battery detector • Low voltage reset • Overvoltage monitor • Window comparator VDD VBAT 1.190 IN+ + IN- OUT 1.184 - HYST 20k 1.186 LoBAT- ISL21440 REF VREF (V) 1.8M V+ = 3V 1.188 V+ 2.4M V+ = 5V 1.182 1.180 1.178 V+ = 2V 1.176 2.4M V- GND 1.174 1.172 -40 LOW BATTERY DETECTOR FIGURE 1. TYPICAL APPLICATION March 17, 2016 FN6532.3 1 -20 0 20 40 60 TEMPERATURE (°C) 80 100 120 FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009-2011, 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL21440 Block Diagram V+ IN+ + IN- OUT - HYST ISL21440 REF V- GND FIGURE 3. BLOCK DIAGRAM Pin Descriptions Pin Configuration ISL21440 (8 LD MSOP, 8 LD TDFN) TOP VIEW PIN SYMBOL GND 1 8 OUT V- 2 7 V+ IN+ 3 6 REF IN- 4 5 HYST DESCRIPTION 1 GND Ground pin. Sets the comparator output low level. 2 V- Negative supply input for voltage reference and comparator. 3 IN+ Comparator noninverting input pin. Range: V- to V+ -1.5V. 4 IN- Comparator inverting input pin. Range: V- to V+ -1.5V 5 HYST Comparator hysteresis input. Accepts a voltage divided from the reference output. Range is VREF - 50mV to VREF. Connect directly to VREF for zero hysteresis. 6 REF Reference output. Source 2mA and Sink 10µA. 7 V+ Positive supply input for comparator and reference. Range is 2.0V to 11.0V 8 OUT Comparator output, CMOS push-pull. Output swing referenced to V+ and GND. Ordering Information PART NUMBER (Notes 3, 4) PART MARKING VDD RANGE (V) TEMP RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL21440IRTZ (Note 1) 1440 2 to 11 -40 to +125 8 Ld TDFN L8.3x3G ISL21440IUZ (Note 2) 1440Z 2 to 11 -40 to +125 8 Ld MSOP M8.118 NOTES: 1. Add “-T13” suffix for 6k unit Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. Add “-T13” suffix for 2.5k unit Tape and Reel option. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL21440. For more information on MSL please see techbrief TB363. Submit Document Feedback 2 FN6532.3 March 17, 2016 ISL21440 Absolute Maximum Ratings Thermal Information Supply Voltage Range, V+ to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +12V IN+, IN- with Respect to V- . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V+) +0.3V GND with Respect to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V to -0.3V V+ with Respect to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V to -0.3V REF, HYST with Respect to V- . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.5V Out with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . (V+) +0.3V to -0.3V Voltage on All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Latch-Up (Tested Per JESD-78B; Class 1, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 8 Ld MSOP Package (Notes 6, 8) . . . . . . . . 154 55 8 Ld TDFN Package (Notes 6, 7). . . . . . . . . 68 8 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile (Note 9). . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Environmental Operating Conditions X-Ray Exposure (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mRem CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Measured with no filtering, distance of 10” from source, intensity set to 55kV and 70mA current, 30s duration. Other exposure levels should be analyzed for output voltage drift effects. See “Applications Information” on page 10. 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 8. For JC, the “case temp” location is taken at the package top center. 9. Post-reflow drift for the ISL21440 device voltage reference output will range from 100mV to 1.0mV based on experimental results with devices on FR4 double sided boards. The design engineer must take this into account when considering the reference voltage after assembly. Analog Specifications (V+ = +5.0V) operating temperature range, -40°C to +125°C. SYMBOL V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply across the PARAMETER TEST CONDITIONS MIN (Note 11) TYP (Note 10) MAX (Note 11) UNIT 11.0 V 0.75 µA 5 µA ±3 mV ±3.25 mV ±3.6 mV ±3.75 mV POWER SUPPLY V+ Supply Voltage Range V- = GND ICC Supply Current IN+ = IN- +80mV, HYST = REF 2.0 0.46 COMPARATOR VOS Input Offset Voltage VCM = 2.5V MSOP Package TDFN Package IIN VCM CMRR Input Leakage Current (IN+, IN-, HYST) VIN+ = VIN- = 2.5V MSOP Package 0.1 1.4 nA TDFN Package 0.1 1.5 nA 3 nA (V+) - 1.5 V 3 mV/V 3.5 mV/V 4.5 mV/V 5 mV/V Common-Mode Input Range Common-Mode Rejection Ratio VV- to (V+ - 1.5V) MSOP Package TDFN Package Submit Document Feedback 3 1.2 1.2 FN6532.3 March 17, 2016 ISL21440 Analog Specifications (V+ = +5.0V) V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PSRR PARAMETER Power Supply Rejection Ratio TEST CONDITIONS V+ = 2V to 11V MIN (Note 11) MSOP Package 0.25 TDFN Package VHYST tPHL tPLH Hysteresis Input Voltage TYP (Note 10) 0.25 REF - 50mV Propagation Delay - HIGH to LOW Transition CL = 100pF Propagation Delay - LOW to HIGH Transition CL = 100pF VOH Output High Voltage IO = -10mA VOL Output Low Voltage IO = 3mA Reference Voltage No Load Output Load Regulation 0 ≤ ISOURCE ≤2mA MAX (Note 11) UNIT 1.1 mV/V 1.2 mV/V 1.5 mV/V 1.6 mV/V REF V Overdrive = 10mV 100 µs Overdrive = 100mV 50 µs Overdrive = 10mV 200 µs Overdrive = 100mV 100 µs (V+) - 0.4 V GND + 0.4 V 1.188 V REFERENCE VREF VREF 1.176 -0.5 0≤ISINK ≤10µA Analog Specifications (V+ = +3.0V) operating temperature range, -40°C to +125°C. SYMBOL 0.1 -2.0 mV -2.5 mV 2.0 mV 2.5 mV V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply across the PARAMETER TEST CONDITIONS MIN (Note 11) TYP (Note 10) MAX (Note 11) UNIT 0.40 0.7 µA 5 µA ±3.4 mV ±3.5 mV ±4.2 mV ±4.3 mV 1.1 nA 3 nA (V+) - 1.5 V 5 mV/V 5.5 mV/V 7.5 mV/V 8 mV/V V+ = 3.0V, V- = GND = 0V ICC Supply Current IN+ = IN- +80mV, HYST = REF COMPARATOR VOS Input offset Voltage VCM = 1.5V MSOP Package ±2.3 TDFN Package IIN VCM CMRR Input Leakage Current (IN+, IN-, HYST) VIN+ = VIN- = 1.5V 0.1 Common-Mode Input Range Common-Mode Rejection Ratio VV- to (V+ - 1.5V) MSOP Package TDFN Package Submit Document Feedback 4 ±2.3 1.2 1.2 FN6532.3 March 17, 2016 ISL21440 Analog Specifications (V+ = +3.0V) V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PSRR PARAMETER MIN (Note 11) TEST CONDITIONS Power Supply Rejection Ratio V+ = 2V to 11V TYP (Note 10) MSOP Package 0.25 TDFN Package VHYST tPHL tPLH 0.25 Hysteresis Input Voltage REF - 50mV Propagation Delay - HIGH to LOW Transition CL = 100pF Propagation Delay - LOW to HIGH Transition CL = 100pF VOH Output High Voltage IO = -6mA VOL Output Low Voltage IO = 1.8mA Reference Voltage No Load Output Load Regulation 0 ≤ ISOURCE ≤ 2mA MAX (Note 11) UNIT 1.1 mV/V 1.2 mV/V 1.5 mV/V 1.6 mV/V REF V Overdrive = 10mV 100 µs Overdrive = 100mV 50 µs Overdrive = 10mV 200 µs Overdrive = 100mV 100 µs (V+) - 0.4 V GND + 0.4 V 1.188 V REFERENCE VREF VREF 1.176 -0.5 0≤ ISINK ≤ 10µA 0.1 -2.0 mV -2.5 mV 2.0 mV -2.5 mV NOTES: 10. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40°C to +125°C = +165°C. 11. Parts are 100% tested at +25°C and +85°C. The -40°C and +125°C temperature limits are established by characterization and are not production tested. Typical Performance Curves 4.0 0.9 3.5 0.8 0.7 V+ = 5V 0.6 2.5 IDD (µA) IDD (µA) 3.0 2.0 1.5 1.0 0.4 0.3 0.2 0.5 0 -40 0.5 V+ = 3V -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 4. IDD vs TEMPERATURE Submit Document Feedback 5 100 120 0.1 0 2 3 4 5 6 7 8 9 10 11 VDD (V) FIGURE 5. IDD vs VDD FN6532.3 March 17, 2016 ISL21440 Typical Performance Curves (Continued) 1.190 1.190 V+ = 3V 1.188 1.186 1.186 V+ = 5V 1.184 VREF (V) 1.184 VREF (V) 1.188 1.182 1.180 1.178 1.182 1.180 1.178 V+ = 2V 1.176 1.176 1.174 1.174 1.172 -40 -20 0 20 40 60 80 100 1.172 120 2 3 4 5 6 FIGURE 6. VREF vs TEMPERATURE 10 11 12 1.188 1.187 V+ = 3V 1.181 1.186 1.180 VREF (V) VREF (V) 9 V+ = 5V 1.182 1.179 1.178 1.185 1.184 V+ = 2V 1.177 1.183 1.176 1.175 0 0.5 1.0 1.5 2.0 2.5 3.0 1.182 0 0.05 0.10 0.15 0.20 0.25 0.30 LOAD (mA) FIGURE 9. VREF vs LOAD (SINK) 3.0 1.25 2.5 1.20 2.0 OUTPUT (V) 1.30 1.15 NO LOAD 100µA LOAD 1.05 1.00 1.00 2mA LOAD 1.50 1.75 2.00 V+ (V) 2.25 2.50 2.75 FIGURE 10. VREF DROPOUT vs VREF OUTPUT vs LOAD Submit Document Feedback 6 V+ = 5V V+ = 3V 1.5 V+ = 2V V+ = 11V 1.0 0.5 10µA LOAD 1.25 0.35 0.40 0.45 0.50 LOAD (mA) FIGURE 8. VREF vs LOAD (SOURCE) VREF OUTPUT (V) 8 FIGURE 7. VREF vs SUPPLY VOLTAGE 1.183 1.10 7 VDD (V) TEMPERATURE (°C) 3.00 0 0 2 4 6 8 10 12 14 ILOAD (mA) FIGURE 11. COMPARATOR OUTPUT LOW VOLTAGE vs LOAD FN6532.3 March 17, 2016 ISL21440 Typical Performance Curves 12 6 10 5 8 4 V+ = 11V OUTPUT (V) OUTPUT (V) (Continued) V+ = 5V 6 4 V+ = 3V 2 3 2 1 V+ = 2V 0 0 5 10 15 20 25 30 ILOAD (mA) 35 40 45 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 50 IN+ - IN- (mV) FIGURE 13. HYSTERESIS - 0mV (V+ = 5V) 6 6 5 5 4 4 OUTPUT (V) OUTPUT (V) FIGURE 12. COMPARATOR OUTPUT HIGH VOLTAGE vs LOAD 3 2 3 2 1 1 0 -60-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 0 -60-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 IN+ - IN- (mV) IN+ - IN- (mV) FIGURE 15. HYSTERESIS - 25mV (V+ = 5V) 6 6 5 5 4 4 OUTPUT (V) OUTPUT (V) FIGURE 14. HYSTERESIS - 12.5mV (V+ = 5V) 3 2 3 2 1 1 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 IN+ - IN- (mV) 0 -60 -55 -50 -45 -40 -35-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 FIGURE 16. HYSTERESIS - 37.5mV (V+ = 5V) Submit Document Feedback 7 IN+ - IN- (mV) FIGURE 17. HYSTERESIS - 50mV (V+ = 5V) FN6532.3 March 17, 2016 ISL21440 (Continued) 3.5 3.5 3.0 3.0 2.5 2.5 OUTPUT (V) OUTPUT (V) Typical Performance Curves 2.0 1.5 2.0 1.5 1.0 1.0 0.5 0.5 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 0 -60-55 -50 -45 -40 -35 -30 -25-20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 IN+ - IN- (mV) IN+ - IN- (mV) FIGURE 19. HYSTERESIS - 12.5mV (V+ = 3V) 3.5 3.5 3.0 3.0 2.5 2.5 OUTPUT (V) OUTPUT (V) FIGURE 18. HYSTERESIS - 0mV (V+ = 3V) 2.0 1.5 2.0 1.5 1.0 1.0 0.5 0.5 0 -60 -55 -50 -45 -40 -35-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 IN+ - IN- (mV) 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 IN+ - IN- (mV) FIGURE 20. HYSTERESIS - 25mV (V+ = 3V) FIGURE 21. HYSTERESIS - 37.5mV (V+ = 3V) 200 3.5 180 3.0 160 140 tPHL (µs) OUTPUT (V) 2.5 2.0 1.5 120 100 80 3V 60 1.0 40 0.5 5V 20 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 IN+ - IN- (mV) FIGURE 22. HYSTERESIS - 50mV (V+ = 3V) Submit Document Feedback 8 0 10 20 30 40 50 60 70 80 90 100 110 120 INPUT VOLTAGE (mV) FIGURE 23. OUTPUT RESPONSE TIME vs INPUT OVERDRIVE (tPHL) FN6532.3 March 17, 2016 ISL21440 Typical Performance Curves (Continued) 5.5 600 5.0 4.5 500 4.0 OUTPUT (V) tPLH (µs) 400 300 200 3V 3.5 3.0 2.5 OUT 2.0 V+ 1.5 1.0 0.5 100 0 5V 0 10 20 30 40 50 60 70 80 90 100 -0.5 110 120 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (ms) INPUT VOLTAGE (mV) FIGURE 25. POWER-UP/DOWN OUTPUT RESPONSE (V+ = 5V, IN+ = V+, IN- = VREF) FIGURE 24. OUTPUT RESPONSE TIME vs INPUT OVERDRIVE (tPLH) 3.5 3.0 OUTPUT (V) 2.5 OUT 2.0 1.5 V+ 1.0 0.5 0 -0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (ms) FIGURE 26. POWER-UP/DOWN OUTPUT RESPONSE (V+ = 3V, IN+ = V+, IN- = VREF) Submit Document Feedback 9 FN6532.3 March 17, 2016 ISL21440 Functional Description Device Power The ISL21440 device has a single positive supply pin, V+, and two other supply pins, V- and GND. Normally, for single supply applications the V- pin is tied to system ground as well as the GND pin. The separate ground pin allows the comparator to be powered by split supplies from ±1.0V to ±5.5V. Note that the minimum supply voltage will be 0.8V above the comparator maximum input level for accurate operation. Comparator Section The comparator inputs can swing from the negative supply (GND pin) to within 0.8V of the positive supply (V+). Alternatively, with the comparator input set at the 1.182V reference level, the minimum input voltage for accurate operation is 2.0V. If the inputs are expected to see voltage levels above V+ or below ground, they should be clamped with low leakage Schottky diodes. The CMOS output swings essentially from the GND potential to V+ potential, depending on load current. If loads in excess of 1mA are expected, then a 0.1µF decoupling capacitor at the V+ pin should be added. Voltage Reference Section The voltage reference is a micropower FGA reference and is set to 1.182V ±0.5% at the factory. The reference output can source up to 2mA but the sink capability is very limited at only 10µA, maximum. Small value capacitors, up to 10nF, can be used on the reference output to lower noise if desired. Applications Information Handling and Board Mounting FGA references provide excellent initial accuracy and low temperature drift at the expense of very little power drain. There are some precautions to take to insure this accuracy is not compromised. Excessive heat during solder reflow can cause excessive initial accuracy drift, so the recommended +260°C maximum temperature profile should not be exceeded. Expect up to 1mV drift from the solder reflow process. FGA references are susceptible to excessive X-radiation like that used in PC board manufacturing. Initial accuracy can change 10mV or more under extreme radiation. If an assembled board needs to be X-rayed, care should be taken to shield the FGA reference device. Hysteresis The Hysteresis function allows for changing the value of the reference switchover point depending on the previous state of the comparator. This works to remove the effects of noise or glitches in the voltage detection input and provide more reliable output transitions. between the HYST pin and REF pin (VH = 2 * (VREF - VHYST)). Since the reference voltage is 1.182V (VREF), Equations 1 and 2 for these two resistors are shown as follows: R REF = V H 2 I REF = V REF – V HYST I REF (EQ. 1) R HYST = 1.182 – V H 2 I REF = V HYST I REF (EQ. 2) IREF is chosen to be less than the maximum output of the reference, usually 5µA is a safe value but for lowest power, 0.1µA can be used. If the hysteresis is not used, the HYST pin should be tied to the REF pin. Board Assembly Considerations FGA references provide high accuracy and low temperature drift but some PC board assembly precautions are necessary. Normal output voltage shifts of 100µV to 1mV can be expected with Pb-free reflow profiles or wave solder on multilayer FR4 PC boards. Precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures, this may reduce device initial accuracy. Post-assembly X-ray inspection may also lead to permanent changes in device output voltage and should be minimized or avoided. If X-ray inspection is required, it is advisable to monitor the reference output voltage to verify excessive shift has not occurred. If large amounts of shift are observed, it is best to add an X-ray shield consisting of thin zinc (300µm) sheeting to allow clear imaging, yet block x-ray energy that affects the FGA reference. Special Applications Considerations In addition to post-assembly examination, there are also other X-ray sources that may affect the FGA reference long term accuracy. Airport screening machines contain X-rays and will have a cumulative effect on the voltage reference output accuracy. Carry-on luggage screening uses low level X-rays and is not a major source of output voltage shift, although if a product is expected to pass through that type of screening over 100x it may need to consider shielding with copper or aluminum. Checked luggage X-rays are higher intensity and can cause output voltage shift in much fewer passes, so devices expected to go through those machines should definitely consider shielding. Note that just two layers of 1/2 ounce copper planes will reduce the received dose by over 90%. The lead frame for the device which is on the bottom also provides similar shielding. If a device is expected to pass through luggage X-ray machines numerous times, it is advised to mount a 2-layer (minimum) PC board over the top of the package, which, along with a ground plane underneath, will effectively shield it from 50 to 100 passes through the machine. Since these machines vary in X-ray dose delivered, it is difficult to produce an accurate maximum pass recommendation. Hysteresis is added to the ISL21440 by connecting one resistor between the REF and HYST pins (RREF), and another resistor(RHYST) between the HYST pin and ground. The hysteresis voltage (VH) is designed to be twice the voltage difference Submit Document Feedback 10 FN6532.3 March 17, 2016 ISL21440 Typical Applications Window Comparator Low Battery Detector Figure 27 shows a typical implementation for the ISL21440, a low battery detector. The values for RREF and RHYST provide 20mV of hysteresis and 0.5µA IREF. The input trip point for VDETECT is the same as the reference voltage, 1.182V, and a resistor divider at the input sets the LoBAT trip point at 2.7V. The total current draw for the circuit is going to be 1.1µA for VDD and 0.6µA for VBAT. VDD V+ IN+ + IN- 1.8M OUT LoBAT- - ISL21440 REF 2.4M R 3 = 1M 1% (EQ. 3) R2 = R3 VH VL – 1 (EQ. 4) R 1 = R 3 V H V REF – 1 – R 2 (EQ. 5) Example: For VH = 3.8V, VL = 2.7V (3.3V ± 0.5V) HYST 20k The resistors are shown as Equations 3, 4 and 5 as follows. Set: VBAT 2.4M The ISL21440 can be combined with a micropower comparator to produce a window comparator circuit. The circuit in Figure 28 uses a 3-resistor divider to produce high and low trip points and the ISL28197 (800nA supply current) comparator is added to give the second output. The two outputs can be used separately for overvoltage or undervoltage indication, or a gate can be added as shown to report either in-window or out-of window condition. V- GND R2 = 402k, R1 = 1.82M (can be 1%) The resulting circuit draws about 3µA and works down to VDD = 2.2V. V BAT FIGURE 27. LOW BATTERY DETECTOR WITH HYSTERESIS R1 V BAT OR V DD IN+ IN- R2 V+ + OUT V WINDOW HYST ISL21440 REF V- + R3 V LOW - V HI- GND ISL28197 FIGURE 28. WINDOW COMPARATOR CIRCUIT Submit Document Feedback 11 FN6532.3 March 17, 2016 ISL21440 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 03/03/16 FN6532.3 On pages 3 and page 4 in Electrical Spec table (Analog Specifications): Changed ICC Supply Current Max Limit across Temperature from: 0.85µA, to: 5µA. Updated typical performance curves Figures 3, 4, 9, 22, 23. Updated POD M8.118 to most current version with revision of POD as follows: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36" Updated POD L8.3x3G to most current version with revision of POD as follows: Tiebar Note updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). Updated Product to About Intersil 1/24/11 FN6532.2 On page 2: Updated Tape & Reel note in “Ordering Information” to add new standard "Add “-T*” suffix for tape and reel." The "*" covers all possible tape and reel options On page 4: Separated “Analog Specifications” tables into 2 tables. Put specs from "V+ = 3.0V, V- = GND = 0V" to end of table into separate table and added following common conditions: "V+= +3.0V. V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C." On page 4: Changed conditions for “VOH” from Io = -7mA to Io = -6mA Changed conditions for “VOL” from Io = 3mA to Io = 1.8mA 3/31/10 In “Window Comparator” on page 11, changed "with a micropower to.." to: "with a micropower comparator to.." Page 14, replaced POD M8.118 with newest revision. Updated to new intersil format by adding land pattern and moving dimensions from table onto drawing 3/2/10 FN6532.1 Updated datasheet with the TDFN spec. Spec added on pages 5-6 are: VOS, IIN, CMRR and PSRR. Each spec has an added row for the TDFN package and the original limit for the MSOP package. 12/7/09 FN6532.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Submit Document Feedback 12 FN6532.3 March 17, 2016 ISL21440 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 13 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. FN6532.3 March 17, 2016 ISL21440 Package Outline Drawing L8.3x3G 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) Rev 1, 5/15 PIN 1 INDEX AREA 3.00 B 1.45 A PIN 1 INDEX AREA 0.075 C 4X 6X 0.50 BSC 3.00 1.50 REF 1.75 8X 0.25 0.10 M C A B 8X 0.40 2.20 TOP VIEW BOTTOM VIEW (8X 0.60) (8X 0.25) SEE DETAIL X'' 0.10 C 0.75 C (1.75) SEATING PLANE 0.08 C (6X 0.50 BSC) SIDE VIEW (1.45) (2.20) TYPICAL RECOMMENDED LAND PATTERN c 0.20 REF 5 0~0.05 DETAIL “X” NOTES: 1. Controlling dimensions are in mm. Dimensions in ( ) for reference only. 2. Unless otherwise specified, tolerance: Decimal ±0.05 Angular ±2° 3. Dimensioning and tolerancing conform to JEDEC STD MO220-D. 4. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 14 FN6532.3 March 17, 2016