INTERSIL ISL21440

ISL21440
Features
The ISL21440 is a micropower, FGA™ reference and
comparator on a single chip. Drawing less than 1.8µA
supply current over the full operating temperature range,
the ISL21440 operates from a single 2V to 11V supply
and can also be used with split bipolar supplies.
The ISL21440’s on-board reference provides a 1.182V
±0.5% output. It features programmable hysteresis and
TTL/CMOS compatible outputs that sink and source
current. Low Bias currents permit high value divider
resistors for typical circuit current drains of <2.5µA.
The low supply current makes the ISL21440 ideal for
battery powered devices in battery level or low voltage
monitors circuits.
• 1.8µA Supply Current Over Full Temperature Range
• Wide Supply Range. . . . . . . . . . . . . . . 2V to 11V
• Precision 1.182V ±0.5% Voltage Reference
• Comparator with User Programmable Hysteresis
• Temperature Range . . . . . . . . . -40°C to +125°C
• 8 Ld MSOP and 8 Ld TDFN Packages
• Pin Compatible Upgrade to MAX921 and LTC1440
Applications*(see page 13)
• Low Battery Detector
• Low Voltage Reset
• Overvoltage Monitor
The ISL21440 is a pin-compatible, performance upgrade
of both the LTC1440, LTC1540, MAX921 and MAX931.
• Window Comparator
Typical Application
Reference Voltage vs
Temperature
Vdd
VBAT
1.190
+
-
IN1.8M
OUT
HYST
ISL21440
20k
REF
1.186
LoBAT-
1.184
VREF (V)
IN+
V+ = 3V
1.188
V+
2.4M
V+ = 5V
1.182
1.180
1.178
V+ = 2V
1.176
2.4M
V-
GND
1.174
1.172
-40
LOW BATTERY DETECTOR
March 2, 2010
FN6532.1
1
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL21440
Micropower Voltage Reference with Comparator
ISL21440
Block Diagram
V+
IN+
+
IN-
OUT
-
HYST
ISL21440
REF
V-
Pin Configuration
Pin Descriptions
ISL21440
(8 LD MSOP, 8 LD TDFN)
TOP VIEW
1
8
OUT
V-
2
7
V+
IN+
3
6
REF
IN-
4
5
HYST
GND
2
GND
PIN
SYMBOL
DESCRIPTION
1
GND
Ground pin. Sets the Comparator output
low level.
2
V-
3
IN+
Comparator non-inverting input pin.
Range: V- to V+ -1.5V.
4
IN-
Comparator inverting input pin. Range: Vto V+ -1.5V
5
HYST
Comparator Hysteresis input. Accepts a
voltage divided from the Reference
output. Range is VREF - 50mV to VREF.
Connect directly to VREF for zero
hysteresis.
6
REF
Reference output. Source 2mA and Sink
10µA.
7
V+
Positive Supply Input for Comparator and
Reference. Range is 2.0V to 11.0V
8
OUT
Comparator output, CMOS push-pull.
Output swing referenced to V+ and GND.
Negative Supply Input for Voltage
Reference and Comparator.
FN6532.1
March 2, 2010
ISL21440
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
ISL21440IUZ
VDD RANGE
(V)
TEMP RANGE
(°C)
2 to 11
-40 to +125
1440Z
PACKAGE
(Pb-free)
PKG.
DWG. #
8 Ld MSOP
M8.118
ISL21440IUZ-T13 (Note 1)
1440Z
2 to 11
-40 to +125
8 Ld MSOP
M8.118
ISL21440IRTZ
1440
2 to 11
-40 to +125
8 Ld TDFN
L8.3x3G
ISL21440IRTZ-T13 (Note 1)
1440
2 to 11
-40 to +125
8 Ld TDFN
L8.3x3G
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL21440. For more information on MSL please
see techbrief TB363.
3
FN6532.1
March 2, 2010
ISL21440
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . 5
Environmental Operating Conditions . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . 5
Electrical Specifications
..................5
Typical Performance Curves . . . . . . . . . . . . . . . 7
Functional Description
. . . . . . . . . . . . . . . . . . 11
Device Power . . . . . . . . . . . . . . . . . . . . . . . . 11
Comparator Section . . . . . . . . . . . . . . . . . . . . 11
Voltage Reference Section . . . . . . . . . . . . . . . 11
Applications Information
. . . . . . . . . . . . . . . . 11
Handling and Board Mounting . . . .
Hysteresis . . . . . . . . . . . . . . . . .
Board Assembly Considerations . . .
Special Applications Considerations
Typical Applications
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11
11
12
12
. . . . . . . . . . . . . . . . . . . . 12
Low Battery Detector . . . . . . . . . . . . . . . . . . . 12
Window Comparator . . . . . . . . . . . . . . . . . . . 12
Revision History . . . . . . . . . . . . . . . . . . . . . . . 13
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
M8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L8.3x3G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
FN6532.1
March 2, 2010
ISL21440
Absolute Maximum Ratings
Supply Voltage Range, V+ to GND . . . .
IN+, IN- with Respect to V- . . . . . . . .
GND with Respect to V-. . . . . . . . . . . .
V+ with Respect to V- . . . . . . . . . . . . .
REF, HYST with Respect to V-. . . . . . . .
Out with Respect to GND. . . . . . . . . . .
Voltage on All Other Pins . . . . . . . . . . .
ESD Rating
Human Body Model . . . . . . . . . . . . .
Machine Model . . . . . . . . . . . . . . . .
Charged Device Model . . . . . . . . . . .
Latch Up (Tested Per JESD-78B; Class1,
Thermal Information
. . . . . -0.5V to +12V
-0.3V to (V+) +0.3V
. . . . . 6.0V to -0.3V
. . . . . . 12V to -0.3V
. . . . . -0.3V to 1.5V
(V+) +0.3V to -0.3V
.-0.3V to VCC + 0.3V
Thermal Resistance (Typical)
.......
.......
.......
Level A) .
Recommended Operating Conditions
.
.
.
.
.
.
.
.
. 4000V
. . 350V
. 2000V
. 100mA
θJA (°C/W) θJC (°C/W)
8 Ld MSOP Package (Notes 5, 7). . . .
154
55
8 Ld TDFN Package (Notes 5, 6) . . . .
68
8
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile (Note 8) . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Temperature. . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Environmental Operating Conditions
X-Ray Exposure (Note 4). . . . . . . . . . . . . . . . . . . .10mRem
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. Measured with no filtering, distance of 10” from source, intensity set to 55kV and 70mA current, 30s duration. Other exposure
levels should be analyzed for Output Voltage drift effects. See “Applications Information” on page 11.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
8. Post-reflow drift for the ISL21440 device voltage reference output will range from 100mV to 1.0mV based on experimental
results with devices on FR4 double sided boards. The design engineer must take this into account when considering the
reference voltage after assembly.
Analog Specifications
SYMBOL
V+= +5.0V. V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 10) (Note 9) (Note 10) UNITS
POWER SUPPLY
V+
Supply Voltage Range
V- = GND
ICC
Supply Current
IN+ = IN- +80mV,
HYST = REF
2.0
0.46
11.0
V
0.75
µA
0.85
µA
±3
mV
±3.25
mV
±3.6
mV
±3.75
mV
COMPARATOR
VOS
Input Offset Voltage
VCM = 2.5V
MSOP Package
TDFN Package
IIN
VCM
CMRR
Input Leakage Current (IN+,
IN-, HYST)
VIN+ = VIN- = 2.5V MSOP Package
0.1
1.4
nA
TDFN Package
0.1
1.5
nA
3
nA
(V+) - 1.5
V
3
mV/V
3.5
mV/V
4.5
mV/V
5
mV/V
Common-Mode Input Range
Common-Mode Rejection Ratio V- to (V+ - 1.5V)
VMSOP Package
TDFN Package
5
1.2
1.2
FN6532.1
March 2, 2010
ISL21440
Analog Specifications
SYMBOL
PSRR
V+= +5.0V. V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
Power Supply Rejection Ratio
TEST CONDITIONS
V+ = 2V to 11V
MIN
TYP
MAX
(Note 10) (Note 9) (Note 10) UNITS
MSOP Package
0.25
TDFN Package
VHYST
tPHL
Hysteresis Input Voltage
REF 50mV
Propagation Delay - High to
Low Transition
CL = 100pF
Propagation Delay - Low to
High Transition
CL = 100pF
VOH
Output High Voltage
IO = -10mA
VOL
Output Low Voltage
IO = 3mA
tPLH
0.25
1.1
mV/V
1.2
mV/V
1.5
mV/V
1.6
mV/V
REF
V
Overdrive = 10mV
100
µs
Overdrive = 100mV
50
µs
Overdrive = 10mV
200
µs
Overdrive = 100mV
100
µs
(V+) - 0.4
V
GND +
0.4
V
1.188
V
-2.0
mV
-2.5
mV
2.0
mV
2.5
mV
0.7
µA
0.8
µA
±3.4
mV
±3.5
mV
±4.2
mV
±4.3
mV
1.1
nA
3
nA
(V+) - 1.5
V
5
mV/V
5.5
mV/V
7.5
mV/V
8
mV/V
1.1
mV/V
1.2
mV/V
1.5
mV/V
1.6
mV/V
REF
V
REFERENCE
VREF
ΔVREF
Reference Voltage
No Load
Output Load Regulation
0 ≤ ISOURCE ≤ 2mA
1.176
-0.5
0 ≤ ISINK ≤ 10µA
0.1
V+ = 3.0V, V- = GND = 0V
ICC
Supply Current
IN+ = IN- +80mV,
HYST =REF
0.40
COMPARATOR
VOS
Input offset Voltage
VCM = 1.5V
MSOP Package
±2.3
TDFN Package
IIN
VCM
CMRR
Input Leakage Current
(IN+, IN-, HYST)
±2.3
VIN+ = VIN- = 1.5V
0.1
Common-Mode Input Range
V-
Common-Mode Rejection Ratio V- to (V+ - 1.5V)
MSOP Package
1.2
TDFN Package
PSRR
Power Supply Rejection Ratio
V+ = 2V to 11V
1.2
MSOP Package
0.25
TDFN Package
VHYST
Hysteresis Input Voltage
6
0.25
REF 50mV
FN6532.1
March 2, 2010
ISL21440
Analog Specifications
SYMBOL
tPHL
V+= +5.0V. V- = GND = 0V unless otherwise specified, TA = +25°C. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
Propagation Delay - High to
Low Transition
CL = 100pF
Propagation Delay - Low to
High Transition
CL = 100pF
VOH
Output High Voltage
IO = -7mA
VOL
Output Low Voltage
IO = 3mA
tPLH
MIN
TYP
MAX
(Note 10) (Note 9) (Note 10) UNITS
TEST CONDITIONS
Overdrive = 10mV
100
µs
Overdrive = 100mV
50
µs
Overdrive = 10mV
200
µs
Overdrive = 100mV
100
µs
(V+) - 0.4
V
GND +
0.4
V
1.188
V
-2.0
mV
-2.5
mV
2.0
mV
-2.5
mV
REFERENCE
VREF
ΔVREF
Reference Voltage
No Load
1.176
Output Load Regulation
0 ≤ ISOURCE ≤ 2mA
-0.5
0 ≤ ISINK ≤ 10µA
0.1
NOTES:
9. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is
divided by the temperature range; in this case, -40°C to +125°C = +165°C.
10. Parts are 100% tested at +25°C and +85°C. The -40°C and +125°C temperature limits are established by characterization and
are not production tested.
Typical Performance Curves
0.49
1.2
V+ = 5V
0.48
1.0
0.46
IDD (µA)
IDD (µA)
0.47
0.45
0.44
V+ = 3V
0.43
0.42
0.6
0.4
0.2
0.41
0.40
-40
0.8
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 1. IDD vs TEMPERATURE
7
100
120
0
2
3
4
5
6
7
8
9
10
11
VDD (V)
FIGURE 2. IDD vs VDD
FN6532.1
March 2, 2010
ISL21440
Typical Performance Curves
1.190
(Continued)
1.190
V+ = 3V
1.188
1.188
1.186
1.186
V+ = 5V
1.184
VREF (V)
VREF (V)
1.184
1.182
1.180
1.178
1.182
1.180
1.178
V+ = 2V
1.176
1.176
1.174
1.174
1.172
-40
-20
0
20
40
60
80
100
1.172
2
120
3
4
5
TEMPERATURE (°C)
1.183
9
10
11
12
1.188
1.182
V+ = 5V
1.187
1.181
V+ = 3V
1.186
1.180
VREF (V)
VREF (V)
7
8
VDD (V)
FIGURE 4. VREF vs SUPPLY VOLTAGE
FIGURE 3. VREF vs TEMPERATURE
1.179
1.178
1.177
1.185
1.184
V+ = 2V
1.183
1.176
1.175
0
0.5
1.0
1.5
2.0
2.5
3.0
1.182
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
LOAD (mA)
LOAD (mA)
FIGURE 5. VREF vs LOAD (SOURCE)
FIGURE 6. VREF vs LOAD (SINK)
1.30
3.0
NO
LOAD
10mA
LOAD
1.25
2.5
100mA
LOAD
OUTPUT (V)
1.20
VREF (V)
6
1.15
1.10
1.05
2.0
V+ = 3V
1.5
V+ = 5V
V+ = 2V
V+ = 11V
1.0
0.5
1.00
1.00 1.25
1.50 1.75
2.00 2.25
VDD (V)
2.50
2.75
FIGURE 7. DROPOUT - VREF OUTPUT
8
3.00
0
0
2
4
6
8
ILOAD (mA)
10
12
14
FIGURE 8. COMPARATOR OUTPUT LOW VOLTAGE vs
LOAD
FN6532.1
March 2, 2010
ISL21440
Typical Performance Curves
(Continued)
12
6
10
5
V+ = 11V
OUTPUT (V)
OUTPUT (V)
8
V+ = 5V
6
4
V+ = 3V
2
4
3
2
1
V+ = 2V
0
0
5
10
15
20 25 30
ILOAD (mA)
35
40
45
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
50
FIGURE 10. HYSTERESIS - 0mV (V+ = 5V)
6
6
5
5
4
4
OUTPUT (V)
OUTPUT (V)
FIGURE 9. COMPARATOR OUTPUT HIGH VOLTAGE vs
LOAD
3
2
3
2
1
1
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
IN+ - IN- (mV)
FIGURE 12. HYSTERESIS - 25mV (V+ = 5V)
6
6
5
5
4
4
OUTPUT (V)
OUTPUT (V)
FIGURE 11. HYSTERESIS - 12.5mV (V+ = 5V)
3
2
3
2
1
1
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
FIGURE 13. HYSTERESIS - 37.5mV (V+ = 5V)
9
FIGURE 14. HYSTERESIS - 50mV (V+ = 5V)
FN6532.1
March 2, 2010
ISL21440
(Continued)
3.5
3.5
3.0
3.0
2.5
2.5
OUTPUT (V)
OUTPUT (V)
Typical Performance Curves
2.0
1.5
1.0
0.5
0.5
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
FIGURE 15. HYSTERESIS - 0mV (V+ = 3V)
FIGURE 16. HYSTERESIS - 12.5mV (V+ = 3V)
3.5
3.5
3.0
3.0
2.5
2.5
OUTPUT (V)
OUTPUT (V)
1.5
1.0
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
FIGURE 18. HYSTERESIS - 37.5mV (V+ = 3V)
FIGURE 17. HYSTERESIS - 25mV (V+ = 3V)
3.5
90
3.0
80
2.5
70
TIME (µs)
OUTPUT (V)
2.0
2.0
1.5
60
50
1.0
40
0.5
30
0
-60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60
IN+ - IN- (mV)
FIGURE 19. HYSTERESIS - 50mV (V+=3V)
10
3V
20
10
5V
20
30
40 50 60 70 80 90
INPUT VOLTAGE (mV)
100 110 120
FIGURE 20. OUTPUT RESPONSE TIME vs INPUT
OVERDRIVE (tPHL)
FN6532.1
March 2, 2010
ISL21440
Typical Performance Curves
(Continued)
270
5.5
245
5.0
220
4.5
4.0
170
OUTPUT (V)
TIME (µs)
195
3V
145
120
95
20
10
3.0
2.5
OUT
2.0
V+
1.5
1.0
70
45
3.5
0.5
5V
20
0
30
40
50
60
70
80
90
-0.5
0
100 110 120
INPUT VOLTAGE (mV)
0.2
0.4
0.6
0.8
1.0 1.2
1.4
1.6
1.8
2.0
TIME (ms)
FIGURE 21. OUTPUT RESPONSE TIME vs INPUT
OVERDRIVE (tPLH)
FIGURE 22. POWER-UP/DOWN OUTPUT RESPONSE
(V+ = 5V, IN+ = V+, IN- = VREF)
3.5
3.0
OUTPUT (V)
2.5
2.0
OUT
1.5
V+
1.0
0.5
0
-0.5
0
0.2
0.4
0.6
0.8
1.0 1.2
1.4
1.6
1.8
2.0
TIME (ms)
FIGURE 23. POWER-UP/DOWN OUTPUT RESPONSE (V+ = 3V, IN+ = V+, IN- = VREF)
Functional Description
Device Power
The ISL21440 device has a single positive supply pin, V+,
and two other supply pins, V- and GND. Normally for
single supply applications the V- pin is tied to system
ground as well as the GND pin. The separate ground pin
allows the comparator to be powered by split supplies
from ±1.0V to ±5.5V. Note that the minimum supply
voltage will be 0.8V above the comparator maximum
input level for accurate operation.
Comparator Section
The comparator inputs can swing from the negative
supply (GND pin) to within 0.8V of the positive supply
(V+). Alternatively, with the comparator input set at
the 1.182V reference level, the minimum input voltage
for accurate operation is 2.0V. If the inputs are
expected to see voltage levels above V+ or below
ground, they should be clamped with low leakage
Schottky diodes.
11
The CMOS output swings essentially from the GND
potential to V+ potential, depending on load current. If
loads in excess of 1mA are expected, then a 0.1µF
decoupling capacitor at the V+ pin should be added.
Voltage Reference Section
The voltage reference is a micropower FGA reference
and is set to 1.182V ±0.5% at the factory. The
reference output can source up to 2mA but the sink
capability is very limited at only 10µA, maximum.
Small value capacitors, up to 10nF, can be used on the
reference output to lower noise if desired.
Applications Information
Handling and Board Mounting
FGA references provide excellent initial accuracy and
low temperature drift at the expense of very little
power drain. There are some precautions to take to
insure this accuracy is not compromised. Excessive
heat during solder reflow can cause excessive initial
accuracy drift, so the recommended +260°C max
FN6532.1
March 2, 2010
ISL21440
temperature profile should not be exceeded. Expect up
to 1mV drift from the solder reflow process.
FGA references are susceptible to excessive
X-radiation like that used in PC board manufacturing.
Initial accuracy can change 10mV or more under
extreme radiation. If an assembled board needs to be
X-rayed, care should be taken to shield the FGA
reference device.
Hysteresis
The Hysteresis function allows for changing the value of
the reference switchover point depending on the
previouse state of the comparator. This works to remove
the effects of noise or glitches in the voltage detection
input and provide more reliable output transitions.
Hysteresis is added to the ISL21440 by connecting one
resistor between the REF and HYST pins (RREF), and
another resistor(RHYST) between the HYST pin and
ground. The hysteresis voltage (VH) is designed to be
twice the voltage difference between the HYST pin and
REF pin (VH = 2 * (VREF - VHYST)). Since the reference
voltage is 1.182V (VREF), Equations 1 and 2 for these
two resistors are shown as follows:
R REF = V H ⁄ ( 2∗ I REF ) = ( V REF – V HYST ) ⁄ I REF
(EQ. 1)
R HYST = ( 1.182 – V H ⁄ 2 ) ⁄ I REF = V HYST ⁄ I REF
(EQ. 2)
IREF is chosen to be less than the maximum output of
the reference, usually 5µA is a safe value but for
lowest power, 0.1µA can be used.
If the hysteresis is not used, the HYST pin should be
tied to the REF pin.
Board Assembly Considerations
FGA references provide high accuracy and low
temperature drift but some PC board assembly
precautions are necessary. Normal Output voltage shifts of
100µV to 1mV can be expected with Pb-free reflow
profiles or wave solder on multi-layer FR4 PC boards.
Precautions should be taken to avoid excessive heat or
extended exposure to high reflow or wave solder
temperatures, this may reduce device initial accuracy.
Post-assembly X-ray inspection may also lead to
permanent changes in device output voltage and
should be minimized or avoided. If X-ray inspection is
required, it is advisable to monitor the reference
output voltage to verify excessive shift has not
occurred. If large amounts of shift are observed, it is
best to add an X-ray shield consisting of thin zinc
(300µm) sheeting to allow clear imaging, yet block xray energy that affects the FGA reference.
12
Special Applications Considerations
In addition to post-assembly examination, there are
also other X-ray sources that may affect the FGA
reference long term accuracy. Airport screening
machines contain X-rays and will have a cumulative
effect on the voltage reference output accuracy.
Carry-on luggage screening uses low level X-rays and
is not a major source of output voltage shift, although
if a product is expected to pass through that type of
screening over 100x it may need to consider shielding
with copper or aluminum. Checked luggage X-rays are
higher intensity and can cause output voltage shift in
much fewer passes, so devices expected to go through
those machines should definitely consider shielding.
Note that just two layers of 1/2 ounce copper planes
will reduce the received dose by over 90%. The lead
frame for the device which is on the bottom also
provides similar shielding.
If a device is expected to pass through luggage X-ray
machines numerous times, it is advised to mount a
2-layer (minimum) PC board over the top of the
package, which along with a ground plane underneath
will effectively shield it from 50 to 100 passes through
the machine. Since these machines vary in X-ray dose
delivered, it is difficult to produce an accurate
maximum pass recommendation.
Typical Applications
Low Battery Detector
Figure 24 shows a typical implementation for the
ISL21440, a low battery detector. The values for RREF
and RHYST provide 20mV of hysteresis and 0.5µA IREF.
The input trip point for Vdetect is the same as the
reference voltage, 1.182V, and a resistor divider at the
input sets the LoBAT trip point at 2.7V. The total
current draw for the circuit is going to be 1.1µA for
VDD and 0.6µA for VBAT.
VDD
VBAT
2.4M
V+
IN+
IN-
1.8M
20k
2.4M
+
OUT
LoBAT-
-
HYST
REF
ISL21440
V-
GND
FIGURE 24. LOW BATTERY DETECTOR WITH
HYSTERESIS
FN6532.1
March 2, 2010
ISL21440
Window Comparator
The ISL21440 can be combined with a micropower to
produce a window comparator circuit. The circuit in
Figure 25 uses a 3 resistor divider to produce high and
low trip points, and the ISL28197 (800nA supply current)
comparator is added to give the second output. The two
outputs can be used separately for over or undervoltage
indication, or a gate can be added as shown to report
either in-window or out-of window condition.
The resulting circuit draws about 3µA and works down to
VDD = 2.2V.
V BAT
R1
V BAT OR V DD
IN+
IN-
R2
V+
+
-
OUT
V WINDOW
HYST
REF
The resistors are shown as Equations 3, 4 and 5 as
follows.
V LOW -
ISL21440
V HI -
V- GND
Set:
R 3 = 1M ( 1% )
(EQ. 3)
R2 = R3 [ VH ⁄ VL – 1 ]
(EQ. 4)
R 1 = R 3 ( [ V H ⁄ V REF – 1 ] – R 2 )
(EQ. 5)
Example: For VH = 3.8V, VL = 2.7V (3.3V ± 0.5V)
+
R3
ISL28197
FIGURE 25. WINDOW COMPARATOR CIRCUIT
R2 = 402k, R1 = 1.82M (can be 1%)
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
3/2/10
FN6532.1
Updated datasheet with the TDFN spec.
Spec added on pages 5-6 are: VOS, IIN, CMRR and PSRR. Each spec has an added row for the
TDFN package and the original limit for the MSOP package.
12/7/09
FN6532.0
Initial Release
Products
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL21440
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FITs are available from our website at http://rel.intersil.com/reports/search.php
13
FN6532.1
March 2, 2010
ISL21440
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L
SEATING
PLANE
C
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
e
L1
0.026 BSC
0.20 (0.008)
C
C
a
CL
E1
0.20 (0.008)
C D
-B-
-
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
SIDE VIEW
0.65 BSC
E
L1
-A-
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
14
FN6532.1
March 2, 2010
ISL21440
Package Outline Drawing
L8.3x3G
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 0, 5/07
PIN 1 INDEX AREA
3.00
1.45
A
PIN 1 INDEX AREA
B
0.075 C
4X
6X 0.50 BSC
3.00
1.50
REF
1.75
8X 0.25
0.10 M C A B
8X 0.40
2.20
TOP VIEW
BOTTOM VIEW
SEE DETAIL X''
(8X 0.60)
(8X 0.25)
0.10 C
0.75
C
(1.75)
SEATING PLANE
0.08 C
(6X 0.50 BSC)
SIDE VIEW
(1.45)
(2.20)
TYPICAL RECOMMENDED LAND PATTERN
c
0.20 REF
5
0~0.05
DETAIL “X”
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to JEDEC STD MO220-D.
4. The configuration of the pin #1 identifier is optional, but must be located
within the zone indicated. The pin #1 identifier may be either a mold or
mark feature.
5. Tiebar shown (if present) is a non-functional feature.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
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15
FN6532.1
March 2, 2010