CT O D U EM EN T R P TE AC O LE E PL O B S N D ED R E 515 OM M Data Sheet HC5 R EC ® LSSGR/TR57 CO/Loop Carrier SLIC with Low Power Standby FN4144.6 • DI Monolithic High Voltage Process The HC5523 is fabricated in a High Voltage Dielectrically Isolated (DI) Bipolar Process that eliminates leakage currents and device latch-up problems normally associated with junction isolated ICs. The elimination of the leakage currents results in improved circuit performance for wide temperature extremes. The latch free benefit of the DI process guarantees operation under adverse transient conditions. This process feature makes the HC5523 ideally suited for use in harsh outdoor environments. Part Number Information PART NUMBER August 2003 Features The HC5523 is a subscriber line interface circuit which is interchangeable with Ericsson’s PBL3764A/4 for distributed central office applications. Enhancements include immunity to circuit latch-up during hot plug and absence of false signaling in the presence of longitudinal currents. TEMP. RANGE (oC) HC5523 • Programmable Current Feed (20mA to 60mA) • Programmable Loop Current Detector Threshold and Battery Feed Characteristics • Ground Key and Ring Trip Detection • Compatible with Ericsson’s PBL3764A/4 • Thermal Shutdown • On-Hook Transmission • Wide Battery Voltage Range (-24V to -58V) • Low Standby Power • Meets TR-NWT-000057 Transmission Requirements • -40oC to 85oC Ambient Temperature Range Applications PKG. DWG. # PACKAGE • Digital Loop Carrier Systems • Pair Gain HC5523IM -40 to 85 28 Ld PLCC N28.45 • Fiber-In-The-Loop ONUs • POTS HC5523IP -40 to 85 22 Ld PDIP E22.4 • Wireless Local Loop • PABX • Hybrid Fiber Coax • Related Literature - AN9632, Operation of the HC5523/15 Evaluation Board Block Diagram RINGRLY DT DR RING RELAY DRIVER 4-WIRE INTERFACE VF SIGNAL PATH RING TRIP DETECTOR VTX RSN TIP RING HPT 2-WIRE INTERFACE LOOP CURRENT DETECTOR E0 E1 HPR GROUND KEY DETECTOR DIGITAL MULTIPLEXER C1 C2 VBAT VCC VEE BIAS DET AGND RD RDC BGND RSG 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. HC5523 Absolute Maximum Ratings Thermal Information Temperature, Humidity Storage Temperature Range . . . . . . . . . . . . . . . . -65oC to 150oC Operating Temperature Range . . . . . . . . . . . . . . -40oC to 110oC Operating Junction Temperature Range . . . . . . . -40oC to 150oC Power Supply (-40oC ≤ TA ≤ 85oC) Supply Voltage VCC to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V Supply Voltage VEE to GND . . . . . . . . . . . . . . . . . . . . -7V to 0.5V Supply Voltage VBAT to GND . . . . . . . . . . . . . . . . . . -80V to 0.5V Ground Voltage between AGND and BGND. . . . . . . . . . . . . -0.3V to 0.3V Relay Driver Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 20V Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Ring Trip Comparator Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT to 0V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA Digital Inputs, Outputs (C1, C2, E0, E1, DET) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to VCC Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . .0V to VCC Output Current (DET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Tipx and Ringx Terminals (-40oC ≤ TA ≤ +85oC) Tipx or Ringx Voltage, Continuous (Referenced to GND) . . . VBAT to +2V Tipx or Ringx, Pulse < 10ms, TREP > 10s . . . . VBAT -20V to +5V Tipx or Ringx, Pulse < 10µs, TREP > 10s . . . VBAT -40V to +10V Tipx or Ringx, Pulse < 250ns, TREP > 10s . . VBAT -70V to +15V Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V Thermal Resistance (Typical, Note 1) θJA (oC/W) 22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . 53 28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . 53 Continuous Power Dissipation at 70oC 22 Lead PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W 28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W Package Power Dissipation at 70oC, t < 100ms, tREP > 1s 22 Lead PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W 28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W Derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70oC Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/oC PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/oC Maximum Junction Temperature Range . . . . . . . . . -40oC to 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .300oC (Soldering 10s, PLCC Lead Tips Only) Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Typical Operating Conditions These represent the conditions under which the part was developed and are suggested as guidelines. PARAMETER CONDITIONS Case Temperature -40oC to 85oC -40oC to 85oC -40oC to 85oC VCC with Respect to AGND VEE with Respect to AGND VBAT with Respect to BGND MIN TYP MAX UNITS -40 - 100 oC 4.75 - 5.25 V -5.25 - -4.75 V -58 - -24 V TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin Electrical Specifications number references in the figures refer to the 28 lead PLCC package. PARAMETER CONDITIONS Overload Level 1% THD, ZL = 600Ω, (Note 2, Figure 1) Longitudinal Impedance (Tip/Ring) 0 < f < 100Hz (Note 3, Figure 2) 2 MIN TYP MAX UNITS 3.1 - - VPEAK - 20 35 Ω/Wire HC5523 TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) Electrical Specifications PARAMETER CONDITIONS RL 600Ω 0 < f < 100Hz EL C RT 600kΩ VTRO TYP AT TIP 27 1VRMS VTX 19 TIP 27 MIN VT 300Ω RING 28 RSN 16 VTX 19 2.16µF ERX RRX UNITS RT 600kΩ 300Ω IDCMET 23mA MAX VR AR RRX RING 28 RSN 16 300kΩ 300kΩ LZT = VT/AT FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT) LZR = VR/AR FIGURE 2. LONGITUDINAL IMPEDANCE LONGITUDINAL CURRENT LIMIT (TIP/RING) Off-Hook (Active) No False Detections, (Loop Current), LB > 45dB (Note 4, Figure 3A) 27 - - mAPEAK/ Wire On-Hook (Standby), RL = ∞ No False Detections (Loop Current) (Note 5, Figure 3B) 8.5 - - mAPEAK/ Wire 368Ω 368Ω A TIP 27 RSN 16 A 39kΩ C EL RDC1 41.2kΩ RD -5V 2.16µF RDC2 A 368Ω RING RDC 14 41.2kΩ 28 DET CDC 2.16µF EL C 2.16µF C TIP 27 RSN 16 39kΩ RD RDC1 41.2kΩ RDC2 RDC RING 14 41.2kΩ 28 DET CDC -5V A 1.5µF 368Ω FIGURE 3A. OFF-HOOK 1.5µF FIGURE 3B. ON-HOOK FIGURE 3. LONGITUDINAL CURRENT LIMIT OFF-HOOK LONGITUDINAL BALANCE Longitudinal to Metallic IEEE 455 - 1985, RLR, RLT = 368Ω 0.2kHz < f < 4.0kHz (Note 6, Figure 4) 58 70 - dB Longitudinal to Metallic RLR, RLT = 300Ω, 0.2kHz < f < 4.0kHz (Note 6, Figure 4) 58 70 - dB Metallic to Longitudinal FCC Part 68, Para 68.310 0.2kHz < f < 1.0kHz 50 55 - dB 1.0kHz < f < 4.0kHz (Note 7) 50 55 - dB Longitudinal to 4-Wire 0.2kHz < f < 4.0kHz (Note 8, Figure 4) 58 70 - dB Metallic to Longitudinal RLR, RLT = 300Ω, 0.2kHz < f < 4.0kHz (Note 9, Figure 5) 50 55 - dB 4-Wire to Longitudinal 0.2kHz < f < 4.0kHz (Note 10, Figure 5) 50 55 - dB 3 HC5523 TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) Electrical Specifications PARAMETER CONDITIONS MIN TIP 27 VTX 19 C UNITS 2.16µF RRX RING 28 RSN 16 4 RT 600kΩ ETR C VL RRX RLR RING 28 300Ω 300kΩ FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BALANCE 2-Wire Return Loss CHP = 20nF 2.16µF VTX VTX 19 TIP 27 300Ω RT 600kΩ VTR RLR MAX RLT RLT EL TYP RSN 16 ERX 300kΩ FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL BALANCE 0.2kHz to 0.5kHz (Note 11, Figure 6) 25 - - dB 0.5kHz to 1.0kHz (Note 11, Figure 6) 27 - - dB 1.0kHz to 3.4kHz (Note 11, Figure 6) 23 - - dB HC5523 TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) Electrical Specifications PARAMETER CONDITIONS MIN TYP MAX UNITS Active, IL = 0 - -4 - V Standby, IL = 0 - <0 - V Active, IL = 0 - -44 - V Standby, IL = 0 - >-48 - V 43 - 47 V TIP IDLE VOLTAGE RING IDLE VOLTAGE TIP-RING Open Loop Metallic Voltage, VTR VBAT = -52V, RSG = 0Ω 4-WIRE TRANSMIT PORT (VTX) Overload Level (ZL > 20kΩ, 1% THD) (Note 12, Figure 7) 3.1 - - VPEAK Output Offset Voltage EG = 0, ZL = ∞ (Note 13, Figure 7) -60 - 60 mV Output Impedance (Guaranteed by Design) 0.2kHz < f < 03.4kHz - 5 20 W 2- to 4-Wire (Metallic to VTX) Voltage Gain 0.3kHz < f < 03.4kHz (Note 14, Figure 7) 0.98 1.0 1.02 V/V 2.16µF ZD TIP 27 R VTX 19 RL 600Ω VM RT 600kΩ VS R EG ZIN RLR TIP 27 C VTX 19 VTR RT 600kΩ IDCMET 23mA RSN 16 RING 28 300kΩ FIGURE 6. TWO-WIRE RETURN LOSS ZL RRX RRX RING 28 VTXO VTX RSN 16 300kΩ FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE VOLTAGE GAIN AND HARMONIC DISTORTION 4-WIRE RECEIVE PORT (RSN) DC Voltage IRSN = 0mA - 0 - V RX Sum Node Impedance (Gtd by Design) 0.2kHz < f < 3.4kHz - - 20 W Current Gain-RSN to Metallic 0.3kHz < f < 3.4kHz (Note 15, Figure 8) 980 1000 1020 Ratio 2-Wire to 4-Wire 0dBm at 1.0kHz, ERX = 0V 0.3kHz < f < 3.4kHz (Note 16, Figure 9) -0.2 - 0.2 dB 4-Wire to 2-Wire 0dBm at 1.0kHz, EG = 0V 0.3kHz < f < 3.4kHz (Note 17, Figure 9) -0.2 - 0.2 dB 4-Wire to 4-Wire 0dBm at 1.0kHz, EG = 0V 0.3kHz < f < 3.4kHz (Note 18, Figure 9) -0.2 - 0.2 dB 2-Wire to 4-Wire 0dBm, 1kHz (Note 19, Figure 9) -0.2 - 0.2 dB 4-Wire to 2-Wire 0dBm, 1kHz (Note 20, Figure 9) -0.2 - 0.2 dB 2-Wire to 4-Wire +3dBm to +7dBm (Note 21, Figure 9) -0.15 - 0.15 dB 2-Wire to 4-Wire -40dBm to +3dBm (Note 21, Figure 9) -0.1 - 0.1 dB 2-Wire to 4-Wire -55dBm to -40dBm (Note 21, Figure 9) -0.2 - 0.2 dB 4-Wire to 2-Wire -40dBm to +7dBm (Note 22, Figure 9) -0.1 - 0.1 dB 4-Wire to 2-Wire -55dBm to -40dBm (Note 22, Figure 9) -0.2 - 0.2 dB FREQUENCY RESPONSE (OFF-HOOK) INSERTION LOSS GAIN TRACKING (Ref = -10dBm, at 1.0kHz) 5 HC5523 TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) Electrical Specifications PARAMETER CONDITIONS MIN TYP MAX UNITS GRX = ((VTR1- VTR2)(300k))/(-3)(600) Where: VTR1 is the Tip to Ring Voltage with VRSN = 0V and VTR2 is the Tip to Ring Voltage with VRSN = -3V V RSN = 0V RRX TIP 27 RL 600Ω RSN 16 C VRSN = -3V RDC1 41.2kΩ VTR TIP 27 RL 600Ω 300kΩ IDCMET VTX 19 RT 600kΩ VTR EG RING 28 RDC 14 RDC2 CDC 41.2kΩ 1.5µF RRX 1/ωC < RL FIGURE 8. CURRENT GAIN-RSN TO METALLIC RING 28 RSN 16 VTX ERX 300kΩ FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING AND HARMONIC DISTORTION NOISE Idle Channel Noise at 2-Wire C-Message Weighting (Note 23, Figure 10) - 8.5 - dBrnC Psophometrical Weighting (Note 23, Figure 10) - -81.5 - dBrnp C-Message Weighting (Note 24, Figure 10) - 8.5 - dBrnC Psophometrical Weighting (Note 23, Figure 10) - -81.5 - dBrnp 2-Wire to 4-Wire 0dBm, 1kHz (Note 25, Figure 7) - -65 -54 dB 4-Wire to 2-Wire 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9) - -65 -54 dB Idle Channel Noise at 4-Wire HARMONIC DISTORTION BATTERY FEED CHARACTERISTICS Constant Loop Current Tolerance RDCX = 41.2kΩ IL = 2500/(RDC1 + RDC2), -40oC to 85oC (Note 27) 0.92IL IL 1.08IL mA Loop Current Tolerance (Standby) IL = (VBAT-3)/(RL +1800), -40oC to 85oC (Note 28) 0.8IL IL 1.2IL mA Open Circuit Voltage (VTIP - VRING) -40oC to 85oC, (Active) RSG = ∞ 14 16.67 20 V LOOP CURRENT DETECTOR On-Hook to Off-Hook RD = 39kΩ, -40oC to 85oC 372/RD 465/RD 558/RD mA Off-Hook to On-Hook RD = 39kΩ, -40oC to 85oC RD = 39kΩ, -40oC to 85oC 325/RD 405/RD 485/RD mA 25/RD 60/RD 95/RD mA Loop Current Hysteresis GROUND KEY DETECTOR Tip/Ring Current Difference - Trigger (Note 29, Figure 11) 8 12 17 mA Tip/Ring Current Difference - Reset (Note 29, Figure 11) 3 7 12 mA Hysteresis (Note 29, Figure 11) 0 5 9 mA 6 HC5523 TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) Electrical Specifications PARAMETER CONDITIONS TIP 27 RL 600Ω TIP 27 VTX 19 RT 600kΩ VTR MIN TYP MAX RSN 16 RDC1 41.2kΩ VTX CDC RDC2 RRX RING 28 RSN 16 UNITS RING RDC 28 DET 14 41.2kΩ 1.5µF 300kΩ E1 = C1 = 0, C2 = 1 FIGURE 10. IDLE CHANNEL NOISE FIGURE 11. GROUND KEY DETECT RING TRIP DETECTOR (DT, DR) Offset Voltage Source Res = 0 -20 - 20 mV Input Bias Current Input Common-Mode Range Source Res = 0 -360 - 360 nA Source Res = 0 VBAT +1 - 0 V Input Resistance Source Res = 0, Unbalanced 1 - - MΩ Source Res = 0, Balanced 3 - - MΩ VSAT at 25mA IOL = 25mA - 0.2 0.6 V Off-State Leakage Current VOH = 12V - - 10 µA Input Low Voltage, VIL 0 - 0.8 V Input High Voltage, VIH 2 - VCC V VIL = 0.4V -200 - - µA Input Low Current, IIL: E0, E1 VIL = 0.4V -100 - - µA Input High Current VIH = 2.4V - - 40 µA Output Low Voltage, VOL IOL = 2mA - - 0.45 V Output High Voltage, VOH IOH = 100µA 2.7 - - V 10 15 20 kΩ 41 mW RING RELAY DRIVER DIGITAL INPUTS (E0, E1, C1, C2) Input Low Current, IIL: C1, C2 DETECTOR OUTPUT (DET) Internal Pull-Up Resistor POWER DISSIPATION (VBAT = -48V) Open Circuit State C1 = C2 = 0 - 26.3 On-Hook, Standby C1 = C2 = 1 - 37.5 57 mW On-Hook, Active C1 = 0, C2 = 1, RL = High Impedance - 110 216 mW Off-Hook, Active C1 = 0, C2 = 1, RL = 600Ω - 1.1 1.4 W 150 - 180 οC ICC - 1.3 2.0 mA IEE - 0.6 0.9 mA TEMPERATURE GUARD Thermal Shutdown SUPPLY CURRENTS (VBAT = -28V) Open Circuit State (C1, 2 = 0, 0) On-Hook Standby State (C1, 2 = 1, 1) On-Hook 7 IBAT - 0.35 0.55 mA ICC - 1.6 2.25 mA IEE - 0.62 0.9 mA IBAT - 0.55 0.85 mA HC5523 TA = -40oC to 85oC, VCC = +5V ±5%, VEE = -5V ±5%, VBAT = -48V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2kΩ, RD = 39kΩ, RSG = 0Ω, RF1 = RF2 = 0Ω, CHP = 10nF, CDC = 1.5µF, ZL = 600Ω, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) Electrical Specifications PARAMETER CONDITIONS Active State (C1, 2 = 0, 1) On-Hook MIN TYP MAX UNITS ICC - 3.7 5.8 mA IEE - 1.1 1.8 mA IBAT - 2.2 3.7 mA VCC to 2 or 4-Wire Port (Note 30, Figure 12) - 40 - dB VEE to 2 or 4-Wire Port (Note 30, Figure 12) - 40 - dB VBAT to 2 or 4-Wire Port (Note 30, Figure 12) - 40 - dB PSRR -48V SUPPLY +5V SUPPLY -5V SUPPLY 100mVRMS, 50Hz TO 4kHz TIP 27 VTX 19 PSRR = 20 log (VT X/VIN) RT 600kΩ RL 600Ω VTX RRX RING 28 RSN 16 300kΩ FIGURE 12. POWER SUPPLY REJECTION RATIO Circuit Operation and Design Information The HC5523 is a current feed voltage sense Subscriber Line Interface Circuit (SLIC). This means that for short loop applications the SLIC provides a programed constant current to the tip and ring terminals while sensing the tip to ring voltage. The following discussion separates the SLIC’s operation into its DC and AC paths, then follows up with additional circuit and design information. Constant Loop Current (DC) Path SLIC in the Active Mode The DC path establishes a constant loop current that flows out of tip and into the ring terminal. The loop current is programmed by resistors RDC1, RDC2 and the voltage on the RDC pin (Figure 13). The RDC voltage is determined by the voltage across R1 in the saturation guard circuit. Under constant current feed conditions, the voltage drop across R1 sets the RDC voltage to -2.5V. This occurs when current flows through R1 into the current source I2. The RDC voltage establishes a current (IRSN) that is equal to VRDC/(RDC1 +RDC2). This current is then multiplied by 1000, in the loop current circuit, to become the tip and ring loop currents. For the purpose of the following discussion, the saturation guard voltage is defined as the maximum tip to ring voltage at which the SLIC can provide a constant current for a given battery and overhead voltage. 8 For loop resistances that result in a tip to ring voltage less than the saturation guard voltage the loop current is defined as: 2.5V I L = -------------------------------------- × 1000 R DC1 + R DC2 (EQ. 1) where: IL = Constant loop current. RDC1 and RDC2 = Loop current programming resistors. Capacitor CDC between RDC1 and RDC2 removes the VF signals from the battery feed control loop. The value of CDC is determined by Equation 2: 1 1 C DC = T × --------------- + --------------- R R DC1 (EQ. 2) DC2 where T = 30ms NOTE: The minimum CDC value is obtained if RDC1 = RDC2 Figure 14 illustrates the relationship between the tip to ring voltage and the loop resistance. For a 0Ω loop resistance both tip and ring are at VBAT/2. As the loop resistance increases, so does the voltage differential between tip and ring. When this differential voltage becomes equal to the saturation guard voltage, the operation of the SLIC’s loop feed changes from a constant current feed to a resistive feed. The loop current in the resistive feed region is no longer constant but varies as a function of the loop resistance. HC5523 VTX ITIP + - IRSN LOOP CURRENT CIRCUIT TIP RRX RSN RDC1 ITIP IRING RING IRING RDC2 RDC SATURATION GUARD CIRCUIT + R1 + I2 I1 HC5523 -2.5V + A2 A1 -5V CDC 17.3kΩ RSG -5V RSG -5V FIGURE 13. DC LOOP CURRENT VBAT = -48V, IL = 23mA, RSG = 4.0kΩ VTIP SATURATION 0 TIP TO RING VOLTAGE (V) GUARD VOLTAGE -10 CONSTANT CURRENT FEED REGION RESISTIVE FEED REGION -20 -30 -40 SATURATION GUARD VOLTAGE -50 0 VRING ∞ 1.2K LOOP RESISTANCE (Ω) FIGURE 14. VTR vs RL Figure 15 shows the relationship between the saturation guard voltage, the loop current and the loop resistance. Notice from Figure 15 that for a loop resistance <1.2kΩ (RSG = 4.0kΩ) the SLIC is operating in the constant current feed region and for resistances >1.2kΩ the SLIC is operating in the resistive feed region. Operation in the resistive feed region allows long loop and off-hook transmission by keeping the tip and ring voltages off the rails. Operation in this region is transparent to the customer. TIP TO RING VOLTAGE (V) 50 CONSTANT CURRENT FEED REGION VBAT = -48V, RSG = 4.0kΩ 40 SATURATION GUARD VOLTAGE, VTR = 38V 30 VBAT = -24V, RSG = ∞ 20 10 0 10 5 5 • 10 V SGREF = 12.5 + ----------------------------------R SG + 17300 (EQ. 3) where: VSGREF = Saturation Guard reference voltage. RSG = Saturation Guard programming resistor. When the Saturation guard reference voltage is exceeded, the tip to ring voltage is calculated using Equation 4: 5 16.66 + 5 • 10 ⁄ ( R SG + 17300 ) V TR = R L × -----------------------------------------------------------------------------------+R ) ⁄ 600 R + (R L DC1 (EQ. 4) DC2 where: SATURATION GUARD VOLTAGE, VTR = 13V RESISTIVE FEED REGION 0 The Saturation Guard circuit (Figure 13) monitors the tip to ring voltage via the transconductance amplifier A1. A1 generates a current that is proportional to the tip to ring voltage difference. I1 is internally set to sink all of A1’s current until the tip to ring voltage exceeds 12.5V. When the tip to ring voltage exceeds 12.5V (with no RSG resistor) A1 supplies more current than I1 can sink. When this happens A2 amplifies its input current by a factor of 12 and the current through R1 becomes the difference between I2 and the output current from A2. As the current from A2 increases, the voltage across R1 decreases and the output voltage on RDC decreases. This results in a corresponding decrease in the loop current. The RSG pin provides the ability to increase the saturation guard reference voltage beyond 12.5V. Equation 3 gives the relationship between the RSG resistor value and the programmable saturation guard reference voltage: RL = Loop resistance. 20 30 LOOP CURRENT (mA) RL 100kΩ 4kΩ 2kΩ <1.2kΩ RL 100kΩ 1.5kΩ 700Ω <400Ω FIGURE 15. VTR vs IL and RL 9 VTR = Voltage differential between tip and ring. For on-hook transmission RL = ∞, Equation 4 reduces to: RSG = 4.0kΩ RSG = ∞ Ω 5 5 • 10 V TR = 16.66 + ----------------------------------R SG + 17300 (EQ. 5) HC5523 IM TIP A = 250 RF ZL VTR ZTR + + + VTX - - + VTX 1 - ZT EG - IM A=4 RSN A = 250 RING RF + VTX - ZRX IM 1000 + VRX - HC5523 FIGURE 16. SIMPLIFIED AC TRANSMISSION CIRCUIT The value of RSG should be calculated to allow maximum loop length operation. This requires that the saturation guard reference voltage be set as high as possible without clipping the incoming or outgoing VF signal. A voltage margin of -4V on tip and -4V on ring, for a total of -8V margin, is recommended as a general guideline. The value of RSG is calculated using Equation 6: 5 5 • 10 R SG = ---------------------------------------------------------------------------------------------------------------------------------------------- – 17300 (R +R ) DC1 DC2 ( V –V ) × 1 + ---------------------------------------------- – 16.66V MAR 600R L BAT (AC) Transmission Path SLIC in the Active Mode Figure 16 shows a simplified AC transmission model. Circuit analysis yields the following design equations: V TR = V TX + I M • 2R F (EQ. 9) V TX V RX IM ----------- + ----------- = ------------Z T Z RX 1000 (EQ. 10) V TR = E G – I M • Z L (EQ. 11) (EQ. 6) where: where: VTR = Is the AC metallic voltage between tip and ring, including the voltage drop across the fuse resistors RF . VBAT = Battery voltage. VMAR = Voltage Margin. Recommended value of -8V to allow a maximum overload level of 3.1V peak. For on-hook transmission RL = ∞, Equation 6 reduces to: 5 5 • 10 R SG = ------------------------------------------------------------------ – 17300 V BAT – V MAR – 16.66V (EQ. 7) IM = Is the AC metallic current. RF = Is a fuse resistor. ZT = Is used to set the SLIC’s 2-wire impedance. SLIC in the Standby Mode Overall system power is saved by configuring the SLIC in the standby state when not in use. In the standby state the tip and ring amplifiers are disabled and internal resistors are connected between tip to ground and ring to VBAT. This connection enables a loop current to flow when the phone goes off-hook. The loop current detector then detects this current and the SLIC is configured in the active mode for voice transmission. The loop current in standby state is calculated as follows: V BAT – 3V I L ≈ -------------------------------R L + 1800Ω VTX = Is the AC metallic voltage. Either at the ground referenced 4-wire side or the SLIC tip and ring terminals. (EQ. 8) VRX = Is the analog ground referenced receive signal. ZRX = Is used to set the 4-wire to 2-wire gain. EG = Is the AC open circuit voltage. ZL = Is the line impedance. (AC) 2-Wire Impedance The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors, and is calculated as follows: Let VRX = 0. Then from Equation 10 where: IL = Loop current in the standby state. RL = Loop resistance. VBAT = Battery voltage. 10 IM V TX = Z T • ------------1000 (EQ. 12) HC5523 Transhybrid Circuit ZTR is defined as: V TR Z TR = ----------IM (EQ. 13) Substituting in Equation 9 for VTR V TX 2R F • I M Z TR = ----------- + ----------------------IM IM (EQ. 14) Substituting in Equation 12 for VTX ZT Z TR = ------------- + 2R F 1000 (EQ. 15) The purpose of the transhybrid circuit is to remove the receive signal (VRX) from the transmit signal (VTX), thereby preventing an echo on the transmit side. This is accomplished by using an external op amp (usually part of the CODEC) and by the inversion of the signal from the 4-wire receive port (RSN) to the 4-wire transmit port (VTX). Figure 17 shows the transhybrid circuit. The input signal will be subtracted from the output signal if I1 equals I2. Node analysis yields the following equation: V TX V RX ----------- + ----------- = 0 R TX Z B Therefore (EQ. 16) Z T = 1000 • ( Z TR – 2R F ) (EQ. 21) The value of ZB is then V RX Z B = – R TX • ----------V Equation 16 can now be used to match the SLIC’s impedance to any known line impedance (ZTR). (EQ. 22) TX Example: Where VRX/VTX equals 1/ A4-4 Calculate ZT to make ZTR = 600Ω in series with 2.16µF. RF = 20Ω. Therefore 1 Z T = 1000 • 600 + ----------------------------------------- – 2 • 20 –6 jω • 2.16 • 10 ZT - + 2R F + Z L Z RX -----------1000 Z B = R TX • ----------- • -------------------------------------------Z L + 2R F ZT (EQ. 23) ZT = 560kΩ in series with 2.16nF Example: (AC) 2-Wire to 4-Wire Gain Given: RTX = 20kΩ, ZRX = 280kΩ, ZT = 562kΩ (standard value), RF = 20Ω and Z = 600Ω The 2-wire to 4-wire gain is equal to VTX/ VTR The value of ZB = 18.7kΩ From Equations 9 and 10 with VRX = 0 Z T ⁄ 1000 V TX A 2 – 4 = ----------- = -----------------------------------------Z T ⁄ 1000 + 2R F V TR RFB (EQ. 17) I2 RTX VTX (AC) 4-Wire to 2-Wire Gain - + The 4-wire to 2-wire gain is equal to VTR/VRX + VTX I1 From Equations 9, 10 and 11 with EG = 0 V TR ZT ZL A 4 – 2 = ----------- = – ----------- • -------------------------------------------V RX Z RX ZT ------------- + 2R F + Z L 1000 - HC5523 ZB + VRX For applications where the 2-wire impedance (ZTR, Equation 15) is chosen to equal the line impedance (ZL), the expression for A4-2 simplifies to: ZT 1 A 4 – 2 = – ----------- • --Z RX 2 ZT (EQ. 18) - RSN ZRX CODEC/ FILTER (EQ. 19) FIGURE 17. TRANSHYBRID CIRCUIT (AC) 4-Wire to 4-Wire Gain The 4-wire to 4-wire gain is equal to VTX/VRX Supervisory Functions From Equations 9, 10 and 11 with EG = 0 The loop current, ground key and the ring trip detector outputs are multiplexed to a single logic output pin called DET. See Table 1 to determine the active detector for a given logic input. For further discussion of the logic circuitry see section titled “Digital Logic Inputs”. V TX ZT Z L + 2R F A 4 – 4 = ----------- = – ----------- • -------------------------------------------V RX Z RX ZT ------------- + 2R F + Z L 1000 11 (EQ. 20) HC5523 Before proceeding with an explanation of the loop current detector, ground key detector and later the longitudinal impedance, it is important to understand the difference between a “metallic” and “longitudinal” loop currents. Figure 18 illustrates 3 different types of loop current encountered. Case 1 illustrates the metallic loop current. The definition of a metallic loop current is when equal currents flow out of tip and into ring. Loop current is a metallic current. Cases 2 and 3 illustrate the longitudinal loop current. The definition of a longitudinal loop current is a common mode current, that flows either out of or into tip and ring simultaneously. Longitudinal currents in the on-hook state result in equal currents flowing through the sense resistors R1 and R2 (Figure 18). And longitudinal currents in the off-hook state result in unequal currents flowing through the sense resistors R1 and R2. Notice that for case 2, longitudinal currents flowing away from the SLIC, the current through R1 is the metallic loop current plus the longitudinal current; whereas the current through R2 is the metallic loop current minus the longitudinal current. Longitudinal currents are generated when the phone line is influenced by magnetic fields (e.g., power lines). Loop Current Detector Figure 18 shows a simplified schematic of the loop current and ground key detectors. The loop current detector works by sensing the metallic current flowing through resistors R1 and R2. This results in a current (IRD) out of the transconductance amplifier (gm1) that is equal to the product of gm1 and the metallic loop current. IRD then flows out the RD pin and through resistor RD to VEE. The value of IRD is equal to: I TIP – I RING IL I RD = ------------------------------------ = ---------300 600 (EQ. 24) The IRD current results in a voltage drop across RD that is compared to an internal 1.25V reference voltage. When the voltage drop across RD exceeds 1.25V, and the logic is configured for loop current detection, the DET pin goes low. The hysteresis resistor RH adds an additional voltage effectively across RD, causing the on-hook to off-hook threshold to be slightly higher than the off-hook to on-hook threshold. Taking into account the hysteresis voltage, the typical value of RD for the on-hook to off-hook condition is: 465 R D = -------------------------------------------------------------------------I ON – HOOK to OFF – HOOK (EQ. 25) Taking into account the hysteresis voltage, the typical value of RD for the off-hook to on-hook condition is: 375 R D = -------------------------------------------------------------------------I OFF – HOOK to ON – HOOK (EQ. 26) A filter capacitor (CD) in parallel with RD will improve the accuracy of the trip point in a noisy environment. The value of this capacitor is calculated using the following Equation: T C D = -------RD (EQ. 27) where: T = 0.5ms Ground Key Detector gm1(IMETALLIC) RH - CURRENT LOOP COMPARATOR TIP gm1 gm2(ITIP - IRING) IRD - - VREF 1.25V VEE -5V gm2 R2 IGK RING RH + ORDERING INFORMATION - CASE 1 CASE 2 CASE 3 IMETALLIC ILONGITUDINAL ILONGITUDINAL IMETALLIC ILONGITUDINAL ILONGITUDINAL ← → ← ← - D2 + GROUND KEY COMPARATOR → → D1 I1 DIGITAL MULTIPLEXER HC5523 FIGURE 18. LOOP CURRENT AND GROUND KEY DETECTORS 12 RD + + + R1 RD DET CD HC5523 A simplified schematic of the ground key detector is shown in Figure 18. Ground key, is the process in which the ring terminal is shorted to ground for the purpose of signaling an Operator or seizing a phone line (between the Central Office and a Private Branch Exchange). The Ground Key detector is activated when unequal current flow through resistors R1 and R2. This results in a current (IGK) out of the transconductance amplifier (gm2) that is equal to the product of gm2 and the differential (ITIP -IRING) loop current. If IGK is less than the internal current source (I1), then diode D1 is on and the output of the ground key comparator is low. If IGK is greater than the internal current source (I1), then diode D2 is on and the output of the ground key comparator is high. With the output of the ground key comparator high, and the logic configured for ground key detect, the DET pin goes low. The ground key detector has a built in hysteresis of typically 5mA between its trigger and reset values. RRT R3 CRT R1 DT + DET DR TIP R4 R2 RING TRIP COMPARATOR ERG VBAT RING RINGRLY RING RELAY HC5523 FIGURE 19. RING TRIP CIRCUIT FOR BATTERY BACKED RINGING Ring Trip Detector Longitudinal Impedance Ring trip detection is accomplished with the internal ring trip comparator and the external circuitry shown in Figure 19. The process of ring trip is initiated when the logic input pins are in the following states: E0 = 0, E1 = 1/0, C1 = 1 and C2 = 0. This logic condition connects the ring trip comparator to the DET output, and causes the Ringrly pin to energize the ring relay. The ring relay connects the tip and ring of the phone to the external circuitry in Figure 19. When the phone is on-hook the DT pin is more positive than the DR pin and the DET output is high. For off-hook conditions DR is more positive than DT and DET goes low. When DET goes low, indicating that the phone has gone off-hook, the SLIC is commanded by the logic inputs to go into the active state. In the active state, tip and ring are once again connected to the phone and normal operation ensues. The feedback loop described in Figure 20(A, B) realizes the desired longitudinal impedances from tip to ground and from ring to ground. Nominal longitudinal impedance is resistive and in the order of 22Ω. Figure 19 illustrates battery backed unbalanced ring injected ringing. For tip injected ringing just reverse the leads to the phone. The ringing source could also be balanced. NOTE: The DET output will toggle at 20Hz because the DT input is not completely filtered by CRT. Software can examine the duty cycle and determine if the DET pin is low for more that half the time, if so the off-hook condition is indicated. In the presence of longitudinal currents this circuit attenuates the voltages that would otherwise appear at the tip and ring terminals, to levels well within the common mode range of the SLIC. In fact, longitudinal currents may exceed the programmed DC loop current without disturbing the SLIC’s VF transmission capabilities. The function of this circuit is to maintain the tip and ring voltages symmetrically around VBAT/2, in the presence of longitudinal currents. The differential transconductance amplifiers GT and GR accomplish this by sourcing or sinking the required current to maintain VC at VBAT/2. When a longitudinal current is injected onto the tip and ring inputs, the voltage at VC moves from it’s equilibrium value VBAT/2. When VC changes by the amount DVC, this change appears between the input terminals of the differential transconductance amplifiers GT and GR. The output of GT and GR are the differential currents ∆I1 and ∆I2, which in turn feed the differential inputs of current sources IT and IR respectively. IT and IR have current gains of 250 single ended and 500 differentially, thus leading to a change in IT and IR that is equal to 500(∆I) and 500(∆I2). The circuit shown in Figure 20(B) illustrates the tip side of the longitudinal network. The advantages of a differential input current source are: improved noise since the noise due to current source 2IO is now correlated, power savings due to differential current gain and minimized offset error at the Operational Amplifier inputs via the two 5kΩ resistors. 13 HC5523 Digital Logic Inputs A combination of the control pins C1 and C2 is used to select 1 of the 4 possible operating states. A description of each operating state and the control logic follow: Table 1 is the logic truth table for the TTL compatible logic input pins. The HC5523 has two enable inputs pins (E0, E1) and two control inputs pins (C1, C2). Open Circuit State (C1 = 0, C2 = 0) In this state the SLIC is effectively off. All detectors and both the tip and ring line drive amplifiers are powered down, presenting a high impedance to the line. Power dissipation is at a minimum. The enable pin E0 is used to enable or disable the DET output pin. The DET pin is enabled if E0 is at a logic level 0 and disabled if E0 is at a logic level 1. The enable pin E1 gates the ground key detector to the DET output with a logic level 0, and gates the loop or ring trip detector to the DET output with a logic level 1. TIP CURRENT SOURCE WITH DIFFERENTIAL INPUTS ILONG ILONG IT TIP 20Ω ∆I1 ∆I1 + ∆VT TIP - 5kΩ GT RLARGE 5kΩ - + RLARGE VC VBAT/2 + - ∆I1 ∆I1 VC VBAT/2 GR RLARGE ILONG + ∆VR ILONG 2I0 ∆I2 - ∆I2 RLARGE GT RING IR RING HC5523 FIGURE 20A. TIP DIFFERENTIAL TRANSCONDUCTANCE AMPLIFIER FIGURE 20B. FIGURE 20. LONGITUDINAL IMPEDANCE NETWORK Active State (C1 = 0, C2 = 1) AC Transmission Circuit Stability The tip output is capable of sourcing loop current and for open circuit conditions is about -4V from ground. The ring output is capable of sinking loop current and for open circuit conditions is about VBAT +4V. VF signal transmission is normal. The loop current and ground key detectors are both active, E0 and E1 determine which detector is gated to the DET output. To ensure stability of the AC transmission feedback loop two compensation capacitors CTC and CRC are required. Figure 21 (Application Circuit) illustrates their use. Recommended value is 2200pF. Ringing State (C1 = 1, C2 = 0) The high pass filter capacitor connected between pins HPT and HPR provides the separation between circuits sensing tip to ring DC conditions and circuits processing AC signals. A 10nf CHP will position the low end frequency response 3dB break point at 48Hz. Where: The ring relay driver and the ring trip detector are activated. Both the tip and ring line drive amplifiers are powered down. Both tip and ring are disconnected from the line via the external ring relay. Standby State (C1 = 1, C2 = 1) Both the tip and ring line drive amplifiers are powered down. Internal resistors are connected between tip to ground and ring to VBAT to allow loop current detect in an off-hook condition. The loop current and ground key detectors are both active, E0 and E1 determine which detector is gated to the DET output. 14 AC-DC Separation Capacitor, CHP 1 f 3dB = ----------------------------------------------------( 2 • π • R HP • C HP ) (EQ. 28) where RHP = 330kΩ Thermal Shutdown Protection The HC5523’s thermal shutdown protection is invoked if a fault condition on the tip or ring causes the temperature of the die to exceed 160oC. If this happens, the SLIC goes into a high impedance state and will remain there until the HC5523 temperature of the die cools down by about 20oC. The SLIC will return back to its normal operating mode, providing the fault condition has been removed. Surge Voltage Protection The HC5523 must be protected against surge voltages and power crosses. Refer to “Maximum Ratings” TIPX and RINGX terminals for maximum allowable transient tip and ring voltages. The protection circuit shown in Figure 21 utilizes diodes together with a clamping device to protect tip and ring against high voltage transients. Positive transients on tip or ring are clamped to within a couple of volts above ground via diodes D1 and D2. Under normal operating conditions D1 and D2 are reverse biased and out of the circuit. Negative transients on tip and ring are clamped to within a couple of volts below ground via diodes D3 and D4 with the help of a Surgector. The Surgector is required to block conduction through diodes D3 and D4 under normal operating conditions and allows negative surges to be returned to system ground. SLIC Operating States TABLE 1. LOGIC TRUTH TABLE E0 E1 C1 C2 SLIC OPERATING STATE ACTIVE DETECTOR DET OUTPUT 0 0 0 0 Open Circuit No Active Detector Logic Level High 0 0 0 1 Active Ground Key Detector Ground Key Status 0 0 1 0 Ringing No Active Detector Logic Level High 0 0 1 1 Standby Ground Key Detector Ground Key Status 0 1 0 0 Open Circuit No Active Detector Logic Level High 0 1 0 1 Active Loop Current Detector Loop Current Status 0 1 1 0 Ringing Ring Trip Detector Ring Trip Status 0 1 1 1 Standby Loop Current Detector Loop Current Status 1 0 0 0 Open Circuit No Active Detector 1 0 0 1 Active Ground Key Detector 1 0 1 0 Ringing No Active Detector 1 0 1 1 Standby Ground Key Detector 1 1 0 0 Open Circuit No Active Detector 1 1 0 1 Active Loop Current Detector 1 1 1 0 Ringing Ring Trip Detector 1 1 1 1 Standby Loop Current Detector Logic Level High The fuse resistors (RF) serve a dual purpose of being nondestructive power dissipaters during surge and fuses when the line in exposed to a power cross. The analog and digital grounds should be tied together at the device. Notes Power-Up Sequence The HC5523 has no required power-up sequence. This is a result of the Dielectrically Isolated (DI) process used in the fabrication of the part. By using the DI process, care is no longer required to insure that the substrate be kept at the most negative potential as with junction isolated ICs. Printed Circuit Board Layout Care in the printed circuit board layout is essential for proper operation. All connections to the RSN pin should be made as close to the device pin as possible, to limit the interference that might be injected into the RSN terminal. It is good practice to surround the RSN pin with a ground plane. 15 2. Overload Level (Two-Wire port) - The overload level is specified at the 2-wire port (VTR0) with the signal source at the 4-wire receive port (ERX). IDCMET = 30mA, RSG = 4kΩ, increase the amplitude of ERX until 1% THD is measured at VTRO. Reference Figure 1. 3. Longitudinal Impedance - The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. LZT, LZR, VT, VR, AR and AT are defined in Figure 2. (TIP) LZT = VT /AT (RING) LZR = VR /AR where: EL = 1VRMS (0Hz to 100Hz) 4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook (Active, C1 = 1, C2 = 0) longitudinal current limit is determined by increasing the amplitude of EL (Figure 3A) until the 2-wire HC5523 longitudinal balance drops below 45dB. DET pin remains low (no false detection). 5. Longitudinal Current Limit (On-Hook Standby) - On-Hook (Active, C1 = 1, C2 = 1) longitudinal current limit is determined by increasing the amplitude of EL (Figure 3B) until the 2-wire longitudinal balance drops below 45dB. DET pin remains high (no false detection). 6. Longitudinal to Metallic Balance - The longitudinal to metallic balance is computed using the following equation: BLME = 20 • log (EL /VTR), where: EL and VTR are defined in Figure 4. 7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The metallic to longitudinal balance is defined in this spec. 8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire balance is computed using the following equation: BLFE = 20 • log (EL /VTX),: EL and VTX are defined in Figure 4. 9. Metallic to Longitudinal Balance - The metallic to longitudinal balance is computed using the following equation: BMLE = 20 • log (ETR /VL), ERX = 0 where: ETR, VL and ERX are defined in Figure 5. 10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal balance is computed using the following equation: BFLE = 20 • log (ERX /VL), ETR = source is removed. where: ERX, VL and ETR are defined in Figure 5. 11. Two-Wire Return Loss - The 2-wire return loss is computed using the following equation: r = -20 • log (2VM /VS) where: ZD = The desired impedance; e.g., the characteristic impedance of the line, nominally 600Ω. (Reference Figure 6). 12. Overload Level (4-Wire port) - The overload level is specified at the 4-wire transmit port (VTXO) with the signal source (EG) at the 2-wire port, IDCMET = 23mA, ZL = 20kΩ, RSG = 4kΩ (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTXO. Note that the gain from the 2-wire port to the 4-wire port is equal to 1. 13. Output Offset Voltage - The output offset voltage is specified with the following conditions: EG = 0, IDCMET = 23mA, ZL = ∞ and is measured at VTX. EG, IDCMET, VTX and ZL are defined in Figure 7. Note: IDCMET is established with a series 600Ω resistor between tip and ring. 14. Two-Wire to Four-Wire (Metallic to VTX) Voltage Gain - The 2-wire to 4-wire (metallic to VTX) voltage gain is computed using the following equation. G2-4 = (VTX /VTR), EG = 0dBm0, VTX, VTR, and EG are defined in Figure 7. 15. Current Gain RSN to Metallic - The current gain RSN to Metallic is computed using the following equation: K = IM [(RDC1 + RDC2)/(VRDC - VRSN)] K, IM, RDC1, RDC2, VRDC and VRSN are defined in Figure 8. 16. Two-Wire to Four-Wire Frequency Response - The 2-wire to 4-wire frequency response is measured with respect to EG = 0dBm at 1.0kHz, ERX = 0V, IDCMET = 23mA. The frequency response is computed using the following equation: F2-4 = 20 • log (VTX /VTR), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX, VTR, and EG are defined in Figure 9. 17. Four-Wire to Two-Wire Frequency Response - The 4-wire to 2-wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG = 0V, IDCMET = 23mA. The frequency response is computed using the following equation: F4-2 = 20 • log (VTR /ERX), vary frequency from 300Hz to 16 3.4kHz and compare to 1kHz reading. VTR and ERX are defined in Figure 9. 18. Four-Wire to Four-Wire Frequency Response - The 4-wire to 4-wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG = 0V, IDCMET = 23mA. The frequency response is computed using the following equation: F4-4 = 20 • log (VTX /ERX), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX and ERX are defined in Figure 9. 19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire insertion loss is measured with respect to EG = 0dBm at 1.0kHz input signal, ERX = 0, IDCMET = 23mA and is computed using the following equation: L2-4 = 20 • log (VTX /VTR) where: VTX, VTR, and EG are defined in Figure 9. (Note: The fuse resistors, RF , impact the insertion loss. The specified insertion loss is for RF = 0). 20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire insertion loss is measured based upon ERX = 0dBm, 1.0kHz input signal, EG = 0, IDCMET = 23mA and is computed using the following equation: L4-2 = 20 • log (VTR /ERX) where: VTR and ERX are defined in Figure 9. 21. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire gain tracking is referenced to measurements taken for EG = -10dBm, 1.0kHz signal, ERX = 0, IDCMET = 23mA and is computed using the following equation. G2-4 = 20 • log (VTX /VTR) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTX and VTR are defined in Figure 9. 22. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire gain tracking is referenced to measurements taken for ERX = -10dBm, 1.0kHz signal, EG = 0, IDCMET = 23mA and is computed using the following equation: G4-2 = 20 • log (VTR /ERX) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTR and ERX are defined in Figure 9. The level is specified at the 4-wire receive port and referenced to a 600Ω impedance level. 23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise at VTR is specified with the 2-wire port terminated in 600Ω (RL) and with the 4-wire receive port grounded (Reference Figure 10). 24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise at VTX is specified with the 2-wire port terminated in 600Ω (RL). The noise specification is with respect to a 600Ω impedance level at VTX. The 4-wire receive port is grounded (Reference Figure 10). 25. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic distortion is measured with the following conditions. EG = 0dBm at 1kHz, IDCMET = 23mA. Measurement taken at VTX. (Reference Figure 7). 26. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic distortion is measured with the following conditions. ERX = 0dBm0. Vary frequency between 300Hz and 3.4kHz, IDCMET = 23mA. Measurement taken at VTR. (Reference Figure 9). 27. Constant Loop Current - The constant loop current is calculated using the following equation: IL = 2500 / (RDC1 + RDC2) 28. Standby State Loop Current - The standby state loop current is calculated using the following equation: HC5523 IL = [|VBAT| - 3] / [RL +1800], TA = 25oC 29. Ground Key Detector - (TRIGGER) Increase the input current to 8mA and verify that DET goes low. (RESET) Decrease the input current from 17mA to 3mA and verify that DET goes high. (Hysteresis) Compare difference between trigger and reset. 30. Power Supply Rejection Ratio - Inject a 100mVRMS signal (50Hz to 4kHz) on VBAT, VCC and VEE supplies. PSRR is computed using the following equation: PSRR = 20 • log (VTX /VIN). VTX and VIN are defined in Figure 12. 17 HC5523 Pin Descriptions PLCC PDIP 1 SYMBOL RINGSENS DESCRIPTION Internally connected to output of RING power amplifier. E 2 7 BGND 4 8 VCC 5 9 RINGRLY 6 10 VBAT Battery supply voltage, -24V to -56V. 7 11 RSG Saturation guard programming resistor pin. 8 12 E1 TTL compatible logic input. The logic state of E1 in conjunction with the logic state of C1 determines which detector is gated to the DET output. 9 13 E0 TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to a logic level one. 11 14 DET Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is an open collector with an internal pull-up of approximately 15kΩ to VCC. 12 15 C2 TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing or Standby) of the SLIC. 13 16 C1 TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing or Standby) of the SLIC. 14 17 RDC DC feed current programming resistor pin. Constant current feed is programmed by resistors RDC1 and RDC2 connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND to isolate the AC signal components. 15 18 AGND 16 19 RSN Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all connect to this pin. 18 20 VEE -5V power supply. 19 21 VTX Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the 2-wire input impedance connects between this pin and RSN. 20 22 HPR RING side of AC/DC separation capacitor CHP . CHP is required to properly separate the ring AC current from the DC loop current. The other end of CHP is connected to HPT. 21 1 HPT TIP side of AC/DC separation capacitor CHP . CHP is required to properly separate the tip AC current from the DC loop current. The other end of CHP is connected to HPR. 22 2 RD Loop current programming resistor. Resistor RD sets the trigger level for the loop current detect circuit. A filter capacitor CD is also connected between this pin and VEE. 23 3 DT Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. 25 4 DR Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. 26 TIPSENSE 27 5 TIPX 28 6 RINGX 3, 10, 17, 24 N/C Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND but it is recommended that it is connected to the same potential as AGND. +5V power supply. Ring relay driver output. Analog ground. Internally connected to output of tip power amplifier. Output of tip power amplifier. Output of ring power amplifier. No internal connection. 18 HC5523 Pinouts N/C BGND RINGSENSE RINGX TIPX TIPSENSE HC5523 (PDIP) TOP VIEW VCC HC5523 (PLCC) TOP VIEW 4 3 2 1 28 27 26 RINGRLY 5 VBAT 6 RSG E1 7 18 AGND 25 DR RINGX 6 17 RDC 24 N/C BGND 7 16 C1 VCC 8 15 C2 16 17 18 RDC AGND RSN N/C VEE 19 VTX C1 DET 11 C2 20 HPR 15 19 20 VEE 19 RSN N/C 10 14 3 5 21 HPT 13 21 VTX DT 4 22 RD 12 22 HPR 2 DR 9 E0 1 RD TIPX 23 DT 8 HPT RINGRLY 9 14 DET VBAT 10 13 E0 RSG 11 12 E1 HC5523 Application Circuit RRT CRT CHP (NOTE 32) R1 RFB R3 RD 21 HPT -5V R2 R4 VBAT PTC RF1 TIP D1 D3 PTC U1 HPR 20 22 RD VTX 19 23 DT VEE 18 25 DR RSN 16 27 TIPX AGND 15 2 BGND RDC 14 RF2 RT RB RRX RDC1 RDC2 CRC D4 - + -5V CODEC/FILTER CTC NOTE 31 RING U2 RTX 4 VCC C1 13 28 RINGX C2 12 CDC D2 Surgector K A VBAT DET 11 6 VBAT G D5 RINGING (VBAT + 90VRMS) +5V OR 12V 5 RINGRLY EO 9 7 RSG E1 8 RSG RELAY -5V D6 U1 SLIC (Subscriber Line Interface Circuit) HC5526 U2 Combination CODEC/Filter e.g. CD22354A or Programmable CODEC/ Filter, e.g. SLAC R1, R3 200kΩ, 5%, 1/4W R2 910kΩ, 5%, 1/4W R4 1.2MΩ, 5%, 1/4W RB 18.7kΩ,1%, 1/4W RD 39kΩ, 5%, 1/4W CDC 1.5µF, 20%, 10V CHP 10nF, 20%, 100V (Note 2) RDC1, RDC2 41.2kΩ, 5%, 1/4W CRT 0.39µF, 20%, 100V RFB 20.0kΩ, 1%, 1/4W CTC, CRC 2200pF, 20%, 100V RRX 280kΩ, 1%, 1/4W Relay Relay, 2C Contacts, 5V or 12V Coil RT 562kΩ, 1%, 1/4W RTX 20kΩ, 1%, 1/4W D1 - D5 IN4007 Diode RRT 150Ω, 5%, 2W Surgector SGT27S10 RSG VBAT = -28V, RSG = ∞ VBAT = -48V, RSG = 21.4kΩ, 1/4W 5% PTC Polyswitch TR600-150 D6 Diode, 1N4454 RF1, RF2 Line Resistor, 20Ω, 1% Match, 2 W Carbon column resistor or thick film on ceramic NOTES: 31. It is recommended that the anodes of D3 and D4 be shorted to ground through a battery referenced surgector (SGT27S10). 32. To meet the specified 25dB 2-wire return loss at 200Hz, CHP needs to be 20nF, 20%, 100V. FIGURE 21. APPLICATION CIRCUIT 20 HC5523 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N28.45 (JEDEC MS-018AB ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 21 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE HC5523 Dual-In-Line Plastic Packages (PDIP) E22.4 (JEDEC MS-010-AA ISSUE C) N 22 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.065 1.15 1.65 8 eA C 0.009 0.015 C D 1.065 1.120 D1 0.005 - 0.13 E 0.390 0.425 9.91 10.79 6 E1 0.330 0.390 8.39 9.90 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. e 0.229 0.381 27.06 0.100 BSC 28.44 - 2.54 BSC 5 5 - eA 0.400 BSC 10.16 BSC 6 eB - 0.500 - 12.70 7 L 0.115 0.160 2.93 4.06 4 N 22 22 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22