ERICSSON PBL3766

September 1997
PBL 3766, PBL 3766/6
Subscriber Line
Interface Circuit
Description
Key Features
The PBL 3766 Subscriber Line Interface Circuit (SLIC) is a monolithic integrated
circuit, manufactured in 75 V bipolar technology. The PBL 3766 SLIC facilitates the
design of cost effective, high performance on-premises (ONS) analog line interface
cards for PABX systems and terminal adapters. Small package size and few
required external components result in a miniaturized design.
The PBL 3766 programmable, constant current loop feed system can operate with
battery supply voltages between -24 V and -58 V.
The SLIC incorporates loop current and ring trip detection functions as well as a
ring relay driver.
The two- to four-wire and four- to two-wire voice frequency (vf) signal conversion,
i.e. the hybrid function, is provided by the SLIC in conjunction with either a conventional or a programmable CODEC/filter.
The PBL 3766 package is a 22 pin, plastic dual-in-line (batwing) or a 28-pin, plastic
j-leaded chip carrier (PLCC).
The differences between PBL 3766 and PBL 3766/6 are the specifications for
balance, output offset voltage, and insertion loss.
• Low cost
• Few external components
• Programmable, constant current loop
feed
• Line feed characteristics independent
of battery supply variations
• -24 V to -58 V battery supply voltage
range
• Detectors
– programmable loop current detector
– ring trip detector
• Ring relay driver
• Hybrid function with conventional or
programmable CODEC/filters
• Line terminating impedance, complex
or real, set by a simple external
network or controlled by a
programmable CODEC/filter
27/21
HPT
20/15
HPR
21/16
Input/Output
Decoder and
Control
VEE
18/13
12/9
C2
9/7
E0
Two-wire
Interface
Line Feed
Controller
and
Longitudinal
Signal
Suppression
• Low on-hook power dissipation:
20 mW @ -28 V, 35 mW @ -48 V
• Tip-ring open circuit state for
subscriber loop power denial
• On-hook transmission
DET
14/11 RDC
7/4
RSG
VBAT
2/1
Loop Current
Detector
22/19
VTX
37
19/14
VF Signal
Transmission
RD
L
B
P 66
GND
3, 6, 10, 17, 24/
5, 6, 17, 18
P
B
4/2
C1
11/8
28/22
VCC
13/10
• Idle noise typ. -83 dBmp, typ. 7 dBrnC
66
TIPX
RINGX
Ring Trip
Detector
23/20
RINGRLY
37
DT
5/3
L
Ring Relay
Driver
16/12 RSN
Figure 1. Block diagram. Pin numbers PLCC/DIP.
4-1
PBL 3766
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature and humidity
Storage temperature range
Operating temperature range
Operating junction temperature
Storage humidity
TStg
TCase
TJ
RH
-60
-10
-10
5
+150
+110
+140
95
°C
°C
°C
% RH
Power supply, -10 °C < TAmb < 80 °C
VCC with respect to GND
VEE with respect to GND
VBat with respect to GND
VCC
VEE
VBat
-0.5
-6.5
-70
6.5
0.5
VEE+0,7
V
V
V
Power dissipation
Continuous power dissipation at TAmb ≤ 70 °C
Peak power dissipation at TAmb = 70°C, t < 10 ms, trep > 10 sec.
PD
PDP
1.5
4
W
W
Relay driver
Ring relay supply voltage
Ring relay current
VRRly
IRRly
VBat
0
50
V
mA
Ring trip comparator
Input voltage
Input current
VDT
IDT
VBat
-2
0
2
V
mA
Digital inputs, outputs (C1, C2, E0, DET)
Input voltage
Output voltage (DET disabled)
Output current (DET enabled)
VID
VOD
IOD
0
0
VCC
VCC
5
V
V
mA
VT, VR
VT, VR
VT, VR
VT, VR
VBat
VBat - 20
VBat - 40
VBat - 70
0.5
5
10
15
V
V
V
V
80
25
mA
mA
TIPX or RINGX terminals, VBAT = -50 V
TIPX or RINGX voltage, continuous, (Note 1)
TIPX or RINGX pulse = tω < 10 ms, trep > 10 s (Notes 2, 3)
TIPX or RINGX pulse = tω < 1 µs, trep > 10 s (Notes 2, 3)
TIP or RING pulse = tω < 250 ns, trep > 10 s (Notes 2, 3)
TIPX or RINGX current
Active
Stand-by
ILdc + ILodc
ILdc
Recommended Operating Conditions
Parameter
Symbol
Min
Max
Unit
Case temperature
VCC with respect to ground
VEE with respect to ground
VBat with respect to ground (Note 4)
TCase
VCC
VEE
VBat
0
4.75
-5.25
-58
90
5.25
-4.75
-24
°C
V
V
V
Notes
1.
With a diode (D2) connected in series with the VBat supply, as shown in figure 11, -70 V may be continuously applied to the
TIPX or RINGX lead.
2.
These voltage ratings require a diode (D2) to be installed in series with the VBat supply as shown in figure 11.
3.
VT and VR are referenced to ground. tω is the pulse width of a rectangular test pulse and trep is the pulse repetition rate.
4.
-24 V < VBat < -21 V may be used in applications requiring maximum vf signal amplitudes less than 3 Vpk (8.75 dBm, 600 ohms).
4-2
PBL 3766
Electrical Characteristics
0 °C < TAmb < 70 °C, VCC = +5 V ±5 %, VEE = -5 V ±5 %, VBat = -48 V, RSG = 0 ohm , RDC = 41.7 kohms, RD = ∞, ZL = 600 ohms,
CHP = 33 nF, CDC = 1.5 µF unless otherwise specified.
Parameter
Two-wire port
Overload level, VTRO
Input impedance, ZTRX
Longitudinal impedance, ZLoT, ZLoR
Longitudinal current limit, ILoT, ILoR
Longitudinal to metallic balance, BLM
PBL 3766
PBL 3766/6
Longitudinal to metallic balance, BLME
Ref
Fig.
2
3
Conditions
Min
ZL = 600 ohms, 1% THD, Note 1
Note 2
f < 100 Hz
active state, C2, C1 = 1, 0
IEEE standard 455-1985
0.2 kHz ≤ f ≤ 3 kHz
3.1
BLME = 20 · log
Typ
Max
Unit
VPk
25
20
40
ohm/wire
mApk/wire
53
48
58
58
dB
dB
53
48
58
58
dB
dB
53
48
58
58
dB
dB
50
48
55
55
dB
dB
55
dB
|ELo|
|VTR|
0.05kHz ≤ f ≤ 3.4kHz
PBL 3766
PBL 3766/6
Longitudinal to four-wire balance, BLFE
3
BLFE = 20 · log
|ELo|
|VTX|
0.05kHz ≤ f ≤ 3.4kHz
PBL 3766
PBL 3766/6
Metallic to longitudinal balance, BMLE
4
BMLE = 20 · log
|ETR|
|VLo|
0.2kHz ≤ f ≤ 3.4kHz
PBL 3766
PBL 3766/6
Four-wire to longitudinal balance, BFLE
4
BFLE = 20 · log
|ERX|
|VLo|
0.2kHz ≤ f ≤ 3.4kHz
, ERX = 0
, ETR source removed
40
C
Figure 2. Overload level, VTRO, two-wire
port.
1
ωC
RL
V TRO
TIPX
27/21
VTX
19/14
PBL 3766
I Ldc
<< RL, RL = 600 ohms,
RINGX
28/22
1
ωC
<< 150 ohms, RLR = RLT = 300 ohms,
RT = 600 kohms, RRX = 300 kohms
E RX
RSN
16/12
RRX
RT = 600 kohms, RRX = 300 kohms
Figure 3. Longitudinal to metallic (BLME)
and longitudinal to four-wire (BLFE)
balance.
RT
E LO
C
TIPX
27/21
RLT
V TR
RLR
VTX
19/14
PBL 3766
RINGX
28/22
RT
V TX
RSN
16/12
RRX
4-3
PBL 3766
Ref.
Fig.
Parameter
Two-wire return loss, r
r = 20 · log
RINGX idle voltage, VRi
Four-wire transmit port (VTX)
Overload level, VTXO
5
Output offset voltage, ∆VTX
PBL 3766
PBL 3766/6
Output impedance, zTX
Frequency response
Two-wire to four-wire, g2-4
6
Four-wire to two-wire, g4-2
6
Four-wire to four-wire, g4-4
6
Insertion loss
Two-wire to four-wire, G2-4
PBL 3766
PBL 3766/6
Four-wire to two-wire, G4-2
PBL 3766
PBL 3766/6
Four-wire to four-wire, G4-4
6
6
6
TIPX
27/21
RLT
E TR
RLR
TIPX
27/21
30
32
25
-5
0
-43
-48
dB
dB
dB
V
V
V
V
3.1
VPk
+40
+55
20
mV
mV
ohm
IRSN = 0
0.3 kHz ≤ f ≤ 3.4 kHz
0.3 kHz ≤ f ≤ 3.4 kHz
0
<5
1000
20
V
ohm
ratio
-0.1
0
+0.1
dB
-0.1
0
+0.1
dB
-0.1
0
+0.1
dB
-0.20
-0.25
0
0
+0.20
+0.25
dB
dB
-0.20
-0.25
-0.3
0
0
0
+0.20
+0.25
+0.3
dB
dB
dB
0.3 kHz < f < 3.4 kHz relative
to 0 dBu, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz relative
to 0 dBu, 1.0 kHz. EL = 0 V
0.3 kHz < f < 3.4 kHz relative
to 0 dBu, 1.0 kHz. EL = 0 V
0 dBm, 1.0 kHz, Note 5
0 dBm, 1.0 kHz, Notes 5, 6
0 dBm, 1.0 kHz, Notes 5, 6
Figure 4. Metallic to longitudinal (BMLE)
and four-wire to longitudinal (BFLE)
balance.
VTX
19/14
RT
E RX
1
ωC
RSN
16/12
<< 150 ohms, RLR = RLT = 300 ohms,
RT = 600 kohms, RRX = 300 kohms
VTX
19/14
PBL 3766
RINGX
28/22
Unit
<5.0
Figure 5. Overload level, VTXO, four-wire
transmit port.
RL
I Ldc
Max
0.2 kHz < f < 3.4 kHz
PBL 3766
RINGX
28/22
C
RT
V TXO
1
ωC
RSN
16/12
RRX
4-4
25
27
23
Load impedance > 20 kohms,
1% THD, Note 4
RRX
EL
Typ
-40
-55
Four-wire receive port (RSN)
RSN dc voltage, VRSN
RSN impedance, zRSN
RSN current (IRSN) to metallic loop current
(IL) gain, αRSN
V LO
Min
|ZTRX + ZL|
|ZTRX - ZL|
ZTRX ≈ ZL = nom. 600Ω, Note 3
0.2 kHz ≤ f ≤ 0.5 kHz
0.5 kHz ≤ f ≤ 1.0 kHz
1.0 kHz ≤ f ≤ 3.4 kHz
active, IL = 0
stand-by, IL = 0
active, IL = 0
stand-by, IL = 0
TIPX idle voltage, VTi
C
Conditions
<< RL, RL = 600 ohms,
RT = 600 kohms, RRX = 300 kohms
PBL 3766
Parameter
Ref
Fig.
Gain tracking
Two-wire to four-wire
6
Four-wire to two-wire
Conditions
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +7 dBm
-55 dBm to -40 dBm
Ref. -10 dBm, 1.0 kHz, Note 8
-40 dBm to +7 dBm
-55 dBm to -40 dBm
6
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) port
Active state, C2, C1 = 1, 0
2500
IL =
RDC + 41700
RDC in ohms
Stand-by state, C2, C1 = 1, 1
VBat - 3
IL =
RL + 1800
VBat tol. ±5%, TAmb = 25 °C
Stand-by state loop current, IL,
tolerance range
Loop current detector
On-hook to off-hook threshold, ILThOff
Off-hook to on-hook threshold, ILThOn
Detector threshold hysteresis, ∂ILTh
Loop current detector conversion factor
on-hook to off-hook, KLThOff
±0.03
±0.03
+0.15
dB
dB
-0.15
±0.03
±0.03
+0.15
dB
dB
-83
7
-78
12
dBmp
dBrnC
-65
-54
dB
0.85 · IL
IL
1.15 · IL
A
0.75·IL
IL
1.25·IL
A
1

375
ILThOff = KLThOff· 
+

 RD 62500 
Note 11
 1
1 
ILThOn = KLThOn· 
+

 RD 62500 
Note 11
Source resistance, RS = 0
VBat < VDT < 0 V
Ring relay driver
On-state voltage, VRRly
Off state leakage current, IRRly
IRRly = 25 mA
VBat < VRRly < 0
C
RT = 600 kohms, RRX = 300 kohms
-0.15
8.0
7.3
0.7
 1
Ring trip detector
Offset voltage, ∆VDTR
Input bias current, IDT
Input common mode range, VDT
<< RL, RL = 600 ohms,
Unit
RD = ∞, Note 10
RD = ∞, Note 10
Loop current detector conversion factor
off-hook to on-hook, KLThOn
ωC
Max
0.3 kHz ≤ f ≤ 3.4 kHz
0 dBm, 1.0 kHz test signal
Battery feed characteristics
Loop current in constant current region, IL
1
Typ
Note 9
Psophometrical weighting
C-message weighting
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
Figure 6. Frequency response, insertion
loss, gain tracking.
Min
TIPX
27/21
500
mA
mA
mA
660
455
-25
-300
VBat+1
-100
-0.5
-0.2
V
V
25
-2
mV
nA
V
10
V
µA
VTX
19/14
RL
V TR
EL
I Ldc
PBL 3766
RINGX
28/22
RT
E RX
V TX
RSN
16/12
RRX
4-5
PBL 3766
Parameter
Digital inputs (C1, C2, E0)
Input low voltage, VIL
Input high voltage, VIH
Input low current, IIL
C1, C2
E0
Input high current, IIH
Digital output (DET)
Output low voltage, VOL
Output high voltage, VOH
Internal pull-up resistor
DET short circuit current, IODs
Power supply rejection ratio, PSRR
To two-wire or four-wire port, from
VCC, PSRRCC
VEE, PSRREE
VBat, PSRRBat
Power supply currents (relay driver off)
VCC current, ICC
VEE current, IEE
VBat current, IBat
VCC current, ICC
VEE current, IEE
VBat current, IBat
VCC current, ICC
VEE current, IEE
VBat current, IBat
Power dissipation
Open circuit state total dissipation, POp
Stand-by state total dissipation, POnSb
Active state total dissipation, POnAct
Active state total dissipation,
POffAct200
POffAct600
Ref.
Fig.
Conditions
22-pin plastic DIP, θJP22dip
4-6
Typ
0
2.0
Max
Unit
0.8
VCC
V
V
40
µA
µA
µA
VIL = 0.4 V
-200
-100
VIH = 2.4 V
IOL = 2 mA, E0 = 0
IOH = -100 µA, E0 = 0
2.7
10
E0 = 1, DET shorted to ground
Note 12
50 Hz ≤ f ≤ 4 kHz
4 kHz ≤ f ≤ 50 kHz
50 Hz ≤ f ≤ 4 kHz
4 kHz ≤ f ≤ 50 kHz
50 Hz ≤ f ≤ 4 kHz
4 kHz ≤ f ≤ 50 kHz
30
30
30
12
40
30
0.4
0.6
15
-330
20
V
V
kohm
µA
35
35
35
18
50
35
dB
dB
dB
dB
dB
dB
Open circuit state
C2, C1 = 0, 0
On-hook
Stand-by state
C2, C1 = 1, 1
On-hook
Active state
C2, C1 = 1, 0
On-hook
1
1
0.5
2
1
0.5
4
2
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
C2, C1 = 0, 0
On-hook (RL = ∞) or off-hook (RL = 0)
C2, C1 = 1, 1
On-hook (RL = ∞)
C2, C1 = 1, 0
On-hook (RL = ∞)
C2, C1 = 1, 0, Note 13
Off-hook, RL = 200 ohm
Off-hook, RL = 600 ohm
25
35
mW
35
45
mW
160
220
mW
1.35
1.05
1.50
1.20
W
W
160
20
170
°C
°C
10
15
°C/W
10
15
°C/W
Temperature guard
Junction temperature at threshold, TJG
Temperature guard hysteresis, ∂TJG
Thermal resistance
28-pin PLCC, θJP28plcc
Min
145
Junction to terminals 3, 6, 10, 17, 24
connected together, Note 14
Junction to terminals 5, 6, 17, 18
connected together, Note 14
PBL 3766
Notes
1.
2.
The overload level is specified at the two-wire port with the signal source at the four-wire receive port.
The two-wire impedance is programmable by selection of external component values according to:
ZTRX = ZT/|G2-4 · αRSN|
where
ZTRX
= impedance between the TIPX and RINGX terminals
ZT
= programming network between the VTX and RSN terminals
G2-4
= TIPX-RINGX to VTX gain, nominally = 1
αRSN
= receive current gain, nominally = -1000 (current defined as positive when flowing into the receive summing node,
RSN and when flowing from TIPX to RINGX).
3.
Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance
programming resistor, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground.
For RT = 600 kohms the capacitance value is approximately 33 pF.
4.
The overload level is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the
gain from the two-wire port to the four-wire transmit port is G2-4 = 1.
5.
Fuse resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for
RF = 0.
6.
The specified insertion loss tolerance does not include errors caused by external components.
7.
The level is specified at the two-wire port.
8.
The level is specified at the four-wire receive port and referenced to a 600 ohm impedance level.
9.
The two-wire idle noise is specified with the port terminated in 600 ohms (RL) and with the four-wire receive port grounded
(ERX = 0, see figure 6).
The four-wire idle noise at VTX is specified with the two-wire port terminated in 600 ohms (RL). The noise specification is with
respect to a 600 ohm impedance level at VTX. The four-wire receive port is grounded (ERX = 0, see figure 6).
10. With the RD terminal left open, the loop current detector on-hook to off-hook threshold is internally set to 8.0 mA and the offhook to on-hook threshold to 7.3 mA. The loop current detection threshold can be set to higher values by connecting a
resistor, RD, between terminal RD and VEE (-5 V), as described in section Loop Monitoring Functions.
11. Refer to section Loop Monitoring Functions, Loop Current Detector.
12. Power supply rejection ratio test signal is 100 mVrms (sinusoidal).
13. Line resistor RF = 0 ohm.
14. Junction to ambient thermal resistance will be dependent on external thermal resistance from VBAT terminals to ambient.
4-7
26 TIPX Sense
27 TIPX
28 RINGX
RINGX Sense
1
BGND
2
3 VBAT
4 VCC
PBL 3766
GND
1
22 RINGX
VCC
2
21 TIPX
RINGRLY
3
20 DT
RSG
4
19 RD
VBAT
5
18 VBAT
VBAT
6
17 VBAT
E0
7
16 HPR
RSG
7
23 DT
NC
8
22 RD
E0
9
21 HPR
VBAT 10
20 HPT
DET
8
15 HPT
11
19 VTX
C2
9
14 VTX
C1 10
13 VEE
RDC 11
12 RSN
C2 12
DET
VEE 18
24 VBAT
VBAT 17
6
RSN 16
VBAT
NC 15
25 NC
RDC 14
5
C1 13
RINGRLY
Figure 7. Pin configuration, 28-pin plastic leaded chip carrier and 22-pin plastic dual-in-line package, top view.
Pin Description
PLCC: 28-pin, plastic, j-leaded chip carrier. DIP: 22-pin, dual-in-line (batwing), plastic package. Refer to figure 7.
PLCC
DIP
Symbol
1
-
RINGXSense RINGXSense is internally connected to RINGX. RINGXSense is used during manufacturing, but
requires no connection in SLIC applications, i.e. leave open.
Description
2
1
GND
Ground.
3
-
VBAT
Refer to PLCC, terminal 6 description.
4
2
VCC
+5 V power supply.
5
3
RINGRLY Ring relay driver output. Open emitter with grounded collector (npn). Sources 50 mA from ground
to a relay coil connected to a negative voltage. Must be protected by external inductive kick-back
diode. Positive voltage relay driver can be provided as a metal mask option. Contact factory for
availability.
6, 3,
5, 6, VBAT
10, 17, 17, 18
24
Battery supply voltage. Negative with respect to GND. -21 V to -58 V. All VBAT terminals
should be connected to printed circuit board traces to provide heatsinking.
7
4
RSG
Saturation guard programming resistor, RSG, connects from this terminal to VEE. Leave open for
nominal battery voltages from -24 V to -28 V. Connect to VEE for a nominal battery voltage of -48
V. For other battery voltages and for detailed information refer to section Battery Feed.
8
-
NC
No internal connection. Note 1.
9
7
E0
TTL compatible enable input. Enables the DET output, when set to logic level low and disables the
DET output, when set to logic level high. Refer to section Enable Input for detailed information.
10
-
VBAT
Refer to PLCC, terminal 6 description.
4-8
PBL 3766
PLCC
DIP
Symbol
Description
11
8
DET
Detector output. Inputs C1 and C2 select one of the two detectors to be connected to the DET output. A
logic low level at the enabled (refer to E0) DET output indicates a triggered detector condition. The DET
output is open collector with internal pull-up resistor (approximately 15 kohms) to VCC.
12
13
9
10
C2
C1
C1 and C2 are TTL compatible inputs controlling the SLIC operating states. Refer to section
Control inputs for details.
14
11
RDC
Dc loop feed is programmed by one resistor connected from this pin to the receive summing node (RSN)
A decoupling capacitor, CDC, connected from RDC to GND removes noise and other ac signals from the
battery feed control loop.
15
-
NC
No internal connection. Note 1.
16
12
RSN
Receive summing node. 1000 times the current (dc and ac) flowing into this pin equals the metallic
(transversal) current flowing from RINGX to TIPX. Programming networks for constant dc loop current,
two-wire impedance and receive gain connect to the receive summing node.
17
-
VBAT
Refer to PLCC, terminal 6 description.
18
13
VEE
-5V power supply.
19
14
VTX
Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of one. The two-wire terminating impedance programming network connects between VTX and RSN.
20
15
HPT
Tip side of ac/dc separation capacitor CHP. Other end of CHP connects to pin, HPR.
21
16
HPR
Ring side of ac/dc separation capacitor CHP. Other end of CHP capacitor connects to pin, HPT.
22
19
RD
Loop current detector programming resistor RD connects from RD to VEE. An optional filter capacitor CD
may be connected between terminal RD and ground. With the RD pin left open, the loop current detect
threshold is internally set to 8.0 mA. Refer to section Loop monitoring functions for additional information.
23
20
DT
DT is the non-inverting ring trip comparator input. The inverting comparator input is internally connected
to VEE. With DT more negative than the inverting input, the detector output, DET, is at logic level low,
indicating off-hook condition. The ring trip network connects to the DT input.
24
-
VBAT
Refer to PLCC, terminal 6 description.
25
-
NC
No internal connection. Note 1.
26
-
TIPXSense
TIPXSense is internally connected to TIPX. TIPXSense is used during manufacturing, but requires no
connection in SLIC applications, i.e. leave open.
27
28
21
22
TIPX
RINGX
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relays).
Notes
1.
Terminals marked NC are not internally connected to the chip. These terminals may be connected to ground for shielding.
4-9
PBL 3766
Functional Description and Applications Information
Transmission
General
A simplified ac model of the transmission
circuits is shown in figure 8. Circuit
analysis yields:
VTR = VTX + IL · 2RF
VTX
VRX
+
ZT
ZRX
=
(1)
IL
G2-4 =
(3)
G4-2 =
VTX is a ground referenced unity gain
version of the ac metallic voltage
between the TIPX and RINGX
terminals, i.e. VTX = 1 · VTRX.
VTR is the ac metallic voltage between tip
and ring.
is the line open circuit ac metallic
voltage.
is the ac metallic current.
RF is a current limiting resistor in the
overvoltage protection network.
ZL
is the line impedance.
ZT
determines the SLIC TIPX to RINGX
impedance.
ZRX controls four- to two-wire gain.
VRX is the analog ground referenced
receive signal.
Two-wire Impedance
To calculate ZTR, the impedance
presented to the two-wire line by the SLIC
including the fuse resistors RF, let VRX = 0.
From (1) and (2):
ZTR =
ZT
1000
+ 2RF
With ZTR and RF known ZT may be
calculated from
ZT = 1000 · (ZTR - 2RF)
Example: calculate ZT to make the
terminating impedance ZTR = 600 ohms in
series with 2.16 µF. RF = 40 ohms.
Using the expression above
ZT = 1000 · (600 +
1
- 2 · 40)
jω · 2.16 · 10-6
i.e ZT = 520 kohms in series with 2.16 nF.
It is necessary to have a high ohmic
resistor in parallel with the capacitor. This
gives a DC-feedback loop, for low
4-10
VTX
VTR
=-
VRX
VTX
ZT
·
ZRX
ZL
ZT/1000 + 2RF + ZL
=-
VRX
ZT
·
ZRX
RTX
+
VRX
=0
ZB
(EL = 0)
ZRX
·
ZT
2ZL
=
ZL + 2RF
ZL
=
ZL + 2RF
1 + jω · RL · CL
1 + jω · (RL + 2RF) · CL
A network consisting of RB1 in series
with the parallel combination of RB and CB
has the same form as the required
balance network, ZB. Basic algebra yields:
RB1 = RTX ·
RL
RB = RTX ·
CB =
= 17.6 kohms
RL + 2RF
2RF
= 2353 ohms
RL + 2RF
(RL + 2RF)2 · CL
= 0.62 µF
RTX · 2RF
Longitudinal Impedance
In the active state, a feedback loop
counteracts longitudinal voltages at the
two-wire port by injecting longitudinal
currents in opposing phase. Therefore
longitudinal disturbances will appear as
longitudinal currents and the TIPX and
RINGX terminals will experience very
small longitudinal voltage excursions, well
within the SLIC common mode range.
This is accomplished by comparing the
instantaneous two-wire longitudinal
voltage to an internal reference voltage,
VBat/2. As shown below, the SLIC appears
as 20 ohms to ground per wire to longitudinal disturbances. It should be noted,
that longitudinal currents may exceed the
dc loop current without disturbing the vf
transmission. From figure 10 the longitudinal impedance can be calculated:
VLo
=
ILo
RLo
= 20 ohms
1000
where
VLo is the longitudinal voltage
Substituting the four-wire to four-wire
gain expression, G4-4, for VRX/VTX yields
the formula for a balanced network:
ZB = -RTx·
= RTX ·
ZL + 2RF
ZT/1000 + 2RF + ZL
Hybrid Function
The PBL 3766 SLIC forms a particularly
flexible and compact line interface when
used with programmable CODEC/filters.
The programmable CODEC/filters allows
for system controller adjustment of hybrid
balance to accommodate different line
impedances without change of hardware.
It also permits the system controller to
adjust transmit and receive gains as well
as terminating impedance. Refer to programmable CODEC/filter data sheets for
design information.
The hybrid function in an implementation utilizing the uncommitted amplifier in
a conventional CODEC/filter combination
is shown in figure 9. Via impedance ZB a
current proportional to VRX is injected into
the summing node of the combination
CODEC/filter amplifier. As can be seen
from the expression for the four-wire to
four-wire gain a voltage proportional to
VRX is returned to VTX. This voltage is
converted by RTX to a current into the
same summing node. These currents
can be made to cancel by letting:
VTX
ZB = {ZL = ZTR} = RTX·
= {G4-2 = -1} = RTX·
ZT/1000 + 2RF
Four-wire to Four-wire gain
The four-wire to four-wire gain, G4-4, is
derived from (1), (2) and (3) with EL = 0:
G4-4 =
series with 2.16 µF (CL), RF = 40 ohms,
RTX = 20 kohms, G4-2 = -1. Calculate ZB.
Using the ZB formula above:
ZT/1000
=
VTR
Four-wire to Two-wire gain
The four-wire to two-wire gain, G4-2, is
derived from (1), (2) and (3) with EL = 0:
1000
where
IL
Two-wire to Four-wire gain
The two-wire to four-wire gain, G2-4, is
obtained from (1) and (2) with VRX = 0:
(2)
VTR = EL - IL · ZL
EL
frequency which ensures stability and
reduces noise.
VRX
VTX
= RTX·
ZRX ZT/1000+2RF+ZL
·
ZT
ZL + 2RF
Example: ZTR = ZL = 600 ohms (RL) in
ILo is the longitudinal current
RLo = 20 kohms sets the longitudinal
impedance
PBL 3766
TIPX
TIP
+
27/21
IL
RF
ZL
ZTR
VTR
-
1
19/14
+
+
RHP
2
-
RF
1
VTX
IL
RINGX
RING
VTX
21/16
HPR
+
EL
-
20/15
CHP
-
+
RHP
2
HPT
ZT
28/22
-
Z RX
16/12
RSN
+
VRX
I L /1000
-
PBL 3766
Figure 8. Simplified ac transmission circuit.
RFB
19/14
RTX
VTX
-
+
PBL
3766
ZT
Combination
CODEC/Filter
ZB
Z RX
16/12
VT
V RX
RSN
Figure 9. Hybrid function.
I Lo
TIPX 27/21
VLo
I Lo
1
R
VLo + VBat /2
R Lo = 20 kohms
+
R
1
I
V Lo Lo
RINGX 28/22
-
1
VLo
I Lo /1000
VBat /2
I Lo
PBL 3766
Figure 10. Longitudinal feedback loop.
4-11
PBL 3766
RFB
CHP
-5V
RRT
R1
HPT 20/15
RD
22/19
DT
23/20
RD
CRT
R2
RF -48V
Tip
Ring
RF
K1
G
K2
Note 6
21/16
19/14
18/13
U2
HPR
RTX
VTX
VEE
RB
RT
+
16/12 RSN
U3
K1
A
K2
U1
TIPX
VBAT
CTISP
RINGX
CRC
CTC
To other line D2
interfaces
D3
D1
PTC
RBat CBat
Note 1
Note 5
RSG
-48V
-5V
Ringing
(-48V +90VRMS )
KR
28/22
GND
2/1
VCC
4/2
+5V
RINGRLY
5/3
VBAT
Notes 2 & 3
RSG
7/4
RRX
RDC
27/21
14/11
13/10
12/9
11/8
9/7
Note 4
CODEC/Filter
+
RDC
CDC
C1
U1
C2
DET
E0
N/C
Digital
Interface
Notes
1. The relay coil may be connected to a negative voltage, down to the VBat limit. For VBat = -48 V
relay coils with voltage ratings from 5 V to 48 V may be used.
2. The plastic leaded chip carrier terminals 3, 6, 10, 17 and 24 shall all be connected to the VBat
supply trace to provide heat sinking.
3. The dual-in line package terminals 5, 6, 17 and 18 shall all be connected to the VBat supply trace
to provide heat sinking.
4. The plastic leaded chip carrier terminals 8, 15 and 25 are not internally connected to the chip.
These terminals may be connected to ground to provide shielding.
5. It may be desirable to include a PTC or other type of short circuit protection for the ringing
generator.
6. The ground terminals of the secondary protection should be connected to the ground terminal of
the SLIC, and to the common ground on the Printed Board Assembly with a track as short and
wide as possible, preferable a groundplane.
SLIC (Subscriber Line Interface
Circuit). PBL 3766
Combination CODEC/filter, e.g.
U2
TP3054 (or programmable
CODEC/filter, e.g. SLAC)
Secordary protection (e g Texas
U3
Instruments TISP PBL1)
Ring relay, 2C contacts. Note 1
KR
D1, D2 Diode, e.g. 1N4454
Diode, e.g. 1N4004
D3
Line resistor, 40 Ω
RF
1% match, e.g. Ericsson
Components
PBR 51XX
Resistor, 150 kΩ, 5%, 1/4 W
R1
Resistor, 2 MΩ, 5%, 1/4 W
R2
Resistor, 17.8 kΩ, %, 1/4 W
RB
Resistor, 5.1 Ω, 5%, 1/4 W
RBat
Optional. Refer to paragraph
RD
“Loop Current Detector”.
Resistor, 41.2 kΩ, 5%, 1/4 W
RDC
Resistor, 24.3 kΩ, 1%, 1/4 W
RFB
Resistor, 261 kΩ, 1%, 1/4 W
RRX
Resistor, 150 Ω, 5%, 2 W
RRT
Resistor, 0 Ω (for VBat = -48V)
RSG
Resistor, 523 kΩ, 1%, 1/4 W
RT
Resistor, 20.0 kΩ, 1%, 1/4 W
RTX
Capacitor, 0.47 µF, 20%, 100 V
CBat
Capacitor, 1.5 µF, 20%, 10 V
CDC
Capacitor, 0.033 µF, 20%, 100V
CHP
Capacitor, 0.39 µF, 20%, 100 V
CRT
CTC, CRC Capacitor, 2200 pF, 20%, 100 V
Capacitor, 220 nF, 20%, 100 V
CTISP
Figure 11. Single channel subscriber line interface with PBL 3766 and a combination CODEC/filter.
Capacitors CTC and CRC
The capacitors designated CTC and CRC in
figure 11, connected between TIPX and
ground as well as between RINGX and
ground, are recommended as an addition
to the overvoltage protection network.
Very fast transients, appearing on tip and
ring, may pass by the diode and SCR
clamps in the overvoltage protection
network, before these devices have had
time to activate and could damage the
SLIC. CTC and CRC short such very fast
transients to ground. The recommended
value for CTC and CRC is 2200 pF. Higher
capacitance values may be used, but
care must be taken to prevent
degradation of either longitudinal balance
or return loss. CTC and CRC contribute a
metallic impedance of 1/(π·f·CTC) ≈
4-12
1/(π·f·CRC), a TIPX to ground impedance
of 1/(2·π·f·CTC) and a RINGX to ground
impedance of 1/(2·π·f·CRC).
Ac - Dc Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HPT and HPR provides the separation between circuits
sensing tip-ring dc conditions and circuits
processing ac signals. A CHP value of
33 nF will position the low end frequency
response 3dB break point at 12 Hz (f3dB)
according to f3dB = 1/(2π·RHP·CHP) where
RHP ≈ 400 kΩ.
Battery Feed
Overview
The PBL 3766 SLIC synthesizes a constant current feed system. The block dia-
gram in figure 12 shows the PBL 3766
active state battery feed system. The
magnitude of the constant current is set
by a programming resistor, RDC.
To permit the line drive amplifiers to
operate without vf signal distortion even
on high resistance or open circuit loops,
a saturation guard circuit limits the loop
voltage, when the tip to ring dc voltage
approaches the available battery supply
voltage. The saturation guard function
allows the PBL 3766 to transmit and
receive vf signals with the telephone onhook.
Figure 13 shows an example of
PBL 3766 active state battery feed.
With the SLIC set to the stand-by state,
most of the circuit is disabled, including
the line drive amplifiers, to conserve power.
PBL 3766
A 2 x 900 ohm resistive feed substitutes for the active state constant current
feed.
The following paragraphs describe the
PBL 3766 battery feed system in detail.
saturation guard becomes active, VSGRef,
can be calculated from
VSGRef = 12.5 +
25000 + RSG
where
In the active state C1 = 0 and C2 = 1.
In this operating state tip to ring voltages
VTRdc less than VSGRef, cause the block
titled saturation guard in figure 12 to be
disabled, i.e. its output is equal to zero.
For this case circuit analysis yields:
RSG is a resistor connected between
terminal RSG and VEE (-5 V).
2500
RDC + 41700
= battery supply voltage
-3 V
= voltage drop across internal
transistors
5·105
Case 1: SLIC in the Active State
VTRdc < VSGRef
ILdc =
VBat
VSGRef is in volts for RSG in ohms
RSG = open circuit yields VSGRef = 12.5 V
RSG = 0 ohm yields VSGRef = 32.5 V
The loop voltage, VTRdc, as a function of
the loop resistance, RL, for VTRdc > VSGRef is
described by
1800 Ω = feed resistance (900 Ω on the
tip side, 900 Ω on the ring side)
PBL 3766 Power Dissipation and
Derating
The tip to ring short circuit total power
dissipation, PShTot, is
PShTot = ILSh · (|VBat| - ILSh · 2RF) + POnAct
where
ILSh = 2500/(41700 + RDC) is the short
circuit loop current
POnAct is the active state on-hook dissipa16.66 + 5.00·105/(25000 + RSG)
· RL
tion, typically 160 mW VBat = -48V
where
RL + (RDC + 41700) / 600
The permissible maximum device
ILdc = the constant loop current. ILdc is in
from which the open loop voltage (IL = 0)
dissipation is 1.5 W. The maximum
amperes for RDC in ohms.
is calculated to
allowable junction temperature is 140 °C
RDC = the programming resistance, in
5.00·105
for normal reliability requirements and
ohms, which sets the constant loop VTRdc = 16.66 +
110 °C for extreme reliability requirements.
25000 + RSG
current magnitude.
The junction temperature is calculated
For RSG = open circuit, the on-hook tip
When the desired constant loop current
from
to ring dc voltage is 16.7 V, which is
is known, RDC is calculated from
TJ = PShTot · (θJP + θPA) + TAmb, TJ < 140 °C
compatible with VBat in the -24 V to -28 V
2500
where
- 41700
RDC =
range.
ILdc
For RSG = 0 ohm, the on-hook tip to ring θ = θ
= θJP22dip is the thermal
JP
JP28plcc
dc voltage is 36.7 V, which is compatible
Capacitor CDC, connected between the
resistance from junction to all VBAT
RDC terminal and ground, removes noise with VBat in the -42 V to -58 V range.
terminals, typically 10 °C/W θPA is the
For intermediate battery voltage values, thermal resistance from all VBAT terminals
and vf signals from the battery feed
VBat, RSG can be calculated from
control loop. CDC is calculated according
to ambient. The θPA value will be dependto
5.00·105
ent on line-card thermal design.
RSG =
- 25000
TAmb is the ambient temperature in °C.
1
 1
1 
VTRdc -16.66
· 
+

CDC =
2π · fDC  41700 RDC 
Loop Monitoring Functions
where
where
RSG is in ohms for VTRdc in volts
Overview
fDC = 5 Hz
VTRdc is the open loop tip to ring
The PBL 3766 SLIC contains detectors for
voltage.Let VTRdc = |VBat| - 8 V to allow
RDC = constant current programming
loop current and ring trip. These two
distortion free transmission of a 3.1 Vpk vf detectors report their status via the shared
resistance in ohms
signal in the on-hook mode. The 8 V
DET output. A triggered detector is
CDC = filter capacitor in farads
margin may be reduced if a vf signal of
indicated by a logic low level at the DET
Case 2: SLIC in the Active State
less than 3.1 Vpk is to be transmitted in
output. The detector to be connected to
VTRdc > VSGRef
the on-hook mode.
the DET output is selected via the control
interface C1 and C2. Refer to section
In the active state C1 = 0 and C2 = 1.
Case 3: SLIC in the Stand-by State
Control Inputs for a description of the
When the tip to ring dc voltage
In the stand-by state C1 = 1 and C2 = 1.
control interface. Enable input E0 sets the
approaches the VBat supply voltage, the
With
the
SLIC
operating
in
the
stand-by,
DET
output to either active or high impedsaturation guard block shown in figure 12
power saving state the tip and ring drive
ance state.
is engaged and will limit the two-wire
amplifiers are disconnected and a
voltage to a small additional increase
Loop Current Detector
resistive battery feed is engaged. The
beyond the saturation guard threshold,
The loop current detector is connected to
loop current can be calculated from
VSGref. This leaves a sufficient voltage
the DET output in the stand-by (C2, C1 =
VBat - 3 V
margin to the VBat supply to maintain
1, 1) and the active (C2, C1 = 1, 0) states.
ILdc ≈
distortion free vf transmission through the
RL + 1800 Ω
Refer to figure 14.
line drive amplifiers. The saturation guard
The loop current value, I LThOff, at which
where
feature makes on-hook transmission
the loop current detector changes from
= loop current
ILdc
possible in the active state.
indicating on-hook to indicating off-hook is
The tip to ring voltage at which the
RL
= loop resistance
internally programmed to 8.0 mA.
VTRdc =
4-13
PBL 3766
The internally set loop current detector
threshold, ILThOn, for the off-hook to onhook transition is 7.3 mA.
An external resistor, RD, may be
connected from terminal RD to VEE to
increase the loop current detector
thresholds. When the desired on-hook to
off-hook loop current threshold, ILThOff, is
known, the RD value is calculated from
Ring Trip Detector
Ring trip detection is accomplished by
monitoring the two-wire line for presence
of dc current while ringing is applied.
When the subscriber goes off-hook during
ringing, dc loop current starts to flow. The
SLIC ring trip comparator detects this
current flow via an interface network. The
DT comparator input is connected to pin
1
23/20. The other comparator input is
RD =
internally connected to VEE. The result of
ILThOff /500 - 1/62500
the comparison is presented at the DET
where RD is in ohms for ILThOff in amperes
output with logic low level indicating offhook. The ring trip comparator is
The off-hook to on-hook loop current
automatically connected to the DET
detector threshold, ILThOn, for the selected
output, when the SLIC control inputs are
RD value is calculated from
set to the ringing state (C2, C1 = 0, 1).
 1
1 
+

ILThOn = KLThOn · 
When off-hook during ringing is detected,
 RD 62500 
the line card or system controller will
where
proceed to disconnect the ringing source
ILThOn is in amperes for RD in ohms.
(software ringtrip) by re-setting the control
input logic states. Alternatively, the DET
ILThOn > 7.3 mA, KLThOn = 455 V
output may be monitored by circuits on
The on-hook to off-hook loop current
the line card, which perform the ringtrip
detector threshold, ILThOff, for a specific RD
function (hardware ringtrip).
value is calculated from
The ringing source may be balanced or
 1
1 
unbalanced,
superimposed on the VBat
ILThOff = KLThOff · 
+

supply voltage. A ring relay, energized by
 RD 62500 
the SLIC ring relay driver, connects the
where
ringing source to tip and ring. For unbalILThOff is in amperes for RD in ohms.
anced ringing systems the loop current
ILThOff > 8.0 mA, KLThOff = 500 V
sensing resistor, RRT, is placed in series
with the return lead to ground.
With a lower voltage battery it may be
Figures 15 and 16 show examples of
desirable to decrease the loop current
detector thresholds. For more information unbalanced and balanced ringing
systems. For either ringing system the
on this issue, please contact the factory.
ringtrip detection function is based on a
During dial pulsing the loop current
polarity change at the inputs of the ringtrip
detector is aided by a speed-up circuit,
acting on the RDC output at loop closures. comparator.
In the unbalanced case the dc voltage
The speed-up circuit will charge the CDC
drop
across resistor RRT is zero, as long
capacitor at a more rapid rate than that set
as
the
telephone remains on-hook. With
by the (CDC· RDC· 41700)/(RDC+ 41700)
time constant, resulting in the loop current the telephone off-hook during ringing, dc
loop current will flow, causing a voltage
reaching the detector threshold value
drop across RRT. The RRT voltage is
faster and therefore minimizing dial pulse
applied to the comparator input DT via
distortion.
resistor R1. R2 shifts the voltage level to
Loop Current Detector - Filter Capacitor be compatible with the inverting input VEE
reference voltage. CRT removes part of
To increase the loop current detector
the ac component of the ringing signal.
noise immunity, a filter capacitor may be
The inverting comparator input is
added from terminal RD to ground. A
biased
at VEE, which is more negative
suggested value for CD is
than DT when the telephone is on-hook
RD + 62500
and is more positive than DT when the
CD =
2π · (RD · 62500) · f3dB
telephone goes off-hook during ringing.
Complete removal of the ringing signal
where
ac component at the DT input is not
CD is in farads for RD in ohms f3dB = 500 Hz
necessary. Some residual ac component
at the DT input may, under certain
Note that CD may not be required if the
operating conditions, cause the DET
DET output is software filtered.
4-14
output to toggle between the on-hook and
off-hook states at the ringing frequency.
However, with the telephone off-hook, the
DET output will be at logic low level for
more than half the time. Therefore, by
sampling the DET output, a software
routine can discriminate between on-hook
and off-hook through examination of the
duty cycle. Full removal of the ringing
frequency from the DT input, while
maintaining ringtrip within required time
limits (approximately < 100 ms), usually
mandates a second order filter rather than
the first order shown in figure 15. The
software approach minimizes the number
of line card components.
In the balanced ringing system shown
in figure 16, RRT1 and RRT2 are the ringing
feed and loop current sensing resistors.
With the telephone on-hook, no dc loop
current flows to cause a dc voltage drop
across resistor RRT1. Voltage divider R1, R2
and R3 biases the ringtrip comparator
input DT to be more positive than VEE
during on-hook. With the telephone offhook during ringing dc loop current will
flow, causing a voltage drop across
resistor RRT1, which will make comparator
input DT more negative than VEE. This will
set the DET output to logic low level,
indicating ringtrip condition. Capacitors C1
and C2 filter the ringing voltage at the
comparator input. With component values
according to figure 16, 20 Hz ringing will
be attenuated by 20 dB and 30 Hz ringing
will be attenuated by 23 dB before reaching the DT input.
Relay Driver
The PBL 3766 SLIC incorporates a ring
relay driver designed as open emitter with
grounded collector (npn) having a current
sourcing capability of 50 mA. The relay
coil must be connected to a negative
voltage ≤ |VBat|. An external inductive kickback clamp diode must be employed to
protect the drive transistor.
Control Inputs
Overview
The PBL 3766 SLIC has two TTL
compatible control inputs, C1 and C2. A
decoder in the SLIC interprets the control
input conditions and sets up the commanded operating state.
Open Circuit State (C2, C1 = 0, 0)
In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as
other circuit blocks are powered down.
PBL 3766
TIPX
I Ldc
27/21
+
VTR
RL
RINGX
-2.5 V
GND
-
14/11
VTR
1
41.7 kΩ
I Ldc
+
Comp
Figure 12. Battery feed (C2, C1 = 1, 0;
active state).
5·105
VSGRef = 12.5 +
RSG + 25 kΩ
VSG = -7.50 –
C DC
VBat
28/22
VSG Ref RSG
RDC
VTR > VSG Ref
1
VTR < VSG Ref
0
RDC
7/4
0.6
R SG
VSG
Saturation Guard
V EE
I Ldc
1000
16/12
RSN
PBL 3766
3.0·105
RSG + 25 kΩ
I L (mA)
RDC = 21.0 kohms
40
RDC = 41.2 kohms
30
RDC = 82.5 kohms
20
10
0
Figure 13. PBL 3766 loop feed examples.
500
0
1000
R L (ohms)
RSG = 0 ohms
1500
2000
VBat = -58 V to -42 V
Ring trip
Comparator
I LTIPX
TIPX
RINGX
27/21
28/22
I LTIPX - I LRINGX
2 K
+
62.5 kΩ
VEE
PBL 3766
RD =
1
,
ILThOff /KLThOff - 1/62500
MUX
11/8
9/7
DET
E0
1.25V
22/19 18/13
RD
ILThOff = 8.0 mA for RD → ∞
For ILThOff > 8.0 mA:
C1
C2
VCC
2-Wire
Interface
I LRINGX
Figure 14. Loop current detector.
On-hook to off-hook loop current
threshold, ILThOff :
13/10
12/9
Input
Decoder
CD
VEE
RD
-5V
KLThOff = 500 V (includes factor K)
4-15
PBL 3766
This causes the SLIC to present a high
impedance to the line. Power dissipation
is at a minimum. No detectors are active.
Ringing State (C2, C1 = 0, 1)
The ring relay driver, RINGRLY, is activated and the ring trip comparator is
connected to the detector out-put, DET.
The TIPX and RINGX terminals are in the
high impedance state and signal transmission is inhibited.
Active State (C2, C1 = 1, 0)
TIPX is the terminal closest to ground
potential and sources loop current, while
RINGX is the more negative terminal and
sinks loop current. Vf signal transmission
is normal. The loop current detector is
activated and connected to the DET output.
Stand-By State (C2, C1 = 1, 1)
In the stand-by state the line drive amplifiers are disconnected. The loop feed is
converted to resistive form according to
IL ≈
VBat - 3 V
RL + 1800 Ω
where
IL
= loop current (A)
VBat = battery supply voltage (V)
RL = loop resistance (ohm)
The short circuit loop current (ILSh) for
VBat = -48V is then limited to ILSh ≈ 25.0 mA.
The loop current detector is activated in
the stand-by state and is gated to the DET
output.
Table 1 summarizes the above
description of the control inputs.
CRT
RRT
R1
DT
23/20
DR
R2
+
To DET
-
VEE
TIP
PBL 3766
E RG
KR
Figure 15. Example ring trip network,
unbalanced ringing.
VBat
RING
Note: Ericsson Components unbalanced
ring trip network PBA 3310 contains a
two-pole filter.
E RG+
RRT1
150Ω
DT
R1
150kΩ
RRT2
150Ω
R2
150kΩ
C1
470nF
23/20
DR
C2
470nF
R3
3.1MΩ
+
To DET
-
VEE
E RG-48V
-48V
TIPX
TIP
RF1
RF2
RING
KR
27/21
Protection
RINGX
28/22
PBL 3766
Figure 16. Example ring trip network,
balanced ringing.
4-16
PBL 3766
Enable Input (E0)
dissipators, when transients are clamped
TTL compatible enable input E0 controls and of being fuses, when the line is
exposed to a power cross. Ericsson
the function of the DET output.
E0, when set to logic level low, enables Components AB offers a series of thick
the DET output, which is a collector output film resistors networks (e g PBR 51-series
and PBR 53-series) designed for this
with internal pull-up resistor (approx.
application.
15 kohms) to VCC. A DET output at logic
Also devices with a build in resetable
level low indicates triggered detector
fuse
function is offered (e g PBR 52condition (loop current above threshold
series)
including positive temperature
current or telephone off-hook during
coefficient (PTC) resistors, working as
ringing). A DET output at logic level high
resetable fuses, in series with thick film
indicates a non triggered detector
resistors. Note that it is important to
condition.
E0, when set to logic level high disables always use PTC's in series with resistors
the DET output; i.e. it appears as a resist- not sensitive to temperature, as the PTC
will act as a capacitance for fast
or connected to VCC.
Table 2 summarizes the above descrip- transients and therefore the ability to
protect the SLIC will be reduced.
tion of the enable input.
If there is a risk for overvoltages on the
Overvoltage Protection
VBat terminal on the SLIC, then this
terminal should also be protected.
The PBL 3766 SLIC must be protected
against overvoltages and power crosses. Overtemperature Protection
Refer to Maximum Ratings, TIPX and
A ring lead to ground short circuit fault
RINGX terminals for maximum allowable
condition, as well as other improper
continuous and transient voltages, that
operating modes, may cause excessive
may be applied to the SLIC. The circuit
shown in figure 11 utilizes series resistors SLIC power dissipation. If junction
temperature increases beyond 160 °C,
(RF, RF) together with a programmable
the
temperature guard will trigger, causing
overvoltage protector (e g Texas Instrument TISP PBL1), serving as a secondary the SLIC to be set to a high impedance
state. In this high impedance state power
protection.
dissipation is reduced and the junction
The protection network in figure 11 is
designed to meet requirements in CCITT temperature will return to a safe value.
Once below 140 °C junction temperature
K20, Table 1. The TISP PBL1 is a dual
the SLIC is returned back to its normal
forward-conducting buffered p-gate
overvoltage protector. The protector gate operating mode and will remain in that
state assuming the fault condition has
references the protection (clamping)
voltage to negative supply voltage (i e the been removed.
Table 1. PBL 3766 operating states
battery voltage, V ). As the protection
Power-up Sequence
The voltage at pin VBAT sets the substrate voltage, which must at all times be
kept more negative than the voltage at
any other terminal. This is to maintain
correct junction isolation between devices
on the chip. To prevent possible latch-up,
the correct power-up sequence is to
connect ground and VBat, then other
supply voltages and signal leads. Should
the VBat supply voltage be absent, a diode
with a 2 A current rating, connected with
its cathode to VEE and anode to VBat,
ensures the presence of the most
negative supply voltage at the VBAT
terminals.
The VBat voltage should not be applied
at a faster rate than ∂VBat/∂t = 4 V/µsec or
with a time constant formed by a 5.1 ohm
resistor in series with the VBAT pin and a
0.47 microfarad capacitor from the VBAT
pin to ground. One resistor may be
shared by several SLICs.
Printed Circuit Board Layout
Care in PCB layout is essential for proper
function. The components connecting to
the RSN input should be placed in close
proximity to that pin, such that no
interference is injected into the RSN
terminal. A ground plane surrounding the
RSN pin is advisable. The CHP capacitor
should be placed close to terminals HPT
and HPR to avoid un-wanted disturbances.
Bat
voltage will track the negative supply
voltage the overvoltage stress on the
SLIC is minimised.
Positive overvoltages are clamped to
ground by an internal diode. Negative
overvoltages are initially clamped close to
the SLIC negative supply rail voltage. If
sufficient current is available from the
overvoltage, then the protector will crowbar into a low voltage on-state condition,
clamping the over-voltage close to ground.
A gate decoupling capacitor, CTISP is
needed to carry enough charge to supply
a high enough current to quickly turn on
the thyristor in the protector. Without the
capacitor even the low inductance in the
track to the VBat supply will limit the
current and delay the activation of the
thyristor clamp.
The fuse resistors RF serve the dual
purposes of being non-destructive energy
State
number
C2
C1
SLIC
operating state
Active detector
DET Output Note 1.
1
2
3
4
0
0
1
1
0
1
0
1
Open circuit
Ringing
Active
Stand-by
No active detector
Ring trip detector
Loop curr. detector
Loop curr. detector
Logic level high
Ring trip status
Loop current status
Loop current status
Note
1. E0 = 0, i.e. the DET output is enabled. A logic low level at the DET output
indicates a triggered detector.
Table 2. Enable input E0
Enable
state
E0
DET output status
Active detector
1
0
Active
2
1
High impedance
Note 2.
Loop current or ring trip detector
Note 1.
None
Notes
1. Detector selected according to Table 1.
2. In the high impedance state the DET output appears as a 15 kohms resistor to VCC
4-17
PBL 3766
Ordering Information
Package
Temp. Range
Part No.
Plastic DIP 22 pin
0 °C to 70 °C
PBL 3766N
Plastic DIP 22 pin
0 °C to 70 °C
PBL 3766/6N
PLCC 28 pin
0 °C to 70 °C
PBL 3766QN
PLCC 28 pin
0 °C to 70 °C
PBL 3766/6QN
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted
by implication or otherwise under any patent or patent
rights of Ericsson Components AB. These products
are sold only according to Ericsson Components AB'
general conditions of sale, unless otherwise confirmed
in writing.
Specifications subject to change without
notice.
1522-PBL 3766 Uen Rev. B
© Ericsson Components AB
September 1997
This product is an original Ericsson product
protected by US, European and other
patents.
Ericsson Components AB
S-164 81 Kista-Stockholm, Sweden
Telephone: (08) 757 50 00
4-18