HC5503PRC ® Data Sheet June 2004 Low Cost SLIC For Large Telecom Switches FN4806.3 Features • Wide Operating Battery Range (-40V to -58V) The HC5503PRC is a low cost SLIC optimized for large Telecom switches. It combines a flexible voltage feed architecture with the Intersil latch-free DI bonded wafer process, to provide a low component count, carrier class solution at very low cost. The re-configurable design permits simple, economical solutions for campus-wide call center and PBX applications. External components can be used in conjunction with the high battery voltage capability to meet the complex impedance and long loop drive requirements of Central Office switches, worldwide. • Single Additional +5V Supply • 30mA Short Loop Current Limit • Ring Relay Driver • Switch Hook and Ring Trip Detect • Low On-Hook Power Consumption • On-Hook Transmission • ITU-T Longitudinal Balance Performance • Loop Power Denial Function Ordering Information TEMP. PART NUMBER RANGE (°C) PACKAGE PKG. DWG. # • Thermal Protection • Supports Tip, Ring or Balanced Ringing Schemes HC5503PRCB 0 to 70 24 Ld SOIC M24.3 • Low Profile SO and QFN Surface Mount Packaging HC5503PRCBZ (Note) 0 to 70 24 Ld SOIC (Pb-free) M24.3 • Pb-free Available HC5503PRCBZ96 (Note) 0 to 70 24 Ld SOIC Tape & Reel M24.3 (Pb-free) HC5503PRCR 0 to 70 32 Ld 7x7 QFN L32.7x7 HC5503PRCRZ (Note) 0 to 70 32 Ld 7x7 QFN (Pb-free) L32.7x7 HC5503PRCRZ96 (Note) 0 to 70 32 Ld 7x7 QFN Tape & Reel (Pb-free) L32.7x7 Applications • Central Office, PBX, Call Centers • Related Literature - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 1999, 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HC5503PRC Block Diagram RING RELAY DRIVER RD RFS 4-WIRE INTERFACE VF SIGNAL PATH RING TRIP DETECTOR C2 TX RX TIP TF 2-WIRE INTERFACE RING LOOP CURRENT DETECTOR SHD RS RF THERMAL LIMIT LOGIC INTERFACE RC PD VBAT VCC BIAS AGND + - BGND DGND 2 C1 OUT +IN -IN HC5503PRC Absolute Maximum Ratings Thermal Information Maximum Continuous Supply Voltages (VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V (VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V (VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V Thermal Resistance (Typical, Note 2, 3) θJA (°C/W) 24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 32 Lead 7x7 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0°C to 70°C Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V Positive Supply Voltage (VB+) . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Negative Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . -40V to -58V High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V Subscriber Loop Resistance . . . . . . . . . . . . . . . . . . . 200Ω - 1800Ω Die Characteristics Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. θJA for the QFN package is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features including conductive thermal vias. See Tech Brief TB379 and TB389 for additional information and board layout consideration Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical Parameters. TA = 25°C. Min-Max Parameters are Over Operating Temperature Range PARAMETER CONDITIONS MIN TYP MAX UNITS On Hook Power Dissipation ILONG = 0 (Note 4) - 113 - mW Off Hook Power Dissipation RL = 600Ω, ILONG = 0 (Notes 3, 4) - 750 - mW On Hook IB+ RL = ∞, ILONG = 0 - 1.4 - mA Off Hook IB+ RL = 600Ω, ILONG = 0 - 2.8 - mA On Hook IB- RL = ∞, ILONG = 0 - 2.2 - mA Off Hook IB- RL = 600Ω, ILONG = 0 - 31 - mA Off Hook Loop Current RL = 1800Ω (ILOOP = 0) 18 - - mA Off Hook Loop Current RL = 200Ω, ILONG = 0 (Note 3) 25 30 35 mA TIP to Ground - 27 - mA RING to Ground - 55 - mA TIP to RING - 30 - mA TIP and RING to Ground - 69 - mA Fault Currents Ring Relay Drive VOL IOL = 62mA - 0.2 0.5 V Ring Relay Driver Off Leakage VRD = 12V, RC = 1 = HIGH, TA = 25°C - - 100 µA DC Ring Trip Threshold 8.1 10.8 13.5 mA Switch Hook Detection Threshold 5.0 7.5 10 mA Loop Current During Power Denial RL = 200Ω - 3.2 - mA Dial Pulse Distortion (Note 4) 0 - 0.5 ms Receive Input Impedance (Note 4) - 110 - kΩ Transmit Output Impedance (Note 4) - 10 20 Ω 3 HC5503PRC Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical Parameters. TA = 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS - 15.5 - dB ERL - 24 - dB SRL HI - 31 - dB 53 58 - dB 2-Wire On Hook (Note 4) 53 58 - dB 4-Wire Off Hook 50 58 - dB - ±0.05 ±0.2 dB - ±0.02 ±0.05 dB - 1 5 dBrnC - -89 -85 dBm0p - - 2 µs 30 40 - dB 1.5 - - VPEAK +3 to -40dBm - - ±0.05 dB -40 to -50dBm - - ±0.1 dB -50 to -55dBm - - ±0.3 dB 15 - - dB VB+ to Transmit 15 - - dB VB- to 2-Wire 15 - - dB VB- to Transmit 15 - - dB 30 - - dB VB+ to Transmit 30 - - dB VB- to 2-Wire 30 - - dB VB- to Transmit 30 - - dB - - ±100 µA Logic ‘0’ VIL - - 0.8 V Logic ‘1’ VIH 2.0 - 5.5 V 2-Wire Return Loss (Referenced to 600Ω + 2.16µF), RP = RS = 150Ω (Note 4) SRL LO Longitudinal Balance 1VRMS 200Hz - 3400Hz, (Note 4) IEEE Method 0°C ≤ TA ≤ 75°C, RP = RS = 150Ω 2-Wire Off Hook (Note 4) Insertion Loss 2-Wire to 4-Wire, 4-Wire to 2-Wire At 1kHz, 0dBm Input Level, Referenced 600Ω, RP = RS = 150Ω Frequency Response 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level, RP = RS = 150Ω (Note 4) Idle Channel Noise RP = RS = 150Ω (Note 4) 2-Wire to 4-Wire, 4-Wire to 2-Wire RP = RS = 150Ω (Note 4) Absolute Delay 2-Wire to 4-Wire, 4-Wire to 2-Wire Trans Hybrid Loss Balance Network Set Up for 600Ω Termination at 1kHz, RP = RS = 150Ω (Note 4) Overload Level VB+ = +5V, RP = RS = 150Ω (Note 4) 2-Wire to 4-Wire, 4-Wire to 2-Wire Level Linearity 2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4) Power Supply Rejection Ratio At 1kHz, (Note 4) Referenced to 0dBm Level, RP = RS = 150Ω RP = RS = 150Ω (Note 4) 30 - 60Hz, RL = 600Ω VB+ to 2-Wire VB+ to 2-Wire 200 - 16kHz, RL = 600Ω, RP = RS = 150Ω Logic Input Current (RS, RC, PD) 0V ≤ VIN ≤ 5V Logic Inputs Logic Outputs Logic ‘0’ VOL ILOAD 800µA, VB+ = 5V - 0.1 0.5 V Logic ‘1’ VOH ILOAD 40µA, VB+ = 5V 2.7 - 5.0 V 4 HC5503PRC Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical Parameters. TA = 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS Input Offset Voltage - ±5 - mV Input Offset Current - ±10 - nA Input Bias Current - 20 - nA UNCOMMITTED OP AMP SPECIFICATIONS Differential Input Resistance (Note 4) - 1 - MΩ Output Voltage Swing RL = 10K, VB+ = 5V - ±3 - VPEAK Output Resistance AVCL = 1 (Note 4) - 10 - Ω Small Signal GBW (Note 4) - 1 - MHz NOTES: 4. ILONG = Longitudinal Current. 5. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. Pin Descriptions 24 PIN DIP/SOIC 7x7 QFN SYMBOL DESCRIPTION 1 28 TIP An analog input connected to the TIP (more positive) side of the subscriber loop through a sense resistor (RS) and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. 2 31 RING An analog input connected to the RING (more negative) side of the subscriber loop through a sense resistor (RS) and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. 3 32 RFS Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into the line at this node and RF is isolated from RFS via a relay. 4 1 VB+ 5 3 C1 Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VB-. Typical value is 0.3µF, 30V. 6 4 DG Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC microcircuit. 7 5 RS Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to 5V. 8 6 RD Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. 9 7, 8 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a sense resistor (RS). Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 10 9, 10 RF Ring Feed - A low impedance analog output connected to the RING terminal through a sense resistor (RS). Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 11 11 VB- Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to -58V. Frequently referred to as “battery”. 12 12 BG Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. 13 13 SHD 14 14,19 NC 5 Positive Voltage Source - Most positive supply. VB+ is typically. Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents exceeding the switch hook threshold. Used during production test. Leave disconnected. HC5503PRC Pin Descriptions (Continued) 24 PIN DIP/SOIC 7x7 QFN SYMBOL DESCRIPTION 15 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled, the ring feed voltage collapses to the tip feed voltage (~4V). The DC feed is disabled, but the AC transmission is maintained. The switch hook detect (SHD) is not necessarily valid, and the relay driver (RD) output is disabled. 16 16 RC Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). 18 20 OUT 19 21 -IN The inverting analog input of the spare operational amplifier. 20 22 +IN The non-inverting analog input of the spare operational amplifier. 21 23 RX Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals. 22 25 C2 Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This capacitor is required for the proper operation of ring trip detection. Recommended value 0.82µF ±10% 10V non-polarized. 23 26 AG Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. 24 27 TX Transmit Output, Four Wire Side - A low impedance analog output proportional to the loop current. Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. 2, 17, 18,24, 29, 30, NC No internal connection. 17 NC Leave disconnected. The analog output of the spare operational amplifier. NOTE: All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. 6 HC5503PRC Functional Diagram RING SYNC RING COMMAND RC RD RP 1/2 RING RELAY TIP RING TRIP RS RING CONTROL SHD SWITCH HOOK DETECTION LOOP MONITORING TIP DIFF AMP + RS TX TRANSMIT OUTPUT TF 2-WIRE LOOP VBSECONDARY PROTECTION BATTERY FEED VB- OUT +1 BG +IN RF LOOP CURRENT LIMITER RFS 1/2 RING RELAY + LINE DRIVERS RING VOLTAGE RING POWER DENIAL PD VBRS: 100Ω; 1/2W to 2W depending on surge requirements RP: 50Ω; 1/2W to 2W depending on surge requirements 7 -IN RS RING RP OP AMP -1 SLIC MICROCIRCUIT RX RECEIVE INPUT HC5503PRC SLIC FUNCTIONAL SCHEMATIC SOIC PIN NUMBERS SHOWN 21 22 11 12 23 6 4 20 19 18 RX C2 VBAT BAT GND ANA GND DIG GND VB+ + - OUT VB+ VB+ VB1 VB2 VB3 VB4 VB5 5V VOLTAGE AND CURRENT BIAS NETWORK A-400 TIP FEED AMP TF 9 R17 + V B+ VBAT VB2 RING TRIP DETECTOR R12 R7 TIP 1 VB+ QD3 QD36 RING FEED SENSE R9 3 R22 R11 RING R4 2 R1 + VBAT V + VBAT R23 B GK R20 VBAT + IB7 - - SWITCH HOOK DETECTOR R14 QD27 R18 QD28 16 RFC VB5 - PD VB5 15 + + VBAT RC THERMAL LIMITING LOAD CURRENT LIMITING IB2 A-300 RING FEED AMP 10 13 VB1 R21 - IB6 VBAT/2 REFERENCE VB2 R19 VBAT IB5 R13 VBAT VBAT C1 TX RS RD 5 24 7 8 8 17 SHD SH + R6 R16 VBAT NC STTL AND LOGIC INTERFACE VB+ VBAT IB6 R2 14 + VB3 A-100 TRANSV’L I/V AMP NC GND SHORTS CURRENT LIMITING IB1 IB8 VB+ + R15 VB4 VBAT R5 R3 RF V B+ A-200 LONG’L I/V AMP R10 5V IB10 VB+ 5V - R8 VBAT IB3 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11 - IB4 A-500 OP AMP HC5503PRC LOGIC GATE SCHEMATIC GK LOGIC BIAS 2 1 DELAY 4 SH 6 8 7 9 3 5 12 16 10 13 11 RELAY DRIVER 14 15 TTL TO STTL TTL TO STTL TTL TO STTL TO R21 A STTL TO TTL C B A B RS RC PD C RD SHD SCHOTTKY LOGIC Surge Protection The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. The voltage withstand capability of pins ‘Tip’, ‘Ring’ and ‘RFs’ is ±450V with respect to ground, as shown in Table 1. TABLE 1. PERFORMANCE (MAX) UNITS Longitudinal Surge 10µs Rise/ 1000µs Fall ±450 (Plastic) VPEAK Metallic Surge 10µs Rise/ 1000µs Fall ±450 (Plastic) VPEAK T/GND R/GND 10µs Rise/ 1000µs Fall ±450 (Plastic) VPEAK 50/60Hz Current T/GND R/GND 11 Cycles Limited to 10ARMS 315 (Plastic) VRMS PARAMETER TEST CONDITION 9 This device is intended for use with an appropriate secondary protection circuit scheme. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS , 15mARMS per leg, without any performance degradation. HC5503PRC Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) N 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e µα B S 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 24 0o 24 8o 0o 7 8o 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 HC5503PRC Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 2X L32.7x7 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKC ISSUE C) 0.15 C A MILLIMETERS D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E 0.15 C B 0.15 C A B TOP VIEW A / / 0.10 C C 0.08 C SEATING PLANE 9 4X P 0.90 1.00 - - 0.05 - A2 - - 1.00 9 A3 0.20 REF 0.23 0.28 - 9 0.38 5, 8 D 7.00 BSC - D1 6.75 BSC 9 4.55 4.70 4.85 7, 8 E 7.00 BSC - E1 6.75 BSC 9 4.55 4.70 4.85 0.65 BSC 7, 8 - k 0.25 - - - L 0.50 0.60 0.75 8 L1 - - 0.15 10 N 32 2 3 Nd 8 Ne 8 8 P - - 0.60 9 NX k θ - - 12 9 D2 7 D2 2 N 3 Rev. 4 8/03 4X P NOTES: 1 (DATUM A) 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2 3 6 INDEX AREA N e (Ne-1)Xe REF. E2 E2/2 NX L 8 0.80 0.10 M C A B 5 NX b (DATUM B) A1 A3 SIDE VIEW NOTES A e A2 MAX A1 E2 0 4X TYP D2 9 2X 2X MIN b E/2 E1 SYMBOL 2. N is the number of terminals. 7 3. Nd and Ne refer to the number of terminals on each D and E. 8 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 9 CORNER OPTION 4X (Nd-1)Xe REF. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. BOTTOM VIEW A1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b 5 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. C L 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. SECTION "C-C" C L L1 10 L L1 e 10 L e C C TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 11 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.