DATASHEET

ISL8483, ISL8485, ISL8488,
ISL8489, ISL8490, ISL8491
Data Sheet
February 16, 2016
5V, Low Power, High Speed or Slew Rate
Limited, RS-485/RS-422 Transceivers
The Intersil RS-485/RS-422 devices are BiCMOS 5V
powered, single transceivers that meet both the RS-485 and
RS-422 standards for balanced communication. Unlike
competitive devices, this Intersil family is specified for 10%
tolerance supplies (4.5V to 5.5V).
The ISL8483, ISL8488, and ISL8489 utilize slew rate limited
drivers which reduce EMI, and minimize reflections from
improperly terminated transmission lines, or unterminated
stubs in multidrop and multipoint applications.
Data rates up to 5Mbps are achievable by using the
ISL8485, ISL8490, or ISL8491, which feature higher slew
rates.
FN6046.9
Features
• Specified for 10% Tolerance Supplies
• Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV
• High Data Rates . . . . . . . . . . . . . . . . . . . . . . up to 5Mbps
• Slew Rate Limited Versions for Error Free Data
Transmission at 250kbps (ISL8483, ISL8488, ISL8489)
• Single Unit Load Allows up to 32 Devices on the Bus
• 1nA Low Current Shutdown Mode (ISL8483)
• Low Quiescent Current:
- 160A (ISL8483, ISL8488, ISL8489)
- 500A (ISL8485, ISL8490, ISL8491)
• -7V to +12V Common Mode Input Voltage Range
All devices present a “single unit load” to the RS-485 bus,
which allows up to 32 transceivers on the network.
• Three State Rx and Tx Outputs (Except ISL8488,
ISL8490)
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high Rx output if Rx inputs are floating.
• 30ns Propagation Delays, 5ns Skew (ISL8485, ISL8490,
ISL8491)
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
The ISL8488 - 91 are configured for full duplex (separate Rx
input and Tx output pins) applications. The ISL8488 and
ISL8490 are offered in space saving 8 lead packages for
applications not requiring Rx and Tx output disable functions
(e.g., point-to-point). Half duplex configurations (ISL8483,
ISL8485) multiplex the Rx inputs and Tx outputs to allow
transceivers with Rx and Tx disable functions in 8 lead
packages.
• Full Duplex and Half Duplex Pinouts
• Operate from a Single +5V Supply (10% Tolerance)
• Current Limiting and Thermal Shutdown for driver
Overload Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Factory Automation
• Security Networks
• Building Environmental Control Systems
• Industrial/Process Control Networks
• Level Translators (e.g., RS-232 to RS-422)
• RS-232 “Extension Cords”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2003, 2005, 2006, 2016. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
HALF/FULL NO. OF DEVICES
DUPLEX
ALLOWED ON BUS
DATA
RATE
(Mbps)
SLEW-RATE
LIMITED?
RECEIVER/
DRIVER
ENABLE?
QUIESCENT
ICC (A)
LOW POWER
SHUTDOWN?
PIN
COUNT
ISL8483
(No longer
available or
supported)
Half
32
0.25
Yes
Yes
160
Yes
8
ISL8485
Half
32
5
No
Yes
500
No
8
ISL8488 (No
longer
available or
supported)
Full
32
0.25
Yes
No
160
No
8
ISL8489 (No
longer
available or
supported
Full
32
0.25
Yes
Yes
160
No
14
ISL8490
Full
32
5
No
No
500
No
8
ISL8491
Full
32
5
No
Yes
500
No
14
Ordering Information
PART NUMBER
PART MARKING
ISL8483IPZ (Note) (No longer
available, recommended
replacement ISL3152EIPZ)
ISL8483IPZ
ISL8485CBZ (Note)
8485CBZ
ISL8485CBZ-T (Note)
8485CBZ
ISL8485CPZ (Note)
ISL8485CPZ
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
-40 to 85
8 Ld PDIP* (Pb-free)
E8.3
0 to 70
8 Ld SOIC(Pb-free)
M8.15
8 Ld SOIC Tape and Reel (Pb-free)
M8.15
0 to 70
8 Ld PDIP* (Pb-free)
E8.3
-40 to 85
8 Ld SOIC (Pb-free)
M8.15
ISL8485IBZ (Note)
8485IBZ
ISL8485IB-T
8485IB
8 Ld SOIC Tape and Reel
ISL8485IBZ-T (Note)
8485IBZ
8 Ld SOIC Tape and Reel (Pb-free)
ISL8485IP
ISL8485IP
M8.15
M8.15
-40 to 85
8 Ld PDIP
E8.3
ISL8485IPZ (Note)
ISL8485IPZ
-40 to 85
8 Ld PDIP* (Pb-free)
E8.3
ISL8488IBZ (Note) (No longer
available, recommended
replacement ISL8488EIBZ)
8488IBZ
-40 to 85
8 Ld SOIC (Pb-free)
M8.15
ISL8488IPZ (Note) (No longer
available, recommended
replacement ISL3152EIPZ)
ISL8488IPZ
-40 to 85
8 Ld PDIP* (Pb-free)
E8.3
ISL8489IP
(No longer available, no
recommended replacement )
ISL8489IP
-40 to 85
14 Ld PDIP
E14.3
ISL8490IBZ (Note)
8490IBZ
-40 to 85
8 Ld SOIC (Pb-free)
M8.15
ISL8490IBZ-T (Note)
8490IBZ
ISL8491IBZ (Note)
8491IBZ
ISL8491IBZ-T (Note)
8491IBZ
8 Ld SOIC Tape and Reel (Pb-free)
-40 to 85
14 Ld SOIC (Pb-free)
14 Ld SOIC Tape and Reel (Pb-free)
M8.15
M14.15
M14.15
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Pinouts
ISL8483, ISL8485 (PDIP, SOIC)
TOP VIEW
ISL8488, ISL8490 (PDIP, SOIC)
TOP VIEW
8
VCC
VCC 1
RE 2
7
B/Z
RO 2
DE 3
6
A/Y
DI 3
RO 1
R
D
DI 4
5
GND 4
GND
R
D
ISL8489, ISL8491 (PDIP, SOIC)
TOP VIEW
8
A
NC 1
7
B
RO 2
6
Z
RE 3
5
Y
DE 4
DI 5
14 VCC
13 NC
R
12 A
11 B
D
10 Z
GND 6
9 Y
GND 7
8 NC
Truth Tables
RECEIVING
TRANSMITTING
INPUTS
INPUTS
OUTPUTS
RE
DE
DI
Z
Y
X
1
1
0
1
X
1
0
1
0
0
0
X
High-Z
High-Z
1
0
X
High-Z *
High-Z *
*Shutdown Mode for ISL8483 (see Note 7)
RE
OUTPUT
DE
DE
Half Duplex Full Duplex
A-B
RO
0
0
X
 +0.2V
1
0
0
X
 -0.2V
0
0
0
X
Inputs Open
1
1
0
0
X
High-Z *
1
1
1
X
High-Z
*Shutdown Mode for ISL8483 (see Note 7)
Pin Descriptions
PIN
FUNCTION
RO
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
Ground connection.
A/Y
Noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1.
B/Z
Inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1.
A
Noninverting receiver input.
B
Inverting receiver input.
Y
Noninverting driver output.
Z
Inverting driver output.
VCC
System power supply input (4.5V to 5.5V).
NC
No Connection.
3
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Typical Operating Circuits
ISL8483, ISL8485
+5V
+5V
+
8
0.1F
0.1F
+
8
VCC
1
RO
2
RE
3
DE
4
DI
VCC
R
D
B/Z
7
A/Y
6
RT
RT
DI
4
7
B/Z
DE
3
6
A/Y
RE
2
RO
1
DI
3
RO
2
DI
5
R
D
GND
GND
5
5
ISL8488, ISL8490
+5V
+5V
+
1
0.1F
0.1F
+
1
VCC
2
RO
3
DI
R
D
VCC
A
8
B
7
Z
6
Y
5
RT
RT
5
Y
6
Z
7
B
8
A
GND
D
R
GND
4
4
ISL8489, ISL8491
+5V
+5V
+
14
VCC
A
12
B
11
0.1F
0.1F
RT
+
14
9
Y
10
Z
VCC
2
RO
3
RE
DE
4
4
DE
RE
3
RO
2
5
DI
R
D
Z
10
Y
9
GND
RT
11
B
12
A
D
R
GND
6, 7
6, 7
4
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Input/Output Voltages
A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Short Circuit Duration
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating
HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >7kV
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range
ISL84XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ISL84XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
JA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
170
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
140
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
120
14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
100
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = 25°C, Note 2
PARAMETER
TEMP
(°C)
MIN
TYP
MAX
UNITS
Full
-
-
VCC
V
R = 50 (RS-422), Figure 1
Full
2
3
-
V
R = 27 (RS-485), Figure 1
Full
1.5
2.3
5
V
VOD
R = 27 or 50, Figure 1
Full
-
0.01
0.2
V
VOC
R = 27 or 50, Figure 1
Full
-
-
3
V
VOC
R = 27 or 50, Figure 1
Full
-
0.01
0.2
V
SYMBOL
TEST CONDITIONS
DC CHARACTERISTICS
Driver Differential VOUT (no load)
VOD1
Driver Differential VOUT (with load)
VOD2
Change in Magnitude of Driver
Differential VOUT for
Complementary Output States
Driver Common-Mode VOUT
Change in Magnitude of Driver
Common-Mode VOUT for
Complementary Output States
Logic Input High Voltage
VIH
DE, DI, RE
Full
2
-
-
V
Logic Input Low Voltage
VIL
DE, DI, RE
Full
-
-
0.8
V
Logic Input Current
IIN1
DE, DI, RE (ISL8483)
Full
-2
-
2
A
IIN1
DI (ISL8485 - ISL8491)
Full
-2
-
2
A
IIN1
DE, RE (ISL8485, ISL8489, ISL8491)
Full
-25
-
25
A
IIN2
DE = 0V, VCC = 0V or
4.5 to 5.5V
VIN = 12V
Full
-
-
1
mA
VIN = -7V
Full
-
-
-0.8
mA
-7V  VCM  12V
Full
-0.2
-
0.2
V
Input Current (A, B), Note 10
Receiver Differential Threshold
Voltage
VTH
Receiver Input Hysteresis
VTH
VCM = 0V
25
-
70
-
mV
Receiver Output High Voltage
VOH
IO = -4mA, VID = 200mV
Full
3.5
-
-
V
Receiver Output Low Voltage
VOL
IO = -4mA, VID = 200mV
Full
-
-
0.4
V
Three-State (high impedance)
Receiver Output Current
IOZR
0.4V  VO  2.4V
Full
-
-
1
A
5
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = 25°C, Note 2 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
Receiver Input Resistance
RIN
-7V  VCM  12V
Full
12
-
-
k
No-Load Supply Current, Note 3
ICC
ISL8488, ISL8489, DE, DI, RE = 0V or VCC
Full
-
160
250
A
ISL8490, ISL8491, DE, DI, RE = 0V or VCC
Full
-
500
565
A
ISL8485, DI, RE = 0V or DE = VCC
VCC
DE = 0V
Full
-
700
900
A
Full
-
500
565
A
ISL8483, DI, RE = 0V or DE = VCC
VCC
DE = 0V
Full
-
470
650
A
Full
-
160
250
A
Shutdown Supply Current
ISHDN
ISL8483, DE = 0V, RE = VCC, DI = 0V or VCC
Full
-
1
50
nA
Driver Short-Circuit Current,
VO = High or Low
IOSD1
DE = VCC, -7V  VY or VZ  12V, Note 4
Full
35
-
250
mA
Receiver Short-Circuit Current
IOSR
0V  VO  VCC
Full
7
-
85
mA
Full
18
30
50
ns
SWITCHING CHARACTERISTICS (ISL8485, ISL8490, ISL8491)
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54, CL = 100pF, Figure 2
Driver Output Skew
Driver Differential Rise or Fall Time
tSKEW
RDIFF = 54, CL = 100pF, Figure 2
Full
-
2
10
ns
tR, tF
RDIFF = 54, CL = 100pF, Figure 2
Full
3
11
25
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, Figure 3
Full
-
17
70
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, Figure 3
Full
-
14
70
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, Figure 3
Full
-
19
70
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, Figure 3
Full
-
13
70
ns
Full
30
40
150
ns
Figure 4
25
-
5
-
ns
Receiver Input to Output Delay
tPLH, tPHL Figure 4
Receiver Skew | tPLH - tPHL |
tSKD
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, Figure 5
Full
-
9
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, Figure 5
Full
-
9
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, Figure 5
Full
-
9
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, Figure 5
Full
-
9
50
ns
Note 11
Full
5
-
-
Mbps
Full
250
800
2000
ns
Maximum Data Rate
fMAX
SWITCHING CHARACTERISTICS (ISL8483, ISL8488, ISL8489)
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54, CL = 100pF, Figure 2
Driver Output Skew
Driver Differential Rise or Fall Time
tSKEW
RDIFF = 54, CL = 100pF, Figure 2
Full
-
160
800
ns
tR, tF
RDIFF = 54, CL = 100pF, Figure 2
Full
250
800
2000
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, Figure 3, Note 5
Full
250
-
2000
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, Figure 3, Note 5
Full
250
-
2000
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, Figure 3
Full
300
-
3000
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, Figure 3
Full
300
-
3000
ns
Full
250
350
2000
ns
Figure 4
25
-
25
-
ns
Receiver Input to Output Delay
tPLH, tPHL Figure 4
Receiver Skew | tPLH - tPHL |
tSKD
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, Figure 5, Note 6
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, Figure 5, Note 6
Full
-
10
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, Figure 5
Full
-
10
50
ns
6
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = 25°C, Note 2 (Continued)
TEMP
(°C)
MIN
TYP
MAX
UNITS
CL = 15pF, SW = VCC, Figure 5
Full
-
10
50
ns
fMAX
Note 11
Full
250
-
-
kbps
tSHDN
Note 7
Full
50
200
600
ns
PARAMETER
SYMBOL
Receiver Disable from Output Low
tLZ
Maximum Data Rate
Time to Shutdown (ISL8483 only)
TEST CONDITIONS
Driver Enable from Shutdown to
Output High (ISL8483 only)
tZH(SHDN) CL = 100pF, SW = GND, Figure 3, Notes 7, 8
Full
-
-
2000
ns
Driver Enable from Shutdown to
Output Low (ISL8483 only)
tZL(SHDN)
Full
-
-
2000
ns
Receiver Enable from Shutdown to
Output High (ISL8483 only)
tZH(SHDN) CL = 15pF, SW = GND, Figure 5, Notes 7, 9
Full
-
-
2500
ns
Receiver Enable from Shutdown to
Output Low (ISL8483 only)
tZL(SHDN)
CL = 15pF, SW = VCC, Figure 5, Notes 7, 9
Full
-
-
2500
ns
CL = 100pF, SW = VCC, Figure 3, Notes 7, 8
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL8483, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL8483, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN.
7. The ISL8483 is put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed not
to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low-Power
Shutdown Mode” section.
8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. Devices meeting these limits are denoted as “single unit load (1 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus.
11. Guaranteed by characterization, but not tested.
7
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Test Circuits and Waveforms
R
VCC
DE
Z
DI
VOD
D
Y
VOC
R
FIGURE 1. DRIVER VOD AND VOC
3V
DI
1.5V
1.5V
0V
VCC
CL = 100pF
DE
tPHL
VOH
Z
DI
tPLH
RDIFF
D
Y
50%
OUT (Y)
50%
VOL
CL = 100pF
tPHL
SIGNAL
GENERATOR
tPLH
VOH
OUT (Z)
50%
50%
VOL
90%
DIFF OUT (Y - Z)
10%
tR
+VOD
90%
10%
-VOD
tF
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
8
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Test Circuits and Waveforms (Continued)
DE
Z
DI
500
SIGNAL
GENERATOR
3V
VCC
D
SW
Y
DE
GND
CL
NOTE 7
1.5V
0V
tZH, tZH(SHDN)
NOTE 7
(SHDN) for ISL8483 only
OUTPUT HIGH
OUT (Y, Z)
PARAMETER OUTPUT
RE
DI
SW
CL (pF)
tHZ
Y/Z
X
1/0
GND
15
tLZ
Y/Z
X
0/1
VCC
15
tZH
Y/Z
0 (Note 5)
1/0
GND
100
tZL
Y/Z
0 (Note 5)
0/1
VCC
100
tZH(SHDN)
Y/Z
1 (Note 8)
1/0
GND
100
tZL(SHDN)
Y/Z
1 (Note 8)
0/1
VCC
100
1.5V
tHZ
VOH - 0.5V VOH
2.3V
0V
tZL, tZL(SHDN)
NOTE 7
tLZ
VCC
OUT (Y, Z)
2.3V
OUTPUT LOW
FIGURE 3A. TEST CIRCUIT
VOL + 0.5V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488, ISL8490)
RE
+1.5V
3V
15pF
B
R
A
A
1.5V
RO
1.5V
0V
tPHL
tPLH
VCC
SIGNAL
GENERATOR
50%
RO
50%
0V
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4A. TEST CIRCUIT
FIGURE 4. RECEIVER PROPAGATION DELAY
RE
B
SIGNAL
GENERATOR
NOTE 7
1k
RO
R
VCC
SW
A
GND
RE
3V
1.5V
1.5V
0V
15pF
tZH, tZH(SHDN)
NOTE 7
(SHDN) for ISL8483 only.
RO
PARAMETER
DE
A
SW
tHZ
0
+1.5V
GND
tLZ
0
-1.5V
VCC
tZH (Note 6)
0
+1.5V
GND
tZL (Note 6)
0
-1.5V
VCC
tZH(SHDN) (Note 9)
0
+1.5V
GND
tZL(SHDN) (Note 9)
0
-1.5V
VCC
FIGURE 5A. TEST CIRCUIT
OUTPUT HIGH
tHZ
VOH - 0.5V VOH
1.5V
0V
tZL, tZL(SHDN)
NOTE 7
RO
tLZ
VCC
1.5V
OUTPUT LOW
VOL + 0.5V V
OL
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488, ISL8490)
9
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Application Information
Data Rate, Cables, and Terminations
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a pointto-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices)
receivers on each bus. RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
for multipoint operation, the RS-485 spec requires that
drivers must handle bus contention without sustaining any
damage.
RS-485/422 are intended for network lengths up to 4000’,
but the maximum system data rate decreases as the
transmission length increases. Devices operating at 5Mbps
are limited to lengths less than 100’, while the 250kbps
versions can operate at full data rates with lengths in excess
of 1000’.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as
long as 4000’, so the wide CMR is necessary to handle
ground potential differences, as well as voltages induced in
the cable by external fields.
Receiver Features
These devices utilize a differential input receiver for maximum
noise immunity and common mode rejection. Input sensitivity
is 200mV, as required by the RS422 and RS-485
specifications.
Receiver input impedance surpasses the RS-422 spec of
4k, and meets the RS-485 “Unit Load” requirement of 12k
minimum.
Receiver inputs function with common mode voltages as
great as 7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
All the receivers include a “fail-safe if open” function that
guarantees a high level receiver output if the receiver inputs
are unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver.
ISL8483/85/89/91 receiver outputs are three-statable via the
active low RE input.
Driver Features
The RS-485/422 driver is a differential output device that
delivers at least 1.5Vacross a 54 load (RS-485), and at
least 2V across a 100 load (RS-422). The drivers feature
low propagation delay skew to maximize bit width, and to
minimize EMI.
Drivers of the ISL8483/85/89/91 are three-statable via the
active high DE input.
The ISL8483/88/89 driver outputs are slew rate limited to
minimize EMI, and to minimize reflections in unterminated or
improperly terminated networks. Data rate on these slew
rate limited versions is a maximum of 250kbps. Outputs of
ISL8485/90/91 drivers are not limited, so faster output
transition times allow data rates of at least 5Mbps.
10
Twisted pair is the cable of choice for RS-485/422 networks.
Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common mode
signals, which are effectively rejected by the differential
receivers in these ICs.
Proper termination is imperative, when using the 5Mbps
devices, to minimize reflections. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. Multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
Built-In Driver Overload Protection
As stated previously, the RS-485 spec requires that drivers
survive worst case bus contentions undamaged. The
ISL84XX devices meet this requirement via driver output
short circuit current limits, and on-chip thermal shutdown
circuitry.
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
exceeds the RS-485 spec, even at the common mode
voltage range extremes. Additionally, these devices utilize a
foldback circuit which reduces the short circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
In the event of a major short circuit condition, ISL84XX
devices also include a thermal shutdown feature that
disables the drivers whenever the die temperature becomes
excessive. This eliminates the power dissipation, allowing
the die to cool. The drivers automatically reenable after the
die temperature drops about 15 degrees. If the contention
persists, the thermal shutdown/reenable cycle repeats until
the fault is cleared. Receivers stay operational during
thermal shutdown.
Low Power Shutdown Mode (ISL8483 Only)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL8483
includes a shutdown feature that reduces the already low
quiescent ICC to a 1nA trickle. The ISL8483 enters shutdown
whenever the receiver and driver are simultaneously
disabled (RE = VCC and DE = GND) for a period of at least
600ns. Disabling both the driver and the receiver for less
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
than 50ns guarantees that the ISL8483 will not enter
shutdown.
the end of the Electrical Specification table, for more
information.
Note that receiver and driver enable times increase when
the ISL8483 enables from shutdown. Refer to Notes 5-8, at
Typical Performance Curves
VCC = 5V, TA = 25°C, ISL8483 thru ISL8491; Unless Otherwise Specified
3.6
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
3.4
3.2
RDIFF = 100
3
2.8
2.6
2.4
RDIFF = 54
2.2
2
-40
5
-25
DIFFERENTIAL OUTPUT VOLTAGE (V)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
25
50
85
75
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
160
700
140
ISL8485, DE = VCC, RE = X
650
120
Y OR Z = LOW
100
600
80
550
60
500
40
ICC (A)
OUTPUT CURRENT (mA)
0
TEMPERATURE (°C)
20
0
-20
450
ISL8483, DE = VCC, RE = X
400
350
Y OR Z = HIGH
-40
ISL8485, DE = GND, RE = X,
ISL8490/91,
= RE
ISL8485,
DE =DE
GND,
RE==XX
300
-60
250
-80
-100
200
-120
150
-40
-7 -6
-4
-2
0
2
4
6
OUTPUT VOLTAGE (V)
8
10
12
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLTAGE
11
ISL8483, DE = GND, RE = GND; ISL8488/89, DE = RE = X
-25
0
25
50
75
85
TEMPERATURE (°C)
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Typical Performance Curves
VCC = 5V, TA = 25°C, ISL8483 thru ISL8491; Unless Otherwise Specified (Continued)
400
1200
PROPAGATION DELAY (ns)
1100
tPLHY
1000
tPLHZ
300
|tPHLY - tPLHZ|
900
800
SKEW (ns)
tPHLY
tPHLZ
700
200
|tPLHY - tPHLZ|
100
600
|CROSS PT. OF Y & Z - CROSS PT. OF Y & Z|
500
-40
-25
0
25
50
0
-40
85
75
-25
TEMPERATURE (°C)
FIGURE 10. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8483, ISL8488, ISL8489)
50
25
85
75
FIGURE 11. DRIVER SKEW vs TEMPERATURE
(ISL8483, ISL8488, ISL8489)
40
3
35
2.5
|tPHLY - tPLHZ|
tPHLY
tPHLZ
30
SKEW (ns)
PROPAGATION DELAY (ns)
0
TEMPERATURE (°C)
tPLHZ
tPLHY
25
2
|tPLHY - tPHLZ|
1.5
|CROSSING PT. OF Y & Z - CROSSING PT. OF Y & Z
-25
0
25
50
75
1
-40
85
-25
TEMPERATURE (°C)
0
5
0
RO
4
3
2
RECEIVER OUTPUT (V)
5
DRIVER INPUT (V)
DI
B/Z
A/Y
1
0
TIME (400ns/DIV)
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8483, ISL8488, ISL8489)
12
25
50
75
85
FIGURE 13. DRIVER SKEW vs TEMPERATURE
(ISL8485, ISL8490, ISL8491)
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
FIGURE 12. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8485, ISL8490, ISL8491)
RDIFF = 54, CL = 100pF
0
TEMPERATURE (°C)
RDIFF = 54, CL = 100pF
DI
0
5
RO
0
5
DRIVER INPUT (V)
20
-40
4
3
A/Y
2
B/Z
1
0
TIME (400ns/DIV)
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8483, ISL8488, ISL8489)
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
0
5
RO
0
4
3
2
B/Z
A/Y
1
0
TIME (10ns/DIV)
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8485, ISL8490, ISL8491)
RDIFF = 54, CL = 100pF
DI
5
5
0
RO
0
DRIVER INPUT (V)
DI
5
RECEIVER OUTPUT (V)
RDIFF = 54, CL = 100pF
DRIVER INPUT (V)
VCC = 5V, TA = 25°C, ISL8483 thru ISL8491; Unless Otherwise Specified (Continued)
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
Typical Performance Curves
4
3
A/Y
2
B/Z
1
0
TIME (10ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8485, ISL8490, ISL8491)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
518
PROCESS:
Si Gate CMOS
13
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
February 16, 2016
FN6046.9
CHANGE
Added Rev History and About Intersil verbiage.
Updated “Ordering Information” table on page 2.
Updated following PODs to current revisions listing POD updates:
POD M8.15:
Updated to new POD format by removing table and moving dimensions
onto drawing and adding land pattern
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994
POD M14.15
Added land pattern and moved dimensions from table onto drawing
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
-
7.62 BSC
0.430
-
0.150
2.93
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
15
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
SEATING
PLANE
A2
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
NOTES
-
0.210
-
5.33
4
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8
eA
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
-
5
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
19.68
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
7.62 BSC
6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
N
14
14
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
16
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
17
FN6046.9
February 16, 2016
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
18
FN6046.9
February 16, 2016