High -P erf or manc e Dr BL AD E 6.6 mm x 4.5 mm x 0.6 mm TD A21 321 Dat a She et Revision 2.4, 2015-07-16 Po wer Ma nage m ent and M ulti M ark e t Edition 2015-07-1626 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TDA21321 Revision History Page or Item Subjects (major changes since previous revision) Revision 2.4, 2015-07-16 Package drawings figures 18 – 20 updated Inserted chapter 10 (packaging information) Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 Data Sheet 3 Revision 2.4, 2015-07-16 TDA21321 Applications Applications 1 Desktop and Server Vcore and non-Vcore buck-converter Single Phase and Multiphase POL CPU/GPU Regulation in Notebook, Desktop Graphics Cards, DDR Memory, Graphic Memory High Power Density Voltage Regulator Modules (VRM). Features 2 Input voltage range +4.5 V to +16 V Maximum average current up to 50 A For synchronous Buck step down voltage applications Power MOSFETs rated 25 V for safe operation under all conditions Fast switching technology for improved performance at high switching frequencies (> 750 kHz) Includes bootstrap diode Shoot through protection Max +8 V VGS, high-side and low-side MOSFET gate driving voltage Compatible to standard +3.3 V PWM controller integrated circuits Tri-state PWM input functionality Small package: LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) RoHS compliant Integrated temperature sense Integrated current sense Table 1 Product Identification Part Number Temp Range Package Marking TDA21321 -25C to 125C LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) TDA21321 Figure 1 Data Sheet Picture of the Product 4 Revision 2.4, 2015-07-16 TDA21321 Description 3 Description 3.1 Pinout Figure 2 Pinout, Numbering and Name of Pins (transparent top view) Table 2 I/O Signals Pin No. Name Pin Type Buffer Type Function 2 PWM I/O +3.3 V logic 3 OFF# I +3.3 V logic 4 IMON O Analog 5 IMONREF O Analog 7 TMON/FAULT O Analog/ Digital 8 BOOT I Analog 9 PHASE I Analog 33-38 (pads) SW O Analog Data Sheet PWM drive logic input, Status output for VCIN The tri-state PWM input is compatible with 3.3 V. Deactivates LS-MOSFET Pull low to prevent LS-FET turn-on. Leave open if not used. (If traced out in noisy layout it may require external pull up.) Load current Sensing Provides a voltage proportional to the high/low-side MOSFET currents; Leave open if not used. Load current Sensing Reference to pin 4; Leave open if not used. Thermal Sensing / Fault Pin Temperature reporting, fault signaling by logic “H”; Status output of VDRV, Leave open if not used. Bootstrap voltage pin Connect to BOOT capacitor Switch node input Internally connected to SW pins, Connect to BOOT capacitor as reference pin for boot voltage Switch node output High current output switching node 5 Revision 2.4, 2015-07-16 TDA21321 Description Table 3 Pin No. Power Supply Pin Type Function 13 – 15, 20, VIN 23-28 (pads) POWER 21 VDRV POWER 22 VCIN POWER Input voltage Converter input voltage (connected to drain of the high-side MOSFET and driver) MOSFET gate drive supply voltage High and low-side gate drive Driver logic supply voltage bias voltage for the internal logic Table 4 Name Ground Pins Pin No. Name Pin Type Function 1 CGND GND 16 – 19, PGND 29-32 (pads) GND Control signal ground Should be connected to local PGND externally, preferably by vias to GND plane Power ground All these pins must be connected to the power GND plane through multiple low inductance vias. Table 5 Pin No. Not Connected Name 6, 10, 11, 12 NC Data Sheet Pin Type Function – No internal connection Leave pin floating, tie to VIN or GND. 6 Revision 2.4, 2015-07-16 TDA21321 Description 3.2 General Description The Infineon TDA21321 is a multichip module that incorporates Infineon’s premier MOSFET technology into a single high-side and a single low-side MOSFET. This is coupled with a robust, high performance, high switching frequency gate driver on a single 38 pin LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) package. The optimized gate timing enables significant light load efficiency improvements over discrete solutions. State of the art MOSFET technology provides exceptional performance at full and light load. When combined with Infineon’s Primarion™ Controller Family of Digital Multi-phase Controllers, the TDA21321 forms a complete core-voltage regulator solution for advanced micro and graphics processors as well as pointof-load applications. The device package height is 0.6 mm. It is an excellent choice for applications with critical height limitations and has reduced thermal impedance from junction to top case compared to DrMOS, allowing for top side cooling. 2 The power density for transmitted power of this approach is approximately 50 W within a 28 mm area. Figure 3 Simplified Block Diagram Attention: GH and GL are not accessible on this package, but are mentioned for clarity in this block diagram. Data Sheet 7 Revision 2.4, 2015-07-16 TDA21321 Electrical Specification 4 Electrical Specification 4.1 Absolute Maximum Ratings Note: TA = 25°C Stresses above those listed in Table 6 “Absolute Maximum Ratings” and Figure 4 “Repetitive Voltage Stress at Phase Node - Safe Operating Area” may cause permanent damage to the device. These are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational sections of this specification. Exposure over values of the recommended ratings (Table 8) for extended periods may adversely affect the operation and reliability of the device. Table 6 Absolute Maximum Ratings Parameter Symbol Frequency of the PWM input fSW Maximum average load current Values Unit Note / Test Condition Min. Typ. Max. – 1.2 MHz rated current sense accuracy between 100 kHz and 800 kHz IOUT 0.01 (in CCM) – – 50 A – Input Voltage VIN (DC) -0.30 – 18 V – Logic supply voltage VCIN (DC) -0.30 – 9 V – High and low-side driver voltage VDRV (DC) -0.30 – 9 V – Switch node voltage VSW (DC) -1 – 18 V – PHASE voltage pin (9) BOOT voltage 1 1 VSW (AC) -10 – 25 V – VPHASE (DC) -1 – 18 V – VPHASE (AC) 1 -10 – 25 V – VBOOT (DC) -0.3 – 25 V – 1 – 30 V – VBOOT-PHASE (DC) -0.3 – 9 V – VBOOT (AC) – 1 OFF# voltage VOFF# -0.3 – 4 V PWM voltage VPWM -0.3 – 4 V TMON/FAULT VTMON/FAULT -0.3 – 3.6 V Maximum value valid for operation up to 24h accumulated over lifetime in temperature range of -25˚C ≤ Tj ≤ 125˚C. Else the maximum value is 3.6V. – IMON VIMON -0.3 – 3.6 V – IMONREF VIMONREF -0.3 – 3.6 V – Junction temperature TJmax -40 – 150 C – Storage temperature TSTG -55 – 150 C – Note: All rated voltages are relative to voltages on the CGND and PGND pins unless otherwise specified. 1 AC is limited to 10 ns Data Sheet 8 Revision 2.4, 2015-07-16 TDA21321 Electrical Specification Figure 4 Repetitive Voltage Stress at Phase Node - Safe Operating Area Note: ton refers to the on-time of the HS-MOSFET. For input voltages below 10 V no limits on the duration of ton need to be applied. Information: a) - Area of typical computing applications with 12 V input supply voltage Data Sheet 9 Revision 2.4, 2015-07-16 TDA21321 Electrical Specification 4.2 Table 7 Thermal Characteristics Thermal Characteristics Parameter Symbol Values Min. Typ. θJC – 3.5 – Thermal resistance to top of package θJCtop θJA – – 3.7 Thermal resistance to ambient – – 4.3 Note / Test Condition K/W – Max. Thermal resistance to case (soldering point) 14 Unit – Ploss = 4.5 W, TA = 70 °C, 8 layer server board (2 oz copper) Recommended Operating Conditions and Electrical Characteristics2 Note: VIN =12V, VDRV = VCIN = 5 V, TA = 25 °C unless otherwise specified Table 8 Recommended Operating Conditions Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. Input voltage VIN 4.5 – 16 V – MOSFET driver voltage VDRV 4.5 – 8 V – Logic supply voltage VCIN 4.5 – 8 Frequency of the PWM fSW 100 – 800 Junction temperature TjOP -25 – 2 – kHz +125 °C CCM operation with stated current sense accuracy – Exposure over values of the recommended ratings for extended periods may adversely affect the operation and reliability of the device. Min/Max values are based on empirical Cpk. Data Sheet 10 Revision 2.4, 2015-07-16 TDA21321 Electrical Specification Table 9 Voltage Supply And Biasing Current Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. UVLO VCIN rising VUVLO1_R 3.0 – 4.0 V UVLO VCIN falling VUVLO1_F 2.6 – 3.6 UVLO VDRV rising VUVLO2_R 4.16 4.25 4.34 V UVLO VDRV falling VUVLO2_F 3.7 UVLO BOOT rising VUVLOboot_R 3.88 4.05 4.22 V UVLO BOOT falling VUVLOboot_F 3.5 3.8 3.63 3.76 18 – IVDRV_1MHz – 30 – IC current (control) IC quiescent IVCIN_O – 1.0 – ICIN+IDRV – 1.2 – Pre-Bias at SW VSW_0 – 120 Table 10 GL, GH and TMON/FAULT enable threshold; when UVLO VCIN is enabled then: above threshold GL is enabled, GH depends on UVLO BOOT, TMON/FAULT is released to report driver temperature GL, GH and TMON/FAULT disable threshold; when UVLO VCIN is enabled: below threshold after 3 consecutive cycles or 15 µs (typ.) the driver outputs GL/GH are disabled, TMON/FAULT stops temperature reporting and is held low by pull-down resistor 3.9 – Driver current IVDRV_600kHz Driver enable threshold; above threshold driver is active, driver responds to PWM input when UVLO VDRV and UVLO BOOT are enabled, TMON/FAULT reports driver temperature when UVLO VDRV is enabled Driver disable threshold; below threshold driver is inactive, PWM and TMON/FAULT held low by pull-down resistors mA VBOOT-VSW rising, GH enable threshold; when UVLO VCIN and UVLO VDRV are active: above threshold GH responds to PWM VBOOT-VSW falling, GL/GH disable threshold; when UVLO VCIN and UVLO VDRV are enabled: below threshold counter starts, after 3 consecutive PWM cycles driver outputs are disabled OFF# = 3.3 V, fSW = 600 kHz OFF# = 3.3 V, fSW = 1 MHz mA 160 mV OFF# = 3.3 V, PWM = Open for > 19 µs (typ.) PWM in Tri-state (VPWM_S), VCIN = VDRV = 5V, internal pulldown resistor 1.5 kΩ Current Sense Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. VIMON 0.8 – 2.2 IMONREF IMON gain resistor RIMON range Current sense gain aCS 0.2 – 1.0 - 6.67 - ILeak -2 0 2 IOffset -3 0 3 µA a11 -3 – 3 % a12 -2.5 – 2.5 % a13 -0.5 – 0.5 A Corresponds to 2.25 mV at 5 mV/A (RIMON = 750Ω), device in regulation for 45 A < Iout < IOCPtrip tested at 25 A, for 25 A ≤ Iout ≤ 45 A other guaranteed by design for -25 < Iout < 25 A a14 -20 – 20 % for -50 A ≤ Iout ≤ -25 A IMON Voltage Range Leakage current Current Zero current offset Monitoring Accuracy at 25 °C … 125 °C VDRV = 5 V ± 10 % VCIN = 5 V ± 10 % Data Sheet 11 V IMONREF is a current mirror output serving kΩ as unfiltered reference node. At IMON a filtered voltage signal proportional to the current is provided. It tracks the average µA/A value of IMONREF. µA ID = 0, VCM = 1.5, PWM in tri-state Revision 2.4, 2015-07-16 TDA21321 Electrical Specification Table 11 Temperature Sense Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Temp. Sense and Accuracy Temp. FAULT TTMAX 140 145 Output high VTMON_H 2.6 – Output monitor VTMON 0.4 – – 3 -25 – 3 Fault delay Temp. range tTMONdeg 4 TTMON Temp. coefficient Nominal 5 TC – 8 V25C – 800 -4 – Accuracy at -25 °C aTMON … 125 °C (tested at 25 °C, other guaranteed by design) Table 12 150 °C Temperature monitors driver junction. – V Circuit reports temperatures to -25 °C accurately (0.4V). The maximum 1.8 temperature reported is TTMAX. Above TTMAX – µs a logic ‘H’ is asserted to indicate a fault 150 °C (latched). At OTP fault PWM input is suspended and driver is being set to – mV/K tri-state mode until VCIN and/or VDRV – mV have been re-cycled. 4 K -25 °C … 125 °C, unspecified below -25 °C Other Logic Functions, Inputs/Outputs And Thresholds Parameter Symbol Values Unit Note / Test Condition OFF# Input low VOFF#_L – – Input high VOFF#_H 2.0 – Input low VPWM_L – – Input high VPWM_H 2.4 – – Input resistance RIN-PWM 6 – 10 k VPWM = 1 V Open voltage VPWM_O – 1.6 – V VPWM_O 1.2 – 2.0 5 – 10 ns Minimum pulse width to detect PWM pulse PWM pulses shorter than tPWMmin will be extended to tPWMmin Duty cycle limitation at IOCPtrip, fault asserted and latched after 10 truncated consecutive switching cycles Min. Typ. Max. PWM Tri-state shutdown VPWM_S 6 window 7 Min pulse width tPWMdetect 8 0.8 V – VOFF# falling VOFF# rising 0.8 V VPWM falling VPWM rising – Min pulse time tPWMmin – 30 – ns OCP Overcurrent Protection IOCPtrip 58 65 72 A HSS High-Side-Short Protection VHSStrip – 0.83 – V Voltage tested at phase node during LSMOSFET on-time. If voltage exceeds VHSStrip, fault is asserted and latched. 3 Guaranteed by design Guaranteed by design 5 Guaranteed by design 4 6 Maximum voltage range for tri-state 7 Guaranteed by design Guaranteed by design 8 Data Sheet 12 Revision 2.4, 2015-07-16 TDA21321 Electrical Specification Table 13 Timing Characteristics 9 Parameter Symbol Values Min. Typ. Unit Note / Test Condition VOUT prebiased at 1 V, other conditions as for t_pts ILOAD = 0, VDRV = VCIN = 5 V, VIN = 12 V, fsw = 600 kHz Max. PWM tri-state to SW falling delay t_pts2 – 16 – ns PWM tri-state to SW rising delay t_pts – 19 – ns PHASE Shutdown Hold-Off time from PWM low PHASE Shutdown Hold-Off time from PWM high t_tsshd – 41 – t_tssh – 45 – PWM to SW Turn-off propagation delay t_pdlu – 31 – PWM to SW Turn-on propagation delay t_pdll – 21 – OFF# Turn-off propagation delay falling t_pdl_OFF# – 17 – OFF# Turn-on propagation delay rising t_pdh_OFF# – 25 – ns Corresponding diagrams can be found under section “Gate Driver Timing Diagram”. 9 All timing data are guaranteed by design Data Sheet 13 Revision 2.4, 2015-07-16 TDA21321 Theory of Operation 5 Theory of Operation The TDA21321 features a power stage with MOSFET driver. Temperature and current are being monitored. Data and various fault conditions can be reported to the controller. The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to +18 V. 5.1 Driver Characteristics The gate driver has 2 voltage inputs, VCIN and VDRV. VCIN is the 5 V logic supply for the driver. VDRV sets the driving voltage for the high-side and low-side MOSFETs. The reference for the gate driver control circuit (VCIN) is CGND. To decouple the sensitive control circuitry (logic supply) from a noisy environment a ceramic capacitor must be placed between VCIN and CGND close to the pins. VDRV needs also to be decoupled using a ceramic capacitor (MLCC) between VDRV and PGND in close proximity to the pins. PGND serves as reference for the power circuitry including the driver output stage. 5.2 Power-Up Sequence Without the logic supply VCIN the device remains off. PWM is held low by an internal pull down resistor. PWM information cannot be fed to the driver. VCIN supplies power to the driver logic. With the presence of VCIN on power-up of the gate drive voltage VDRV, the driver and the PWM input will be enabled, the unforced PWM level will be within its tri-state window. This signals that the driver supply voltages have cleared their respective UVLO thresholds. TMON/FAULT reports temperature. The PWM controller is expected to wait for this to happen before initiating PWM signals to start up the system. Note that with VCIN and VDRV present, the switching node can rise up to VSW_0 with PWM in tri-state condition. 5.3 Inputs to the Internal Control Circuits PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V logic. The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is held internally at a tri-state level of VPWM_O. The PWM signal must prevail for at least tPWMmin to initiate a response from the driver. The PWM threshold voltages VPMW_O, VPWM_H, VPWM_L do not vary over the wide range of VCIN supply voltages (4.5 V to 8 V). The OFF# pin provides a means to keep the low-side MOSFET disabled regardless of the PWM signal. It is an active low signal. An internal pull up resistor ensures regular operation when the pin is not used. When pulled low, the low-side MOSFET is kept in off-state. In multiphase systems the OFF# pins of all phases may be connected together. One controller output is then able to toggle the LS-FET operation mode. Data Sheet 14 Revision 2.4, 2015-07-16 TDA21321 Theory of Operation Table 14 PWM and OFF# Pin Functionality, Driver Outputs PWM logic level High Open (Tri-state: left floating, or high impedance) Any Low Low 5.4 OFF# logic level Gate HS-FET (GH) Gate LS-FET (GL) High Low Low High or open High Monitoring and Protection Circuits The TDA21321 is designed with the various protection functions. Most of these protection features require a PWM controller that reacts properly on the assertion of a fault signal at TMON/FAULT to shutdown the circuit. Fault assertion is latched and is being removed when VCIN and/or VDRV will be re-cycled. A reported fault is always indicating a critical condition with high stress levels on the device and/or load that requires immediate action in form of shutdown to prevent imminent catastrophic failure. In multiphase regulators the TMON/FAULT outputs of the power stages will have to be connected together. The TMON/FAULT output voltage follows the highest voltage output of any phase connected. The pull-down capability of any TMON/FAULT output is weak so that a fault assertion of any phase will always override other phase outputs. 5.4.1 High-Side Short Protection (HSS) The voltage at the switching node is being monitored during the LS-MOSFET being driven in on-state. When during that time the switching node voltage exceeds a critical threshold of VHSStrip the HSS fault is being asserted by pulling TMON/FAULT to ‘high’. The PWM controller has to shut down the power stage to prevent catastrophic failure. TMON/FAULT is latched and will be released when VCIN and/or VDRV will be re-cycled. HSS can lead to a very sudden current rise that can impact voltage potentials in and in vicinity of the power device so that early reset events could potentially occur. Therefore, it is important to always have the system controller terminate the power supply as soon as a critical event has been reported by the power stage. 5.4.2 Thermal Protection and Temperature Monitoring The driver monitors and reports its temperature. In multiphase systems with connected TMON/FAULT pins only the highest temperature of any of the connected phases will be reported. The PWM controller is supposed to react on the reported temperature with power throttling commands to the load. If the system fails to respond and the temperature continues to rise to a value of T TMAX for at least tTMONdeg, TMON/FAULT is being pulled high to report an Over-Temperature Fault (OTP). TMON/FAULT is latched and will be released when VCIN and/or VDRV will be re-cycled. At OTP fault the driver outputs will be deactivated until VCIN and/or VDRV have been re-cycled. The PWM controller is ecxpected to shut down the power stage to prevent catastrophic failure. Data Sheet 15 Revision 2.4, 2015-07-16 TDA21321 Theory of Operation Figure 5 Thermal monitoring and protection Note: Temperature reporting below TTMON_min occurs with limited accuracy. TTMON_min is being defined by the corresponding controller detection threshold for logic ‘L’. The reported voltage as function of temperature follows this equation: VTMON 0.6V 8 mV 5.4.3 K T C (1) Undervoltage Lockout (UVLO) The power stage should not be operated when its supply voltages are out of the nominal range. UVLO conditions occurring during power up and power down must be accommodated by proper sequencing. An UVLO condition under normal operation can indicate a problem with the driver voltage and must be handled with a shutdown to prevent damage to the power stage. A primary UVLO circuit monitors VCIN. Only after having VCIN in regulation range the UVLO monitoring on VDRV takes place. During startup UVLO on VDRV is being signaled by keeping TMON/FAULT low. With VCIN being below VUVLO1_R at startup the driver is inactive, PWM and TMON/FAULT are held low. When VCIN exceeds VUVLO1_R the driver becomes active, pin PWM is being enabled as input and held internally at its tri-state level of VPWM_O. Then VDRV determines TMON/FAULT: - Below VUVLO2_R TMON/FAULT remains ‘low’. - When VDRV exceeds VUVLO2_R TMON/FAULT is released and reports temperature. - When VDRV falls below VUVLO2_F for 3 consecutive cycles or 15 µs (typ.) TMON/FAULT is being pulled ‘low’. If at startup VCIN and/or VDRV are below their respective undervoltage lockout rising thresholds (VUVLO1_R, VUVLO2_R) GL and GH remain disabled. Once these thresholds have been cleared, the driver provides GL output Data Sheet 16 Revision 2.4, 2015-07-16 TDA21321 Theory of Operation signal following PWM. When the voltage VBOOT-VSW has been exceeding VUVLOboot_R, GH is being released to respond to PWM. When VCIN and/or VDRV are falling below their respective undervoltage lockout falling thresholds ( VUVLO1_F, VUVLO2_F) the driver disables its outputs GH and GL to drive the MOSFETs. When the voltage VBOOT-VSW has been falling below VUVLOboot_F for 3 consecutive PWM cycles the driver will be disabled. Figure 6 5.4.4 Output Signal at TMON/Fault BOOT - Undervoltage Protection (UVLOBOOT) The voltage between BOOT and SW pins (boot-voltage) is being monitored when VCIN and VDRV have been clearing their respective UVLO conditions. At startup, the LS-MOSFET gate (GL) is enabled to respond to the PWM signal when VDRV is being active. If the voltage at the boot capacitor is insufficient to clear the VUVLOboot_R threshold, GH remains disabled until the active LS-MOSFET has forced sufficient charge onto the boot capacitor during the PWM “L” state. When the boot capacitor voltage exceeds VUVLOboot_R, the GH output for the gate drive of the HS-MOSFET is enabled. At startup and anytime when the boot voltage is below VUVLOboot_F an internal boot-error flag is set. The booterror flag is being reset when the boot voltage exceeded VUVLOboot_R. If during the falling edge of the PWM (from ‘H’ to tri-state or from ‘H’ to ‘L’) the UVLOBOOT error flag is set, an internal counter increases by one. When the counter reaches three, the driver outputs GH/GL are being disabled (i.e. latched in tri-state), regardless of the PWM input. To reset the driver and resume operation, the PWM input has to be held in tri-state for 19 µs (typ). After that, the UVLOBOOT counter is being reset to zero and the driver performs a startup sequence as described before in order to bring sufficient charge onto the boot capacitor. Data Sheet 17 Revision 2.4, 2015-07-16 TDA21321 Theory of Operation The UVLOBOOT counter is also being reset to zero whenever during the falling edge of the PWM the UVLO BOOT error flag was not set, i.e. the error condition had been temporary for less than three consecutive instances of the falling edge of the PWM signal. To prevent depletion of the boot capacitor during extended time in tri-state during regular operation, a boot refresh circuit will engage after 19 µs (typ) in consecutive tristate condition when the voltage at the boot capacitor has fallen below VUVLOboot_F. This circuit remains active until VUVLOboot_R has been reached or the PWM input signal leaves the region of tri-state. The boot refresh circuit is powered by VIN. To ensure full effectiveness the voltage difference (VIN-VSW ) should be more than 4.8 V. If the driver was disabled due to an UVLOBOOT error, it will be reset to resume operation when VCIN and/or VDRV will be re-cycled or PWM will be held at tri-state level for more than 19 μs (typ). In case of an UVLOBOOT error it is expected that the system controller discovers a missing phase, phase current mismatch, excessive temperature or OCP events on other phases and initiates shutdown. 5.4.5 Current Monitoring and Overcurrent Protection (OCP) The TDA21321 senses and reports current back to the controller via the voltage at IMON. This voltage is a filtered representation of the voltage at IMONREF. IMONREF is a current source output: I IMONREF I OUT aCS (2) The voltage at IMONREF depends on the impedance its current is being passed through. A recommended target voltage at zero output current is 1.5V (common mode voltage). The series resistor RIMONREF between IMONREF and the common mode voltage reference sets the voltage gain of the current sense according to: VIMONREF VIMONREF _ CM RIMONREF I MONREF (3) The output current is now represented by the voltage difference between IMON and V IMONREF_CM. VIMONREF_CM is the voltage at IMONREF when the load current is zero. VIMON VIMONREF _ CM I OUT RIMONREF aCS (4) acs is given in Table 10 for VDRV = 5V. If VDRV has been chosen to be different, acs has to be calculated as: aCS 6.67 A A 1 VDRV V 5 0.012 (5) A filter capacitor CIMON of 10 pF has to be placed between IMON and VIMONREF_CM (reference voltage pin of RIMONREF). CIMON and RIMONREF have to be arranged in a tight loop close to the pins of the TDA21321. An additional resistor RIMON has to be connected in parallel to CIMON. Its location is flexible and can also be at the controller. The value for RIMON should be chosen identical to RIMONREF within the range of 200 Ω to 1 kΩ. At the voltage receiver side the measurement loop has to be closed. It is important to not inject noise into this loop. Therefore differential routing of IMON and IMONREF is required. Data Sheet 18 Revision 2.4, 2015-07-16 TDA21321 Theory of Operation For example, having a permissible 500 mV voltage range at the receiver side to report positive current of 100 A, the resistor that has to be used in the IMONREF path can be calculated as: VIMON VIMONREF _ CM 500mV RIMONREF VIMON VIMONREF _ CM I OUT aCS (6) 500mV 750 100 A 6.67 10 6 Having a resistor value of 348 Ω will result in the following voltage difference: VIMON VIMONREF _ CM RIMONREF I OUT aCS 348 100 A 6.67 106 232mV (7) The sensing of current occurs in the HS-MOSFET and the LS-MOSFET during their respective on-times. During tri-state condition both MOSFETs are in off-state without sensing. The current reported is then zero. If the tristate condition was present for more than 19 µs (typ.), current reporting resumes with a delay of 1 µs (typ.). OCP: By design of the application the current should never exceed the OCP tripping threshold I OCPtrip. The duty cycle is being truncated by the TDA21321 when the current exceeds IOCPtrip. This prevents the part from being destroyed by excessive current. A counter is being increased counting consecutive PWM duty cycle truncations. The counter is being reset at the first non-truncated PWM duty cycle. When the counter reaches the value of 10, a fault will be reported at TMON/FAULT by pulling it to ‘high’ level signaling the PWM controller the need for immediate action to prevent catastrophic failure. This fault is latched and will be released when VCIN and/or VDRV are being re-cycled. 5.4.6 Shoot Through Protection The TDA21321 driver includes gate drive functionality to protect against shoot through. In order to protect the power stage from overlap, both high-side and low-side MOSFETs being on at the same time, the adaptive control circuitry monitors specific voltages. When the PWM signal transitions to low, the high-side MOSFET will begin to turn-off after the propagation delay time t_pdlu. When VGS of the high-side MOSFET is discharged below 1 V (a threshold below which the high-side MOSFET is off), a secondary delay t_pdhl is initiated. After that delay the low-side MOSFET turns on regardless of the state of the “PHASE” pin. It ensures that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See Figure 9 for more detail. Data Sheet 19 Revision 2.4, 2015-07-16 TDA21321 Application 6 Application 6.1 Implementation Figure 7 Pin Interconnection Outline (transparent top view) Note: 1. Pin 9 (PHASE) is internally connected to the SW pads 33-38. 2. The capacitor CTMON is used to filter noise from the TMON/FAULT connection. The capacitor has to be placed at the input of the controller. Its value should be set between 0.1 nF and 0.5 nF. 3. RIMON should be chosen identical to RIMONREF. 4. CIMON and RIMONREF have to be arranged in a tight loop close to the pins of the TDA21321. 5. To lower the pre-bias voltage at Vout to below VSW_0, place a resistor from Vout to GND. 6. CIN should consist of a 0.1 µF and a 1 µF very close to the pins 15/16 and a 1 µF capacitor at pins 19/20. In addition place sufficient MLCCs in relative proximity of each power stage to deliver energy for the on-time of the HS-MOSFET. 7. The value of capacitor CBOOT should be chosen according to the corresponding application note. Data Sheet 20 Revision 2.4, 2015-07-16 TDA21321 Application 6.2 Figure 8 Data Sheet Typical Application Six-phase voltage regulator - typical application (simplified schematic) 21 Revision 2.4, 2015-07-16 TDA21321 Gate Driver Timing Diagram Gate Driver Timing Diagram 7 VPWM_H VPWM_H VPWM_H Tri-State PWM VPWM_L t_pdlu t_pdll VPWM_L t_tsshd t_pts t_tssh d t_pts2 90% VSW SW 10% VSW Note: SW during entering/exiting tri-state behaves dependend on inductor current. Figure 9 Adaptive Gate Driver Timing Diagram VOFF#_H OFF# VOFF#_L t_pdh(OFF#) t_pdl(OFF#) LS-FET ‘ON’ LS-FET ‘ON’ SW -VF LS-FET ‘OFF’ (body diode conducting) Note: PWM is low. Figure 10 Data Sheet OFF# Timing Diagram 22 Revision 2.4, 2015-07-16 TDA21321 Performance Curves – Typical Data 8 Performance Curves – Typical Data Operating conditions (unless otherwise specified): VIN = +12 V, VCIN = VDRV = +5 V, VOUT = +1.8 V, fSW = 750 kHz, 180nH (Delta, HCB118080D-181, DCR = 0.19 mΩ) inductor, TA = 25 °C, airflow = 200 LFM, no heatsink. Efficiency and power loss reported herein include only TDA21321 losses. 8.1 Figure 11 Data Sheet Driver Current versus Switching Frequency Driver Current over Switching Frequency in CCM Operation 23 Revision 2.4, 2015-07-16 TDA21321 Performance Curves – Typical Data 8.2 Efficiency and Power Loss versus Output Voltage Figure 12 Efficiency at VIN = 12 V, VCIN = VDRV = 5 V, fSW = 750 kHz, Parameter: VOUT Figure 13 Power Loss at VIN = 12 V, VCIN = VDRV = 5 V, fSW = 750 kHz, Parameter: VOUT Data Sheet 24 Revision 2.4, 2015-07-16 TDA21321 Performance Curves – Typical Data 8.3 Efficiency and Power Loss versus Input Voltage Figure 14 Efficiency at fSW = 750 kHz, VCIN = VDRV = 5 V, VOUT = 1.8 V, Parameter: VIN Figure 15 Power Loss at fSW = 750 kHz, VCIN = VDRV = 5 V, VOUT = 1.8 V, Parameter: VIN Data Sheet 25 Revision 2.4, 2015-07-16 TDA21321 Performance Curves – Typical Data 8.4 Efficiency and Power Loss versus Switching Frequency Figure 16 Efficiency at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.8 V, Parameter: fSW Figure 17 Power Loss at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.8 V, Parameter: fSW Data Sheet 26 Revision 2.4, 2015-07-16 TDA21321 Mechanical Drawing LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) 9 Figure 18 Data Sheet Mechanical Drawing LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) Mechanical Dimensions of Package (Top and Side View) in mm 27 Revision 2.4, 2015-07-16 TDA21321 Mechanical Drawing LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) Figure 19 Data Sheet Mechanical Dimensions of Package (Bottom View) in mm 28 Revision 2.4, 2015-07-16 TDA21321 Mechanical Drawing LG-WIQFN-38-1 (6.6x4.5x0.6 mm³) Figure 20 Data Sheet Landing Pattern and Stencil Dimensions (SW on upper end) in mm 29 Revision 2.4, 2015-07-16 TDA21321 Packaging Information 10 Figure 21 Data Sheet Packaging Information Packaging Information in mm 30 Revision 2.4, 2015-07-16 TDA21321 Board Layout Recommendations Board Layout Recommendations 11 The PCB (printed circuit board) layout design follows the listed industry standards: 10 - Recommended vias: 10 mil hole with 20 mil via pad diameter, 12 mil hole with 24 mil via pad diameter - Minimum (typical) via to via center distance: 25 mil (30 … 35 mil) - Minimum feature width: 5 mil - Minimum (typical) clearance: 5 mil (15 … 20 mil) Commonly, 10 mil via drill diameters are used for PCBs up to 150 mil thicknesses (usually 22 layers). For thicker boards, 12 mil vias are recommended. To reduce voltage spikes caused by parasitic circuit inductance, all primary decoupling capacitors for VIN, VDRV, BOOT and VCIN should be of MLCC type, X6S or X7R rated and located at the same board side as the powerstage close to their respective pins. This is especially important for the VIN to PGND MLCCs. Electrical and thermal connection of the powerstage to the PCB is crucial for achieving high efficiency. Therefore, vias in VIN and PGND pads are required in the pad areas to connect most effectively to other power and PGND layers. Bigger value MLCC input capacitors should be placed at the bottom side of the PCB close to the vias of the powerstage’s VIN and PGND pads. To reduce the stray inductance in the current commutation loop it is strongly recommended to have the 2 nd layers from the top and the bottom of the board to be monolithic ground planes. All logic and signal connections between powerstage and controller should be embedded between two ground layers. The routing of the current sense lines back to the controller has to be done differentially, for example with 5 mil spacing and 10 – 15 mil distances to other potentials. If the PCB features more than 10 layers, the passive components associated with the current sense lines should be located only at the top side of the board. All resistors and capacitors near the powerstage should be in 0402 case size. For minimizing distribution loss to the load and maintaining signal integrity, have multiple layers/planes in parallel and ensure that the copper cross section for PGND is at least as big as it is for Vout. Figure 22 10 Generic Board Design Unit conversion: 1 mil = 25.4 μm Data Sheet 31 Revision 2.4, 2015-07-16 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG