High -P erf or manc e Dr M O S 6 mm x 6 mm x 0.8 mm IQFN TD A21 220 Dat a She et Revision 1.9, 2011-03-31 Preliminary Indust r y a nd Mul ti Ma rk et Edition 2011-03-31 Published by Infineon Technologies AG 81726 Munich, Germany © 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TDA21220 Revision History Page or Item Subjects (major changes since previous revision) Revision 1.9, 2011-03-31 All Table 6 Update format of document. Figure 1 Update the package picture Table 14 Correct a typo on logic function of SMOD pin Figure 9 Clarify the definition of T_GHtsshd and T_GLtsshd Table 11 Update the Toff_min_PWM to min 65ns Define the AC values. Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. 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Last Trademarks Update 2010-10-26 Preliminary Data Sheet 3 Revision 1.9, 2011-03-31 TDA21220 Applications 1 Applications Desktop and Server VR11.X and VR12 Vcore and non-Vcore buck-converter Network and Telecom processor VR Single Phase and Multiphase POL CPU/GPU Regulation in Notebook, Desktop Graphics Cards, DDR Memory, Graphic Memory High Power Density Voltage Regulator Modules (VRM). 2 Features ® Compliant to Intel VR12 Driver and Mosfets Module (DrMOS) for Desktop/Server Applications For synchronous Buck step down voltage applications Maximum average current of 50 A Input voltage range +4.5 V to +16 V Power MOSFETs rated 25 V for safe operation under all conditions Extremely fast switching technology for improved performance at high switching frequencies (> 1 MHz) Remote driver disable function Switch modulation (SMOD#) of low side MOSFET Includes bootstrap diode Shoot through protection +5 V High and Low Side driving voltage Compatible to standard +3.3 V PWM controller integrated circuits Three-state PWM input functionality Small package: IQFN40 (6 x 6 x 0.8 mm³) RoHS compliant Table 1 Product Identification Part Number Temp Range Package Marking TDA21220 -25 to 125C 6 x 6 x 0.8 mm³ PG-IQFN-40-1 TDA21220 Figure 1 Picture of the Product Preliminary Data Sheet 4 Revision 1.9, 2011-03-31 TDA21220 5 SMOD# 6 VCIN 7 BOOT 8 VDRV 9 GH 10 CGND Pinout NC 3.1 PHASE Description VIN 3 VIN Description 4 3 2 1 VIN 11 40 PWM 39 DISB# 38 NC VIN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH VIN 12 VIN VIN 13 Figure 2 CGND PGND 27 28 29 30 VSWH PGND 26 VSWH PGND 25 PGND 24 PGND 23 PGND 22 PGND 21 PGND VSWH Pinout, Numbering and Name of Pins (transparent top view) Note: Signals marked with “#” at the end are active low signals. Table 2 I/O Signals Pin No. Name Pin Type Buffer Type Function 1 SMOD# I +3.3 V logic 6 GH O Analog 7 PHASE O Analog 4 BOOT I Analog 15, 29 to 35, VSWH pad VSWH O Analog 36 GL O Analog 39 DISB# I +3.3 V logic 40 PWM I +3.3 V logic Preliminary Data Sheet High and Low Side gate disable When SMOD# is “low” the GL is “off” High side gate signal Monitoring of High Side MOSFET gate Switch node output Internally connected to VSWH pin, Connect to BOOT capacitor Bootstrap voltage pin Connect to BOOT capacitor Switch node output High current output switching node Low side gate signal Monitoring of Low Side MOSFET gate Disable signal (active low) Pull to GND to disable the IC. PWM drive logic input The three state PWM input is compatible with 3.3 V. 5 Revision 1.9, 2011-03-31 TDA21220 Description Table 3 Power Supply Pin No. Name Pin Type Buffer Type Function 2 VCIN POWER – 3 VDRV POWER – 9 to 14, Vin pad VIN POWER – Table 4 Logic supply voltage 5 V bias voltage for the internal logic FET gate supply voltage High and Low Side gate drive 5 V supply Input voltage Supply of the drain of the High Side MOSFET Ground Pins Pin No. Name Pin Type Buffer Type Function 5, 37, CGND pad CGND GND – 16 to 28 PGND GND – Table 5 Control signal ground Should be connected to PGND externally Power ground All these pins must be connected to the power GND plane through multiple low inductance vias. Not Connected Pin No. Name Pin Type Buffer Type Function 8, 38 NC – Preliminary Data Sheet – No internal connection Leave pin floating or tie to GND. 6 Revision 1.9, 2011-03-31 TDA21220 Description 3.2 General Description The Infineon TDA21220 is a multichip module that incorporates Infineon’s premier MOSFET technology for a single high side and a single low side MOSFET coupled with a robust, high performance, high switching frequency gate driver in a single 40 pin QFN package. The optimized gate timing allows for significant light load efficiency improvements over discrete solutions. State of the art MOSFET technology provides exceptional full load performance. Thus this device has a clear advantage over existing approaches in the marketplace when both full load and light load efficiencies are important. When combined with the Infineon’s Primarion™ Controller Family of Digital Multi-phase Controllers, the TDA21220 forms a complete core-voltage regulator solution for advanced micro and graphics processors as well as point-of-load applications. The TDA21220 is pin to pin compatible and compliant with the Intel 6x6 DrMOS specification. The device package height is only 0.8 mm, and is an excellent choice for applications with critical height limitations. VCIN PHASE GH BOOT VDRV HS MOS HS Driver VIN Level Level Shifter Shifter UVLO UVLO 500k DISB# 500k HS HS Logic Logic CGND VCIN Shoot Through Protection 16k5 Input Input Logic Logic 3- State 3-State PWM 7k1 VSWH VDRV LS MOS CGND VCIN 400k LS LS Logic Logic SMOD# LS Driver 600K CGND PGND IC DRIVER CGND Figure 3 500k GL VDRV Simplified Block Diagram Preliminary Data Sheet 7 Revision 1.9, 2011-03-31 TDA21220 Electrical Specification 4 Electrical Specification 4.1 Absolute Maximum Ratings Note: TA = 25°C Stresses above those listed in Table 6 “Absolute Maximum Ratings” may cause permanent damage to the device. These are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational sections of this specification. Exposure to the absolute maximum ratings for extended periods may adversely affect the operation and reliability of the device. Table 6 Absolute Maximum Ratings Parameter Symbol Unit Note / Test Condition Min. Typ. Max. Frequency of the PWM input fSW – – 1.2 MHz – Maximum average load current IOUT – – 50 A – Input Voltage VIN (DC) -0.30 – 25 V – Logic supply voltage VCIN (DC) -0.30 – 6.5 V – High and Low side driver voltage VDRV (DC) -0.30 – 6.5 V – Switch node voltage VSWH (DC) -1 – 25 V – – 25 V – PHASE node voltage BOOT voltage Values 1 VSWH (AC) -10 VPHASE (DC) -1 – 25 V – VPHASE (AC) -10 – 25 V – VBOOT (DC) -0.3 – 31.5 V – 1 VBOOT (AC) -1 – 31.5 V – VBOOT-PHASE (DC) -1 – 6.5 V – SMOD# voltage VSMOD# (DC) -0.3 – 5.5 V – DISB# voltage -0.3 – 5.5 V – PWM voltage VDISB2 VPWM2 -0.3 – 5.5 V – Junction temperature TJmax -40 – 150 C – Storage temperature TSTG -55 – 150 C – Note: All rated voltages are relative to voltages on the CGND and PGND pins unless otherwise specified. 1 AC is limited to 10 ns 2 Latch Up class II- Level B (Jedec 78). Please refer to Quality Report for details. Preliminary Data Sheet 8 Revision 1.9, 2011-03-31 TDA21220 Electrical Specification 4.2 Table 7 Thermal Characteristics Thermal Characteristics Parameter Symbol Min. Typ. Max. Thermal resistance, junction-soldering point1 Thermal resistance, junction-top of package θJS – 5 – θJtop – 20 – 4.3 Values Unit Note / Test Condition K/W – – Recommended Operating Conditions and Electrical Characteristics Note: VDRV = VCIN = 5 V, TAt = 25°C Table 8 Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Input voltage VIN 5 – 16 MOSFET driver voltage VDRV 4.5 5 6 – Logic supply voltage VCIN 4.5 5 6 – Junction temperature TjOP -25 – +125 Table 9 Values Unit Note / Test Condition V – °C – Unit Note / Test Condition Voltage Supply And Biasing Current Parameter Symbol Values Min. Typ. Max. IVDRV_300kHz – 10 – mA DISB# = 5 V, fSW = 300 kHz IVDRV_PWML – 25 – μA DISB# = 5 V, PWM = 0 V IVCIN_PWML – 400 – DISB# = 5 V, PWM = 0 V SMOD# = Open IVCIN_O – 500 – DISB# = 5 V, PWM = Open SMOD# = Open IC quiescent ICIN+IDRV – – 550 DISB# = 0 V UVLO rising VUVLO_R 2.9 3.5 3.9 UVLO falling VUVLO_F 2.5 3.1 3.3 Driver current IC current (control) 1 V VCIN rising VCIN falling The junction-soldering point is referred to the VSWH bottom exposed pad. Preliminary Data Sheet 9 Revision 1.9, 2011-03-31 TDA21220 Electrical Specification Table 10 Logic Inputs And Threshold Parameter DISB# SMOD# PWM Symbol Values Min. Typ. Max. Note / Test Condition V VDISB falling Input low VDISB_L 0.7 1.1 1.3 Input high VDISB_H 1.9 2.1 2.4 Sink current IDISB – 2 – μA VDISB = 1 V Input low VSMOD#_L 0.7 1.1 1.3 V VSMOD# falling Input high VSMOD#_H 1.9 2.1 2.4 Open voltage VSMOD#_O – 3.0 – Sink current ISMOD# – -8 – μA VSMOD# = 1 V Input low VPWM_L – – 0.7 V VPWM falling Input high VPWM_H 2.4 – – Input resistance RIN-PWM 3 5 7 k VPWM = 1 V Open voltage VPWM_O – 1.5 – V VPWM_O Tristate shutdown 1 window VPWM_S 1.2 – 1.9 Table 11 VDISB rising VSMOD# rising – VPWM rising – Timing Characteristics Parameter Symbol Values Min. Typ. Max. Three State to GL/GH rising delay GL Shutdown Hold-Off time T_pts – 15 – T_GLtsshd – 150 – GH Shutdown Hold-Off time T_GHtsshd – 85 – GH Turn-on propagation delay T_pdhu – 15 – GH Turn-off propagation delay T_pdlu – 20 – GL Turn-on propagation delay T_pdhl – 20 – GL Turn-off propagation delay T_pdll – 10 – DISB# Turn-off propagation delay falling DISB# Turn-on propagation delay rising T_pdl_DISB – 20 – T_pdh_DISB – 20 – PWM minimum pulse width high side Ton_min_PWM – 25 – PWM minimum off time Toff_min_PWM 65 – – 1 Unit Unit Note / Test Condition ns GH, GL unloaded Maximum voltage range for tri-state Preliminary Data Sheet 10 Revision 1.9, 2011-03-31 TDA21220 Theory of Operation 5 Theory of Operation The TDA21220 incorporates a high performance gate driver, one high-side power MOSFET and one low-side power MOSFET in a single 40 lead QFN package. The advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.This module is ideal for use in Synchronous Buck Regulators either as a stand-alone power stage that can deliver up to 50 A or with an interleaved approach for higher current loads. The power MOSFETs are tailored for this device. The gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to +25 V. The closely coupled driver and MOSFETs enable efficiency improvements that are hard to match using discrete components. The power density for 2 transmitted power of this approach is approximately 40 W within a 36 mm area. 5.1 Driver Characteristics The gate driver of the TDA21220 has 2 voltage inputs, VCIN and VDRV. VCIN is the 5 V logic supply for the driver. VDRV is also 5 V and is used to drive the High and Low Side MOSFETs. Ceramic capacitors should be placed very close to these input voltage pins to decouple the sensitive control circuitry from a noisy environment. The MOSFETs selected for this application are optimized for 5 V gate drive, thus giving the end user optimized high load as well as light load efficiency. The reference for the power circuitry including the driver output stage is PGND and the reference for the gate driver control circuit (VCIN) is CGND. Referring to the Block Diagram page, VCIN is internally connected to the UVLO circuit and for VCIN voltages less than required for proper circuit operation will provide shut-down. VDRV supplies both, the floating high side drive and the low-side drive circuits. An active boot circuit for the high side gate drive is also included. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to prevent false GH turn on during insufficient power supply level condition (BOOT Cap charging/discharging sequence). During undervoltage both GH and GL are driven low actively; further passive pull-down (500 k) is placed across gate-source of both FETs. UVLO Output Logic Level “H” Enable Shutdown “L” VUVLO_F Figure 4 VUVLO_R VCIN Internal Output Signal from UVLO Unit Preliminary Data Sheet 11 Revision 1.9, 2011-03-31 TDA21220 Theory of Operation 5.2 Inputs to the Internal Control Circuits The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V. The PWM input has three-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time T_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is internally fixed to VPWM_O = 1.5 V level. Table 12 PWM Pin Functionality PWM logic level Driver output Low GL= High, GH = Low High GL = Low, GH = High Open (left floating, or High impedance) GL = Low, GH = Low The possibility to use a wide range of VCIN power supply voltages (from 4.5 V to 5.5 V) implies a shifting in the threshold voltages for the following parameters: VPMW_O, VPWM_H, VPWM_L. The typical behavior of these thresholds with the VCIN power supply is shown in the following graph: Figure 5 Variation of PWM Levels versus VCIN Logic Supply Voltage Attention: The VPWM_S also scales in the same way. The DISB# is an active low signal. When DISB# is pulled low, the power stage is disabled. The disable pin is pulled down also during the thermal shut down condition. Preliminary Data Sheet 12 Revision 1.9, 2011-03-31 TDA21220 Theory of Operation Table 13 DISB# Pin Functionality DISB# logic level Driver output Low Shutdown : GL = GH = Low High Enable : GL = GH = Active Open (left floating, or High impedance) Shutdown : GL = GH = Low The SMOD# feature is provided to disable the low sides MOSFET during active operation. When synchronized with the PWM signal, SMOD# intended to improve light load efficiency by saving the gate charge loss of the low-side MOSFET. Once left open, the pin is internally fixed to VSMOD#_O =3 V level. Table 14 SMOD# Pin Functionality SMOD# logic level Driver output Low Shutdown : GL = Low GH = PWM High Enable : GL = GH = Active Open (left floating, or High impedance) Enable : GL = GH = Active 5.3 Shoot Through Protection The TDA21220 driver includes gate drive functionality to protect against shoot through. In order to protect the power stage from overlap, both High Side and Low Side MOSFETs being on at the same time, the adaptive control circuitry monitors the voltage at the “VSWH” pin. When the PWM signal goes low, the High Side MOSFET will begin to turn off, after the propagation delay (T_pdlu). Once the “VSWH” pin falls below 1 V, the Low Side MOSFET is gated on after the predefined delay time, (T_pdhl). Additionally, the gate to source voltage of the High Side MOSFET is also monitored. When VGS(High Side) is discharged below 1 V, a threshold known to turn High Side MOSFET off, a secondary delay is initiated, (T_pdhl), which results in Low Side being gated “ON” irregardless of the state of the “VSWH” pin.This way it will be ensured that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See Figure 9 for more detail. GH and GL are monitoring pins to check the internal gate drive signals. 5.4 Safe Operating Area The maximum load current versus the temperature of the PCB (below the device) is given below: Safe Operating Area 60 Iload max (A) 50 40 30 20 Iload 10 0 0 25 50 75 100 125 150 PCB temperature (°C) Figure 6 Safe Operating Area Preliminary Data Sheet 13 Revision 1.9, 2011-03-31 TDA21220 Application 6 Application 6.1 Implementation +5v CBOOT 1u F CIN 10 9 8 4 3 2 CGND SMOD VCIN VDRV BOOT 5 1u F 1 PWM 2x22uF 2x1uF 1x0.1uF 11 40 12 39 DISB# VIN CGND VIN 13 38 NC 14 37 VSWH 15 36 CGND GL PGND 16 35 VSWH 17 34 VSWH 18 Signal GND 6 7 CGND GH NC V IN (+ 5 - 20 V) PHASE VIN 1Ω 1u F 33 19 32 20 31 Power GND 21 22 23 24 25 26 27 28 29 30 Figure 7 VOUT VSWH PGND L Pin Interconnection Outline (transparent top view) Note: 1. Pin PHASE is internally connected to VSWH node 2. It is recommended to place a RC filter between VCIN and VDRV as shown. 3. During power-up and down sequences, the PWM signal must be either low or tri-state (open voltage), but never high, in order to avoid uncontrolled output voltage. Preliminary Data Sheet 14 Revision 1.9, 2011-03-31 TDA21220 Application 6.2 Typical Application CBOOT VIN (+12V) VIN 1K PWM VDRV (+5V) +3.3V BOOT PHASE DISB# VDD VCIN Cb Rb DrMOS VDRV 1 L VSWH PGND SMOD# CGND TSEN PX3895 CBOOT FAULT VIN VR_EN VR_READY BVR_READY PWM ISEN1N SDA PWM2 SCL ISEN2N SADDR_M ISEN2P SADDR_L VCIN Cb Rb DrMOS PGND SMOD# CGND PWM3 CBOOT VIN ISEN3P VDIO L VSWH VDRV 1 ISEN3N SVID Interface PHASE DISB# PWM1 ISEN1P I2C Interface BOOT VCLK ISEN4N VADDR ISEN4P BOOT PHASE DISB# PWM4 PWM VCIN Cb Rb DrMOS VDRV 1 VSENP L VSWH PGND SMOD# CGND Rext_m VSENN VOUT Cext_m CBOOT VIN BOOT PHASE DISB# PWM Figure 8 VCIN Rb DrMOS VDRV 1 L VSWH Cb PGND SMOD# CGND Four Phases Voltage Regulator Typical Application (Simplified Schematic) Preliminary Data Sheet 15 Revision 1.9, 2011-03-31 TDA21220 Gate Driver Timing Diagram 7 Gate Driver Timing Diagram VPWM_H VPWM_H Three_State VPWM_L VPWM_L PWM T_pdll T_GLtsshd T_pts GL T_pdhl 1V T_GHtsshd T_pdlu T_pts T_pdhu GH 1V VSWH Note: VSWH during entering/exit to tristate behaves accordingly to inductor current. Figure 9 Adaptive Gate Driver Timing Diagram Preliminary Data Sheet 16 Revision 1.9, 2011-03-31 TDA21220 Gate Driver Timing Diagram DISBL# VDISB_H VDISB_L T_pdh(DISB) T_pdl(DISB) GH/GL Figure 10 DISB# Timing Diagram SMOD SMOD disabled SMOD disabled SMOD active PWM T_pdlu GL DCM CCM CCM VSWH Figure 11 SMOD# Timing Diagram Preliminary Data Sheet 17 Revision 1.9, 2011-03-31 TDA21220 Performance Curves – Typical Data 8 Performance Curves – Typical Data 8.1 Efficiency and Power Loss versus Vout Operating conditions (unless otherwise specified): VIN = +12 V, VCIN = VDRV = +5 V, VOUT = 0.8 V to 1.6 V, FSW = 362 kHz, 210 nH inductor (Cooper-FPI1108, DCR (typ) = 0.29 mΩ) TA = 25° C, load line = 0 mΩ, airflow = 100LFM, no heatsink. Efficiency and Power Loss reported herein includes only TDA21220 losses. Data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. 96 94 92 90 Efficiency (%) 88 86 Vout_362Khz_12V_0.8V Vout_362Khz_12V_1V 84 Vin_362Khz_12V_1.2V 82 Vout_362Khz_12V_1.35V Vout_362Khz_12V_1.6V 80 78 76 0 5 10 15 20 25 30 35 40 45 50 Output Load Current (A) Figure 12 Efficiency vs. VOUT Preliminary Data Sheet 18 Revision 1.9, 2011-03-31 TDA21220 Performance Curves – Typical Data 14 12 Vout_362Khz_12V_0.8V Power Loss (W) 10 Vout_362Khz_12V_1V Vout_362Khz_12V_1.2V 8 Vout_362Khz_12V_1.35V Vout_362Khz_12V_1.6V 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 Output Load Current (A) Figure 13 8.2 Power Loss vs. VOUT Efficiency and Power Loss versus Vin Operating conditions (unless otherwise specified): VIN = +10/12/14 V, VCIN = VDRV = +5 V, VOUT = 1.2 V, FSW = 362 kHz, 210 nH inductor (Cooper-FPI1108, DCR (typ) = 0.29 mΩ) TA = 25° C, load line = 0 mΩ, airflow = 100LFM, no heatsink. Efficiency and Power Loss reported herein includes only TDA21220 losses. Data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. Preliminary Data Sheet 19 Revision 1.9, 2011-03-31 TDA21220 Performance Curves – Typical Data 96 94 92 90 Efficiency (%) 88 86 Vin_362Khz_10V_1.2V 84 Vin_362Khz_12V_1.2V Vin_362Khz_14V_1.2V 82 80 78 76 0 5 10 15 20 25 30 35 40 45 50 35 40 45 50 Output Load Current (A) Figure 14 Efficiency vs. VIN 12 10 Vin_362Khz_10V_1.2V Vin_362Khz_12V_1.2V 8 Power Loss (W) Vin_362Khz_14V_1.2V 6 4 2 0 0 5 10 15 20 25 30 Output Load Current (A) Figure 15 Power Loss vs. VIN Preliminary Data Sheet 20 Revision 1.9, 2011-03-31 TDA21220 Performance Curves – Typical Data 8.3 Efficiency and Power Loss versus Switching Frequency Operating conditions (unless otherwise specified): VIN= +12 V, VCIN=VDRV= +5 V, VOUT=1.2 V, FSW = 296 kHz to FSW = 592 kHz, 210 nH inductor (Cooper-FPI1108, DCR (typ) =0.29 mΩ) TA = 25° C, load line = 0 mΩ, airflow = 100LFM, no heatsink. Efficiency and Power Loss reported herein includes only TDA21220 losses. Data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. 96 94 92 90 Freq_296Khz_12V_1.2V Freq_362Khz_12V_1.2V Efficiency (%) 88 Freq_407Khz_12V_1.2V 86 Freq_465Khz_12V_1.2V Freq_592Khz_12V_1.2V 84 82 80 78 76 0 5 10 15 20 25 30 35 40 45 50 Output Load Current (A) Figure 16 Efficiency vs. FSW Preliminary Data Sheet 21 Revision 1.9, 2011-03-31 TDA21220 Performance Curves – Typical Data 14 12 Freq_296Khz_12V_1.2V Freq_362Khz_12V_1.2V 10 Power Loss (W) Freq_407Khz_12V_1.2V 8 Freq_465Khz_12V_1.2V Freq_592Khz_12V_1.2V 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 Output Load Current (A) Figure 17 Power Loss vs. FSW Preliminary Data Sheet 22 Revision 1.9, 2011-03-31 TDA21220 Performance Curves – Typical Data 8.4 Driver Current versus Switching Frequency Operating conditions (unless otherwise specified): VIN= +12 V, VCIN=VDRV= +5V, VOUT=1.2V, from FSW = 296 kHz to FSW = 592 kHz, 210 nH inductor (Cooper-FPI1108, DCR (typ) = 0.29 mΩ) TA = 25° C, load line = 0 mΩ, airflow = 100 LFM, no heatsink. Efficiency and Power Loss reported herein includes only TDA21220 losses. Data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. 0.025 Idr Vs Fsw 0.02 0.015 0.01 0.005 0 296 Figure 18 362 407 465 592 IDR Vs FSW Preliminary Data Sheet 23 Revision 1.9, 2011-03-31 TDA21220 Mechanical Drawing 9 Figure 19 Mechanical Drawing Mechanical Dimensions Preliminary Data Sheet 24 Revision 1.9, 2011-03-31 TDA21220 Mechanical Drawing Figure 20 Footprint and Solder Stencil Recommendations Preliminary Data Sheet 25 Revision 1.9, 2011-03-31 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG