HIP0082, HIP0084 PRELIMINARY Quad Power Drivers with Serial Diagnostic Interface May 1998 Features Description • Low Side Power MOSFET Output Drivers - Output Voltage Clamp (Typ) . . . . . . . . . . . . . . . . 80V - Maximum Output Current . . . . . . . . . . . . . . . . 5A/2A - Output rDS(ON) (TJ = 150oC) (Max) . . . . . 0.57Ω/0.62Ω The HIP0082 and HIP0084 Quad Power Drivers contain four individually protected NDMOS transistor switches to drive inductive and resistive loads such as: fuel injectors, relays, solenoids, etc. The outputs are low-side switches driven by active-low CMOS logic inputs. Each output is protected against excessive current due to a short-circuit. Internal drain-to-gate zener diodes provide output clamping for over voltage. An integrated charge pump allows operation from a single 5V logic supply. Diagnostic circuits provide ground short (SG), supply short (SC) and open load (OL) detection for each of the four output stages and indicate over temperature. Diagnostic information may be read via a synchronous serial interface. Six bits of write/store data sets a long or short OL fault delay time for each output and sets Outputs 3 and 4 to a 2A or 5A current shutdown threshold. The HIP0084 is specified with controlled slew rate switching. • Controlled Slew Rate Switching (HIP0084) • Single Pulse Energy Rating . . . . . . . . . . . . . . . . . 70mJ • Programmable Output Over Current Shutdown Threshold - Bit Select 2A or 5A on Outputs 3 and 4 • Output Protection - Output Over Current Shutdown - Output Over Voltage Clamp - Over Temperature Diagnostic Feedback • Diagnostics for Shorts, Opens and Over Temperature • Synchronous Serial Interface with - 22-Bit Serial Diagnostic Register - SPI Compatible Interface Both types are fabricated in a Power BiMOS IC process and are intended for use in automotive and other applications with a wide range of temperature and electrical stress. They are particularly suited for driving high-current inductive loads requiring high breakdown voltage and high output current. Both types available in the 15 lead Power SIP or 20 lead PSOP packages with low thermal resistance for high power applications. • Single 5V Supply Operation with CMOS Logic Inputs • Supply Current, ICC , Full Load (Typ) . . . . . . . . . <10mA • Low θJC Power SIP Packages SIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W PSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2oC/W Ordering Information • -40oC to 125oC Operating Temperature PART NUMBER Applications • Drivers For - Solenoids - Relays - Power Output - Lamps - Injectors Steppers Motors Displays • System Use - Automotive - Appliances - Industrial - Robotics TEMP. RANGE(°C) PKG. NO. PACKAGE HIP0082AS1 -40 to 125 15 Ld SIP Z15.05A HIP0084AS1 -40 to 125 15 Ld SIP Z15.05A HIP0082AS2 -40 to 125 15 Ld SIP Z15.05B HIP0082AB -40 to 125 20 Ld PSOP M20.433 HIP0084AB -40 to 125 20 Ld PSOP M20.433 Pinouts HIP0082, HIP0084 (SIP) TOP VIEW HIP0082, HIP0084 (PSOP W/HEAT SLUG) TOP VIEW HEAT SINK TAB INTERNALLY CONNECTED TO PIN 8 GROUND (VSS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 INTEGRAL COPPER HEAT SINK ‘SLUG’ FOR PCB CONTACT OR EXT. HEAT SINK IN3 OUT3 IN1 OUT1 R/W VCC RST GND (VSS) TXD CLK CS OUT2 IN2 OUT4 IN4 GND (SLUG) IN4 OUT4 IN2 GND (VSS) OUT2 CS CLK TXD GND (SLUG) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND (SLUG) IN3 OUT3 IN1 GND (VSS) OUT1 R/W VCC RST GND (SLUG) FN3643.4 HIP0082, HIP0084 Block Diagram VCC (NOTE 1) ROL VBATT DOL LOAD 1 OF 4 CHANNELS RST VCC QOL POR OUTx INx QO S Q R OSC OL CHARGE PUMP VCC VCC OPENLOAD CURRENT SENSE OSC POR POR RST RESET DELAY OVER TEMP. SG SC (SHORT CIRCUIT) RST ISC REF (PROG. 3, 4) - TXD CLK CS DIAG. REG. R/W SHIFT REG. OL IOL(MAX) + REF FILTER - FILTER/ DELAY OL + IOLF REF WRITE/ STORE - SG + R/W (SHORT-TO-GND) VSG REF VSS (GND) VCC VBATT LOAD NOTE 2, CASE 1 HIP0084 OUTPUT STAGE OUTx NOTE 2, CASE 2 QO OL SG SC NOTES: 1. For Open-Load Detection, the HIP0082 has an internal series pullup resistor, ROL and diode, DOL connected from OUTx to VCC . 2. HIP0084 OL (Open-Load) Detection: Case 1: For OL Detection, an external series resistor and diode pullup connected from OUTx to VCC is needed. Case 2: If no failure distinction for OL or SG (Short-to-GND) is required, both faults may be detected (without distinction), with an external pulldown resistor. For either case, the pullup or pulldown resistors should be typically 10kΩ or greater. 2 HIP0082, HIP0084 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (Logic and Control), VCC . . . . . . . . . . . . -0.3V to 7V Power MOSFET Drain Voltage, VO (Note 3) . . . . . . -0.7 to VCLAMP Output Clamp Energy, EOK (See Note 5) . . . . . . . . . . . . . . . . 70mJ Input Voltage (Logic and Driver Inputs), VIN . . .-0.5V to VCC + 0.5V Maximum Output Current, Outputs 1 and 2 . . . . . . . . . . . . . . . . +2A Maximum Output Current, Outputs 3 and 4 . . . . . . . . . . . . . . . . +5A Maximum Total Output Current, All Outputs ON . . . . . . . . . . . . +8A Maximum Peak Output Current, IO(MAX), (Note 4) . . . . . -5A to ISC Thermal Resistance (Typical, Notes 5, 6, 7) θJA (oC/W) θJC (oC/W) Power SIP Package. . . . . . . . . . . . . . . 45 3 PSOP Package . . . . . . . . . . . . . . . . . . 40 2 Maximum Junction Temperature. . . . . . . . . . . . . . . -40oC to 150oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (During Soldering 10s) . . . . . . 300oC (PSOP - Lead Tips Only) Die Characteristics Operating Conditions Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . .VSS (Tab Ground) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns on the MOSFET to hold the Drain at the VCLAMP voltage. Refer to the Electrical Specifications Table for the VCLAMP voltage limits. 4. Each Output has Over Current Shutdown protection in the positive current direction. The maximum peak current rating is set equal to the minimum Over Current Shutdown as detailed in the Electrical Specification Table. In the event of an Over Current Shutdown the input drive is latched OFF. The output short must be removed and the input toggled OFF and ON to restore the output drive. 5. Refer to Application Note AN9416 for Single Pulse Energy and Device Dissipation rating information, including inductive load operation and other thermal stress characterization. 6. θJA is measured with the component mounted on an evaluation PC board in free air. 7. Maximum PSOP Package Dissipation at 125oC with 26oC/W Heat Sink (6 sq cm Copper PCB) is 0.96W. Electrical Specifications VCC = 5V ±10%, TA = -40oC to 125oC; Unless Otherwise Specified HIP0082 PARAMETER SYMBOL TEST CONDITIONS HIP0084 MIN TYP MAX MIN TYP MAX UNITS rDS(ON)1, Outputs 1 and 2, One Output ON, rDS(ON)2 IOUT = 2A, TJ = 150oC - - 0.62 - - 0.62 Ω rDS(ON)3, Outputs 3 and 4, One Output ON, rDS(ON)4 IOUT = 2A, TJ = 150oC - - 0.57 - - 0.57 Ω - - 0.5 Ω - - 0.5 Ω 73 80 90 V - - ±1.5 V POWER OUTPUTS Output ON Resistance (Normal Mode) Output ON Resistance (Normal Mode) rDS(ON)1, Outputs 1 and 2, One Output ON, rDS(ON)2 IOUT = 2A, TJ = 75oC Output ON Resistance (Normal Mode) rDS(ON)3, Outputs 3 and 4, One Output ON, rDS(ON)4 IOUT = 2A, TJ = 105oC Output Zener Clamp Voltage Matching Zener Clamp Voltage VZ ∆VZ Output Short Current Limit, Outputs 1 and 2 (Note 8) ISC(L) Output Short Current Limit, Outputs 3 and 4 (Note 8) ISC(L) Output Short Current Limit, Outputs 3 and 4 (Note 8) ISC(H) Short Circuit Current Filter Time tSC Output Capacitance CO IOUT = 40mA N/A 73 IOUT = 40mA, tZ = 100µs 80 90 N/A 2 - 3.4 3 - 5.1 A ISC Bit High 2 - 3.4 2 - 3.4 A ISC Bit Low 5 - 7.5 5 - 8.3 A - - 1 - - 3 µs - - 250 - - 250 pF VOUTX = 16V, f = 1MHz 3 HIP0082, HIP0084 Electrical Specifications VCC = 5V ±10%, TA = -40oC to 125oC; Unless Otherwise Specified (Continued) HIP0082 PARAMETER Positive Output Voltage Ramp Slew Rate, Inductive Load Switching Off SYMBOL SR1 TEST CONDITIONS IOUTX = 1A, Load 6mH, 12Ω ; Measure 25% to 75% of VZ HIP0084 MIN TYP MAX MIN TYP MAX UNITS 6 70 100 6 14 24 V/µs 2 9 20 V/µs 5.1 11 20.4 V/µs 0.75 1.5 3.75 V/µs 1 - 3 V/µs IOUTX = 1A, Load 6mH, 12Ω ; Measure 4V to 16V of VZ N/A IOUTX = 1A, Load 6mH, 12Ω ; Measure 75% to 95% of VZ Negative Output Voltage Ramp Slew Rate, Inductive Load Switching On SR2 VBATT = 12V, Load 6mH, 6Ω ; Measure 25% to 75%, VCC = 5V ±2% 0.75 VBATT = 12V, Load 6mH, 6Ω ; Measure 25% to 75%, TJ = 25oC, VCC = 5V ±2% Output Negative Voltage Ramp Fall Time tf IOUTX = 2A, From 90% to 10%, 6Ω Load Turn-Off Delay td(OFF) IOUTX = 2A, From 50% of INx to 10% of OUTx Turn-On Delay td(ON) IOUTX = 2A, From 50% of INx to 90% of OUTx 15 25 N/A - - 25 - 15 25 µs 0.5 - 3 - - 10 µs - - 10 µs N/A Matching Turn-On Delay ∆td(ON) - - ±3 µs Matching Turn-Off Delay ∆td(OFF) - - ±3 µs 10 µs Output Rise Time Output Leakage Current tr ILK For SR3 Postive Ramp Conditions From 10% to 90% of VZ - INx = High, VOUTX = 60V - - 10 VOUTX = 60V, VCC Open - - 10 INx = High, VOUTX = VCC+ to 60V N/A INx = Low, VOUTX = 0V to 60V, VCC = 0V µA N/A µA -10 - 10 µA -10 - 10 µA SUPPLY Power Supply Current ICC Standby, No Load - 7.5 15 - 7.5 15 mA Low VCC Shutdown Threshold VCC(LOW) (Note 9) 3.4 3.7 4.0 3.4 3.7 4.0 V Active Supply Range for RST Pin VCC(RST) 3.5 - 5.5 3.5 - 5.5 V INPUTS (INx, CS, CLK, RST, R/W, TXD) Low-Level Input Voltage VIL -0.3 - 0.2 X VCC -0.3 - 0.2 X VCC V High-Level Input Voltage VIH 0.7 x VCC - VCC + 0.3 0.7 x VCC - VCC + 0.3 V Input Hysteresis Voltage VHYS 0.85 1.2 2.25 0.85 1.2 2.25 V Reset Time after RST L→H tRST 48 - 80 48 - 80 µs Input Pull-Up Resistance RIN 50 - 150 50 - 150 kΩ IIH Logic High Input Voltage - - 2 - - 2 µA Three-State Leakage Current ILK_TXD CS = High, VTXD = VCC -5 - 5 -5 - 5 µA Logic High Output Voltage VTXDH IOH = -4mA, CS = Low VCC 0.4 - - VCC 0.4 - - V Logic Low Output Voltage VTXDL IOL = 3.2mA, CS = Low - - 0.42 - - 0.42 V Input Current TXD PIN (R/ W = High) 4 HIP0082, HIP0084 Electrical Specifications VCC = 5V ±10%, TA = -40oC to 125oC; Unless Otherwise Specified (Continued) HIP0082 PARAMETER SYMBOL TEST CONDITIONS HIP0084 MIN TYP MAX MIN TYP MAX UNITS rDS(ON)1OL Outputs 1 and 2, One Output ON, rDS(ON)2OL IOUT = 10mA, TJ = 150oC - - 6.2 rDS(ON)3OL Outputs 3 and 4, One Output ON, rDS(ON)4OL IOUT = 10mA, TJ = 150oC - - 5.7 Ω mA OPEN LOAD DETECTION Output ON Resistance in High rDS(ON) Open-Load Detection Mode Max. Output Current in High rDS(ON) Mode IOL(MAX) 90 - 180 Min. Output Current in Low rDS(ON) Normal Mode (Hysteresis Range) IO(HYS) 0.25 x IOL - 0.95 x IOL Open-Load Fault Threshold IOLF Open-Load Detection Pull-up Resistance ROL (MAX) (ISC Bit is set in Fault Register) Open-Load Delay Time after INx H→L tDOLL Td_OLx Bit = Low Open-Load Delay Time after INx H→L tDOLH Td_OLx Bit = High (Note 10) Open Load Filter Time tOL Ω N/A mA NA (MAX) 15 60 100 mA 3 - 20 2 - 6.5 3 - 5.2 3 - 5.2 ms 340 - 580 340 - 580 µs 150 - 252 150 - 252 µs kΩ NA OVER TEMPERATURE AND SHORT CIRCUIT PROTECTION Over Temperature Detection Threshold TTMP 155 - 165 155 - 165 οC Output Short-to-Gnd Threshold VSG 2.4 - 2.9 2.4 2.6 2.9 V Short-to-GND Filter Time tSG 150 - 252 150 - 252 µs - - 3 - - 3 MHz SERIAL INTERFACE (Figure 3) CEXT = 50pF Serial Clock Frequency fCLK 50% Duty Cycle Propagation Delay CLK to Data Valid tPCLKDV - - 150 - - 150 ns Setup Time, CS to CLK tCSLCLK 150 - - 150 - - ns CS Low to Data Valid tCSLDV - - 100 - - 100 ns Hold Time CS after CLK tCLKCSH 150 - - 150 - - ns CS High to Output High Z tCSHDZ - - 100 - - 100 ns Minimum Time CLK = High tCLKH 100 - - 100 - - ns Minimum Time CLK = Low tCLKL 100 - - 100 - - ns Setup Time R/ W Low to CLK tRWLCLK 150 - - 150 - - ns R/ W Low to Output High Z tRWLDZ - - 100 - - 100 ns Setup Time Data Valid to CLK Low tDVCLKL 20 - - 20 - - ns Setup Time R/ W High to CLK tRWHCLK 100 - - 100 - - ns Time R/ W High to Data Valid tRWHDV - - 100 - - 100 ns NOTES: 8. Each Output has Over Current Shutdown protection in the positive current direction. The maximum peak current rating is set equal to the minimum Over Current Shutdown as detailed in the Electrical Specification Table. In the event of an Over Current Shutdown the input drive is latched OFF. The output short must be removed and the input toggled OFF and ON to restore the output drive. 9. The “Low VCC Shutdown” is an internal control that switches off all power drive stages when VCC is less than VCC(LOW). 10. Measurement includes the Filter Time. 5 HIP0082, HIP0084 Functional Description 2A and 5A with the ISC bit. After shutdown, the output remains off until the corresponding input is taken high and again low. Power Output Stages The Block Diagram details the equivalent logic control of each power output driver. Each power output stage has a separately controlled input with hysteresis and is active low with a pull-up to maintain an off state when there is no input. Each output driver has sensors for short circuit, open load and short-to-ground fault detection. The drive to each output is also controlled by the POR, Reset and an RS latch that switches off the output when a short circuit occurs. An internal zener diode feedback from the drain to gate of the output driver provides over voltage clamp protection. Open-Load (OL) Detection Load currents are monitored while the outputs are ON. If the open load current falls below the fault threshold current, IOLF , the open load fault bit is set after a delay time tDOL. The open load fault bits (OLx) are stored in the diagnostic register as shown in Figure 1. The output of open-load detector circuit is input to the Diagnostic Register via the delay filter and is also connected directly to the R/W Shift Register for potential monitoring via the serial interface. For the HIP0082, each power output channel has a low rDS(ON) (QO) and a high rDS(ON) (QOL) NDMOS drivers in parallel. The high rDS(ON) driver is used to enhance the open load detection while providing one-tenth of the output load current. For the HIP0082 in an ON state, if a load current falls below the IOL threshold level, a low load current condition is detected and the low rDS(ON) , high current DMOS output transistor (QO) is switched off. The high rDS(ON) driver (QOL) continues to conduct. If the load current is then increased from a low level, QO will be switched on, with hysteresis, to a normal mode of operation as defined by the IOL(HYS) limits. When the output current is higher than IOL(MAX) , both QO and QOL conduct. The HIP0084 output is modified into one low rDS(ON) driver and provides controlled slew rate switching. In addition, the HIP0084 requires an external zener and resistor network for OL detection. Refer to the Block Diagram, Specifications and OL Detection information. Reset Operation The HIP0084 OL detection diagnostics differ from the HIP0082. The HIP0084 does not have an internal pullup resistor (shown in the Block Diagram of the HIP0082 as ROL in series with the diode, DOL) connected between OUTx and VCC . Where no failure distinction between an OL and a SG fault condition is required, an external pulldown resistor from OUTx-to-Ground may be used. For a distinction between an OL and SG fault condition, an external pullup resistor in series with a diode between OUTx and VCC is needed. The pullup resistor must have a value greater than (VCC - VBE - VSG)/IOLF where VCC is the external power supply voltage for the outputs, VBE is the diode drop of the series diode; VSG is the short-toground comparator threshold level for OUTx and IOLF is the open-load current detection threshold of OUTx. While the values for pullup and pulldown resistors are not critical, they should not be minimally small. In either case, they should be typically 10kΩ or greater. An active low reset on the RST pin or the writing of a Low to the Test Bit is required to guarantee normal operation after power-up. When RST is in the low state all outputs are off and all registers and counters are reset. When the reset pin is taken high the IC remains in reset mode for a time tRST . When the RST pin is switched active low, the on-chip reset circuitry ensures that the output stages are turned off, all counters and registers are reset, and the programmable functions are in their default states. The default state for the Test Bit is a Low. The default state for the short-circuit current for outputs 3 and 4 is the higher value for 5A maximum current operation (ISC Bit Low). The default state for the open-load delay times for each output is the higher value between 3ms and 5.2ms (Td_OLx Bits Low). Low Power Drive Shutdown As part of the POR function, there is a low voltage power drive shutdown when the supply voltage, VCC drops below the voltage threshold, VCC(LOW) . During the low voltage condition the output stages are held off. Output Short-to-Ground (SG) Detection When the voltage on an output pin is below VSG and the output is off, a ground short is detected and stored in the diagnostic register after a delay tSG. The outputs of the short-to-ground (SG) comparators are also connected directly to the diagnostic register so that they can be monitored via the serial interface. Where VSG is specified in the range of 2.4V to 2.9V, IOLF is specified in the range of 15mA to 100mA for the HIP0084 and 3mA to 20mA for the HIP0082. Over Voltage Clamp Operation A drain-to-gate zener diode on each output driver internally clamps an over voltage pulse, including the kick pulse generated when turning off an inductive load. While providing over voltage protection, it is not part of the diagnostic feedback via the Diagnostic Register. Short-Circuit (SC) Protection Serial Interface Operation If the output current is above the current limit for a time delay greater than tSC the output is switched off and the corresponding bit in the diagnostic register set. The current level for shutdown on outputs 3 and 4 is programmable between Microprocessor communication to the diagnostic/control registers is via a 4 wire serial interface. Data control is bidirec- 6 HIP0082, HIP0084 tional, the direction of data transfer being dependent on the state of the R/W pin (See Figure 2). CLK CS R/W TXD ZZZZ FSB TMP SC1 OL1 SG1 SC2 OL2 SG2 SC3 OL3 ZZ = HIGH IMPEDANCE SG3 SC4 OL4 SG4 OL1 SG1 OL2 SG2 OL3 SG3 OL4 SG4 ZZ DIRECT COMPARATOR OUTPUTS FIGURE 1. SERIAL INTERFACE READ OPERATION Diagnostic Read Operation bits to the Write/Store register to influence the IC mode of operation. The write operation is illustrated in Figure 3. The FSB (First Significant Bit) is present when CS pin goes from high to low while the CLK pin is high and the R/W pin is in the high (read) state. The FSB is the error flag and is the same FSB bit shown for the Figure 1 read operation. When FSB is high, a read operation is assumed, until or unless the R/W goes low. When the R/W pin goes low (write mode), TXD is ready to receive input data. The first write bit occurs when CLK goes low. When CS goes from high to low (while CLK is high), data from the diagnostic register is jammed into the serial shift register, At the same time, the TXD pin exits three-state and outputs the FSB bit which indicates whether any of the fault bits in the shift register are set. With the first negative transition of CLK, the diagnostic register is cleared. Data from the shift register is shifted to TXD on each low to high transition of the CLK pulse. The Diagnostic Fault Bits as shown in Figure 1 are described as follows: In the write mode, data is latched in the Write/Store register when CS goes high. The Write/Store data will be in the default state after a RST reset or power up reset. The write operation does not affect the data present in the Diagnostic Register and a read operation does not affect the data present in the Write/Store Register. FSB Bit - Indicates that one or more of the bits in the diagnostic register are set. TMP Bit - Indicates that the chip temperature has exceeded the limit TTMP . The outputs are not switched off when this occurs; the condition is indicated by the setting of the TMP bit. Sensors for the TMP bit are located near the power drivers and are ORed to provide a single bit for the chip. The programmable bits in the Write/Store register are: Test Bit - Used to put the IC in test mode (not recommended). This bit should be low for normal operation. SCx Bits - Indicate a short-circuit to battery or over current on the corresponding output. The corresponding output driver has been latched off. It will remain off until the input is toggled off and then on. ISC Bit - This bit programs the short circuit level for outputs 3 and 4. When this bit is set high the lower value for the current shutdown threshold is set. OLx Bits - Indicate that no load (or a high resistance load) is connected to the corresponding output. The open load bit is set when the output current is less than IOLF . Td_OLx Bits - The tDOL delay times for the Td_OLx Bits are programmable to two levels (tDOLL or tDOLH). These bits set the delay times for the open-load detection at each of the four outputs. A logical high sets the open-load delay time to its shorter value. SGx Bits - Indicate that the voltage on the corresponding output is below the VSG limit. The final 8 bits (most significant bits) of the diagnostic word indicate the states of the open load and short-to-ground comparators when the CS pin went from high to low. As such, an external microprocessor can monitor the status of the OL and SG comparators directly to cross-check the action of the filtered fault bits, OL1 to OL4 and SG1 to SG4 (See Figure 1). The action of the filters is to suppress switching anomalies that may be read as false data. To avoid potential confusion in normal operation, reading the direct comparator output bits is not necessary or recommended. Reading Serial Data on the SPI Interface When interfacing to an 8-bit SPI system and choosing to read all 22 bits as shown in Figure 1, note that the FSB (First Significant Bit) is the first bit present before the first CLK pulse goes low. This leaves 21 bits of available output data to be shifted by the CLK. An FSB high state when CS goes low indicates the presents of a fault bit in the Diagnostic Register. The FSB bit is normally used as a flag to initiate a read of all data bits in the shift register. The FSB output bit should be separately directed to an interrupt or port that is programmed to initiate a fault data read sequence. Diagnostic Write Operation When the R/W pin is in the low state it is possible to write six 7 HIP0082, HIP0084 Since SPI data is read 8 bits at a time, reading 24 bits leaves 3 (dummy) bits that follow after the 21 bits of diagnostic fault output data. Internally, the shift register has an input low state which will cause the last 3 bits shifted out to be low. fCLK tCLKL CLK tRWHCLK tCLKH tCSLCLK tCLKCSH tCSLDV CS tRWLCLK R/W tpCLKD tDVCLKL tRWLDZ TXD tRWHDV tCSHDZ ZZZZZ ZZ ZZ = HIGH IMPEDANCE FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM CLK CS R/W TXD ZZZZ FSB Td_OL1 Td_OL2 Td_OL3 Td_OL4 ISC TEST ZZZZ FIGURE 3. SERIAL INTERFACE WRITE OPERATION There is no need in normal operation to read the Direct Comparator output bits, except to directly read the fault state when CS goes low or to cross-check on the filtered OL and SG fault data. If the Direct Comparator data is ignored, then only 16 bits of SPI data is read. In this case the last 3 bits in the 16 bit sequence is the first 3 bits of Direct Comparator data which can be ignored. drive. This allows a single 5V supply to satisfy all logic and drive requirements. Data read from a SPI interface starts with the first clock pulse. The CS and R/W inputs cannot be changed while reading data from the shift register. And, as noted, an internal low on the shift register input causes low data bits to follow the 21 bits of diagnostic data. IN1 - IN4 - Active-low CMOS logic inputs which control the output stages OUT1 - OUT4. These inputs are provided with pull-up resistors. While the Write/Store operation calls for 6 bits of data, a SPI write will output 8 bits. The first 2 bits transmitted should be dummy bits. The 3-bit is the Test bit which should be low for normal operation. The Test bit is used to facilitate testing in the manufacturing process and is not recommended for other use. The 6 programmable bits are described in the section on Diagnostic Write Operation. CLK - Clock input for synchronous serial interface with internal pull-up resistor. This input must be high when CS transitions from high to low. OUT1 - OUT4 - Low-side output drivers with 0.62Ω (OUT1 and OUT2) or 0.57Ω (OUT3 and OUT4) on resistance. The outputs are provided with over current shutdown and over voltage clamping. Additionally, open-load and short-toground detection is carried out when the outputs are ON. RST - Active-low logic-level reset input with internal pull-up resistor. CS - Active-low chip select input for serial interface. This input has an internal pull-up resistor. R/ W - Read/write control pin for serial interface. This input controls whether the TXD pin is an input or output. This input has an internal pull-up resistor. Pin Descriptions TXD - Bidirectional data pin for serial interface. When R/W is high diagnostic data can be read from HIP0082. When R/W is low, 6 bits may be written to the internal program register. VCC and GND - 5V Supply and Ground connections. A charge pump is used to boost the Power MOSFET gate 8 HIP0082, HIP0084 B S Power Small Outline Plastic Package (PSOP) E2 2 PLACES (DATUM PLANE A) -C- PIN 1 MARKER N 3 2 1.10 MAX. X 45o b D1 A S 0.25 M C A S SEATING PLANE D e -A- D2 2 PLACES 0.25 M C B S 1 E3 -H- E1 -B- A 20 LEAD POWER SMALL OUTLINE PLASTIC PACKAGE INCHES MIN MAX MIN MAX A 0.122 0.142 3.10 3.60 - A1 0.004 0.012 0.10 0.30 - A2 0.118 0.130 3.00 3.30 - A3 0.000 0.004 0.00 0.10 - b 0.016 0.021 0.40 0.53 6, 7 b1 0.016 0.020 0.40 0.50 6, 7 c 0.009 0.013 0.23 0.32 7 c1 0.009 0.011 0.23 0.29 7 A1 0.10 C SEATING PLANE SEE DETAIL "A" 3.10 REF. 0.15 REF. B L A3 DETAIL "A" L1 GAUGE PLANE D 0.622 0.630 15.80 16.00 3 0.496 0.512 12.60 13.00 - D2 - 0.043 E 0.547 0.571 E1 0.429 0.437 E2 - 0.114 - 2.90 - E3 0.228 0.244 5.80 6.20 - 0.050 BSC 0.031 0.043 - 1.10 - 13.90 14.50 - 10.90 11.10 4 1.27 BSC 0.80 - 1.10 5 L1 0.014 BSC 0.35 BSC - N 20 20 - Rev. 0 3/96 NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "C" is a reference datum. Seating plane is defined by lead tips only. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. D measured at -H-. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 per side. E1 measured at -H-. 5. Dimension "L" is the length of terminal for soldering to a substrate. 6. The lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of the lead width dimension at maximum material condition. 7. Section "B-B" to be determined at 0.10mm to 0.25mm from the lead tip. 8. Controlling dimension: MILLIMETER. 9. Dimensions conform with JEDEC Outline MO-166AA Issue B. 0-8o B NOTES D1 L A2 MILLIMETERS SYMBOL e E HEAT SLUG M20.433 17.15 4.09 N 1.60 REF. 13.92 1.52 4.22 7.26 b1 c c1 2.87 0.71 4.09 b 2.21 1 SECTION "B-B" 9 e LAND PATTERN HIP0082, HIP0084 Single-In-Line Plastic Packages (SIP) D -X- Z15.05A (JEDEC MO-048 AB ISSUE A) 15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM A SEE TAB DETAIL F INCHES E E1 L1 -Y- TERMINAL N 3 R1 TERMINAL #1 L H e e3 e1 e2 B 0.024(0.61) M C L L L L L L L H H H H H H H H 0.010(0.25) M L -Z- Z X M Z TYP ALL LEADS Y M SYMBOL MIN MAX MIN MAX A 0.172 0.182 4.37 4.62 B 0.024 0.031 0.61 0.79 C 0.014 0.024 0.36 0.61 D 0.778 0.798 19.76 20.27 E 0.684 0.694 17.37 17.63 E1 0.416 0.426 10.57 10.82 E2 0.110 BSC 2.79 BSC e 0.050 BSC 1.27 BSC e1 0.200 BSC 5.08 BSC e2 0.169 BSC 4.29 BSC e3 0.700 BSC 17.78 BSC F 0.057 0.063 1.45 1.60 L 0.150 0.176 3.81 4.47 L1 0.690 0.710 17.53 N ØP Ø 0.015(0.38) M Z X S MILLIMETERS 15 18.03 15 ØP 0.148 0.152 3.76 3.86 R1 0.065 0.080 1.65 2.03 Rev. 1 4/98 E2 TAB DETAIL NOTES: 1. Refer to series symbol list, JEDEC Publication No. 95. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. N is the number of terminals. 4. Controlling dimension: INCH. 10 HIP0082, HIP0084 Single-In-Line Plastic Packages (SIP) -ZD Z15.05B A -X- 15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT “GULLWING” LEAD FORM F ØP E2 INCHES MIN MAX MIN MAX A 0.172 0.182 4.37 4.62 B 0.024 0.031 0.61 0.79 C 0.018 0.024 0.46 0.61 D 0.778 0.798 19.76 20.27 E E1 R1 -Y- e 15 C SURFACES B TYP 0.010 M Z X S Y M 0.684 0.694 17.37 17.63 0.416 0.426 10.57 10.82 E2 0.110 BSC 2.79 BSC e 0.050 BSC 1.27 BSC F 0.008 Z e3 E E1 e3 0.004 15 LEAD TIPS (NOTE 3) 0.700 BSC 0.057 HEADER BOTTOM L L1 0.063 17.78 BSC 1.45 1.60 L 0.065 0.080 1.66 2.03 L1 0.098 0.108 2.49 2.74 N 0o- 8o MILLIMETERS SYMBOL 15 15 ØP 0.148 0.152 3.76 R1 0.065 0.080 1.65 3.86 2.03 Rev. 1 11/97 NOTES: 1. Dimensioning and Tolerancing per ANSI Y14.5M - 1982. 2. N is the number of terminals. 3. All lead surfaces are within 0.004 inch of each other. No lead can be more than 0.004 inch above or below the header plane, ( -Z- Datum). BOTTOM VIEW 4. Controlling dimension: INCH. LAND PATTERN 0.814 0.407 CL OF 0.150 0.130 0.700 0.662 0.774 0.030 TYP 0.050 TYP 0.350 0.700 11