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High Speed, Dual Channel, 6A, MOSFET Driver With
Programmable Rising and Falling Edge Delay Timers
ISL89367
Features
The ISL89367 is a high-speed, 6A, 2 channel MOSFET driver
optimized for synchronous rectifier applications. Internal timers
can be programmed with resistors to delay the rising and/or
falling edges of the outputs. Logically ANDed dual inputs are also
provided. One input is for the PWM signal and the second can be
used as an enable. A third control input is used to optionally
invert the logical polarity of the driver outputs.
• 2 outputs with 6A peak drive currents (sink and source) with
output voltage range of 4.5V to 16V
Comparator like logical inputs allows this driver to be configured
for any logic level from 3.3V to 10 VDC. The precision logic
thresholds provided by the comparators allow the use of external
RC circuits to generate longer time delays than are possible with
the internal timers. The comparators also allow the driver to be
configured with a low output voltage that is negative relative to
the logic ground if desired. This is useful for applications that
require a negative turn-off gate drive voltage for driving FETs with
logic thresholds.
At high switching frequencies, these MOSFET drivers use very
little bias current. Separate, non-overlapping drive circuits are
used to drive each CMOS output FET to prevent shoot-thru
currents in the output stage.
The start-up sequence is design to prevent unexpected glitches
when VDD is being turned on or turned off. When VDD < ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V < VDD < UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
VDD > UVLO, and after a short delay, the outputs now respond to
the logic inputs.
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• EPAD provides very low thermal impedance (JC = 3°C/W)
• Dual logic inputs with hysteresis for high noise immunity
• Rising and/or falling output edge delays programmed with
resistors
• 20ns rise and fall time driving a 10nF load
• Flexible logic options available by use of INVA and INVB pins
Applications
• Synchronous Rectifier (SR) Driver
• Switch mode power supplies
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer Driver
• Clock/Line Driver
Related Literature
• AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”
3.3V
ENABLE
VREF+
FDELA
INVA
RDELA
12V
/OUTA
OUTB
GND
PWM
RDELB
INVB
FDELB
VREF-
RISING OR FALLING EDGE DELAY (ns)
350
300
+125°C (WORST CASE)
250
200
150
+25°C (TYPICAL)
100
50
0
-40°C (WORST CASE)
0
5
10
15
20
RDT (2k TO 20k)
FIGURE 1. TYPICAL APPLICATION
October 8, 2012
FN7727.1
1
FIGURE 2. PROGRAMMABLE TIME DELAYS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL89367
Block Diagram
VREF+
VDD
For clarity, only one
channel is shown
Separated gate drives
prevent shoot-thru currents
in the output CMOS FETs.
RDELx
IN1x
The positive threshold is
63% of ((VREF+)-(VREF-)).
Rising edge
is delayed
Delay
Timer
OUTx
The negative threshold is
37% of ((VREF+)-(VREF-)).
Falling edge
is delayed
Delay
Timer
10K
INVx
IN2x
FDELx
VREFEPAD
2
For proper thermal and
electrical performance, the
EPAD must be connected to
the PCB signal ground plane.
VSS
FN7727.1
October 8, 2012
ISL89367
Pin Configurations
Pin Descriptions
ISL89367
(16 LD TDFN, EPSOIC)
TOP VIEW
PIN
NUMBER
VREF+
1
16
FDELA
INVA
2
15
RDELA
IN1A
3
14
VDD
IN2A
4
13
OUTA
IN1B
5
12
OUTB
IN2B
6
11
VSS
INVB
7
10
RDELB
9
FDELB
VREF-
8
EPAD
TRUTH TABLE
INVx
IN1x
IN2x
OUTx
0
0
0
0
0
0
1
0
0
1
0
0
IN1x
0
1
1
1
IN2x
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
INVx
OUTx
SYMBOL
DESCRIPTION
1, 8
VREF+
VREF-
VREF+ and VREF- are the reference voltages for
the IN1A, IN1B, IN2A, and IN2B logic inputs.
VREF+ is normally connected to the positive bias
voltage of the input logic. VREF- is normally
connected to the ground reference of the input
logic.
2, 7
INVA or
INVB
Connect these pins to VDD to invert the
corresponding output. Connect to VSS to not
invert the corresponding output.
3, 4,
5, 6
IN1A,
IN2A,
IN1B,
IN2B
ANDed logical inputs. One input to each channel
can be used as an enable. Logic high threshold is
63% of [(VREF+) - (VREF-)]. Logic low threshold is
37% of [(VREF+) - (VREF-)].
9, 16
FDELB,
FDELA
Connect a resistor between these pins and VSS to
program the duration of the falling edge
propagation delay of the corresponding output
relative to the logic inputs.
10, 15
RDELB,
RDELA
Connect a resistor between these pins and VSS to
program the duration of the rising edge
propagation delay of the corresponding output
relative to the logic inputs.
11, 14
12, 13
VSS, VDD Output bias voltage. (VDD to VSS) range is 4.5V to
16V. VSS may be negative relative to VREF-.
OUTB,
OUTA
6A peak outputs. Output voltage swing is
between VDD and VSS.
EPAD
Must be connected to logic ground (VREF-).
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL89367FRTAZ
PART MARKING
9367A
TEMP RANGE
(°C)
INPUT CONFIGURATION
-40 to +125
Non-inverting
PACKAGE
(Pb-Free)
16 Ld 3x5 TDFN
PKG.
DWG. #
L16.5x3
NOTES:
1. Add “-T”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89367. For more information on MSL, please see Technical Brief
TB363.
3
FN7727.1
October 8, 2012
ISL89367
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD Relative to VSS . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
VREF+ Relative to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
VREF- Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V to VSS - 0.3V
INVx (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS - 0.3V to VDD + 0.3V
INnx (Note 5) Relative to VREF- . . . . . . . . . (VREF-) - 0.3V to (VREF+) + 0.3V
VREF+ Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
VREF+ Relative to VREF- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
Average Output Current (Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . 200V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Latch-Up
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 Ld TDFN Package (Notes 6, 7) . . . . . . .
36
3
Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . . 2.8W
Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . . 33.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Recommended Operating
Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, VDD Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . 0V to 16V
VREF- Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V to VSS
INVx (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS or VDD
INnx (Note 5) Relative to VREF- . . . . . . . . . . . . . . . . . . . . . . . . VREF- to VREF+
VREF+ Relative to VSS, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 10V
VREF+ Relative to VREF-, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 10V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Substitute INVA or INVB for INVx.
5. Substitute IN1A, IN2A, IN1B, or IN2B for INnx
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current (sinking and
sourcing). The peak output currents of this driver are self limiting by transconductance or rDS(ON) and do not required any external components to
minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to
less than the specified absolute average output current.
DC Electrical Specifications
VDD = 12V, GND = 0V, No load on OUTA or OUTB, RDELA = RDELB = FDELA = FDELB = 0kΩ unless
otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
TJ = +25°C
PARAMETERS
TJ = -40°C to +125°C
MIN
(Note 9)
TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
UNITS
-
-
-
4.5
16
V
INx = GND
-
5
-
-
-
mA
INA = INB = 1MHz, square wave
-
25
-
-
mA
SYMBOL
TEST CONDITIONS
POWER SUPPLY
Voltage Range (VDD relative to
VSS)
VDD
VDD Quiescent Current
IDD
VREF+ AND VREF- BIAS
VREF+ Relative to VSS
VP-S
3
-
10
3
10
V
VREF- Relative to VSS
VN-S
0
-
4
0
4
V
VREF+ Relative to VREF-
VP-N
3
-
10
3
10
V
VREF+ Quiescent Current
IPP
VP-N = 12V
-
200
-
100
300
µA
VUV
INnx = True (Note 12)
-
3.3
-
-
-
V
-
~25
-
-
-
mV
UNDERVOLTAGE
VDD Undervoltage Lock-out
(Note 11)
Hysteresis
4
FN7727.1
October 8, 2012
ISL89367
DC Electrical Specifications
VDD = 12V, GND = 0V, No load on OUTA or OUTB, RDELA = RDELB = FDELA = FDELB = 0kΩ unless
otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = -40°C to +125°C
MIN
(Note 9)
TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
UNITS
-
-
-
Vref-
Vref+
V
-
-
-
VSS
VDD
V
-
37
-
34
40
%
-
63
-
60
66
%
-
0.9
-
1
1.2
V
-
1.5
-
1.5
1.7
V
-
2
-
-
-
pF
-
-
-
-10
+10
µA
-
-
-
-40
+40
µA
VDD - 0.1
VDD
V
GND
GND + 0.1
INPUTS
Input Range for
IN1A, IN2A, IN1B, IN2B
VIN
Input Range for INVA, INVB
VINV
Logic 0 Threshold for IN1A,
IN2A, IN1B, IN2B
VIL
Logic 1 Threshold for IN1A,
IN2A, IN1B, IN2B
VIH
Logic 0 Threshold for INVA,
INVB
VILV
Logic 1 Threshold for INVA,
INVB
VIHV
Input Capacitance of IN1A,
IN2A, IN1B, 1N2B, INVA, INVB
CIN
Input Bias Current for
IN1A, IN2A, IN1B, IN2B
IIN
Input Bias Current for
INVA, INVB
IINV
VIN is referenced to VREFVINV is referenced to VSS
Nominally 37% x ((VREF+) - (VREF-))
Nominally 63% x ((VREF+) - (VREF-))
VILV is referenced to VSS
VIHV is referenced to VSS
VREF- < VIN < VREF+
VSS < VINV < VDD
OUTPUTS
High Level Output Voltage
VOHA VOHB
-
-
-
Low Level Output Voltage
VOLA
VOLB
-
-
-
V
Peak Output Source Current
IO
VO (initial) = 0V, CLOAD = 10nF
-
-6
-
-
-
A
Peak Output Sink Current
IO
VO (initial) = 12V, CLOAD = 10nF
-
+6
-
-
-
A
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
11. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9.
12. The true state of a specific part number is defined by the input logic symbol.
AC Electrical Specifications
VDD = 12V, GND = 0V, No Load on OUTA or OUTB, RDELA = RDELB = FDELA = FDELB = 0kΩ unless
otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
TJ = -40°C
to +125°C
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
/NOTES
MIN
(Note 9)
TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
UNITS
Output Rise Time (see Figure 4)
tR
CLOAD = 10nF,
10% to 90%
-
20
-
-
40
ns
Output Fall Time (see Figure 4)
tF
CLOAD = 10nF,
90% to 10%
-
20
-
-
40
ns
-
25
-
-
50
ns
Output Rising Edge Propagation Delay (see Figure 3)
5
tRDLYA,
tRDLYB
FN7727.1
October 8, 2012
ISL89367
AC Electrical Specifications
VDD = 12V, GND = 0V, No Load on OUTA or OUTB, RDELA = RDELB = FDELA = FDELB = 0kΩ unless
otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
TJ = -40°C
to +125°C
TJ = +25°C
PARAMETERS
Output Falling Edge Propagation Delay (see Figure 3)
SYMBOL
TEST CONDITIONS
/NOTES
tFDLYA,
tFDLYB
MIN
(Note 9)
TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
UNITS
-
25
-
-
50
ns
Rising Propagation Matching (see Figure 3)
tRM
RDELx = 0kΩ,
FDELx = 0kΩ
-
<1
-
-
-
ns
Falling Propagation Matching (see Figure 3)
tFM
RDELx = 0kΩ,
FDELx = 0kΩ
-
<1
-
-
-
ns
RDELx = 20kΩ,
No load
-
270
-
237
297
ns
RDELx = 2.0kΩ,
No load
-
45
-
29
58
ns
FDELx = 20kΩ,
No load
-
270
-
237
297
ns
FDELx = 2.0kΩ,
No load
-
45
-
29
58
ns
-IMP
VDD = 10V,
VMILLER = 5V
-
6
-
-
-
A
-IMP
VDD = 10V,
VMILLER = 3V
-
4.7
-
-
-
A
-IMP
VDD = 10V,
VMILLER= 2V
-
3.7
-
-
-
A
IMP
VDD = 10V,
VMILLER = 5V
-
5.2
-
-
-
A
IMP
VDD = 10V,
VMILLER = 3V
-
5.8
-
-
-
A
IMP
VDD = 10V,
VMILLER = 2V
-
6.9
-
-
-
A
Rising Edge Timer Delay
(Note 13)
tRTDLY
Falling Edge Timer Delay
(Note 13)
tTDLY
Miller Plateau Sink Current
(See Test Circuit Figure 5)
Miller Plateau Source Current
(See Test Circuit Figure 6)
NOTE:
13. Delays for timing resistors < 2.0kΩ or > 20kΩ are not specified and are not recommended. The resistors tolerances (including the boundary values
of 2.0kΩ and 20.0kΩ) are recommended to be 1% or better.
6
FN7727.1
October 8, 2012
ISL89367
Test Waveforms and Circuits
3.3V
63%
37%
INnx
0V
tRDLYA
tFDLYA
50%
90%
50%
OUTA
tRDLYB
OUTA
or
OUTB
tFDLYB
50%
10%
tR
tF
50%
OUTB
tRM
tFM
FIGURE 3. PROP DELAYS AND MATCHING
FIGURE 4. RISE/FALL TIMES
10V
10V
ISL8916x
ISL8916x
10k
0.1µF
0.1µF
10k
VMILLER
VMILLER
10µF
10µF
200ns
200ns
+ISENSE
+ISENSE
10nF
10nF
0.1
0.1
-ISENSE
FIGURE 5. MILLER PLATEAU SINK CURRENT TEST CIRCUIT
-ISENSE
FIGURE 6. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT
10V
IM P
0A
CURRENT THROUGH
0.1 RESISTOR
V M ILLER
V OUT
V OUT
V MILLER
-I MP
CURRENT THRO UGH
0.1 RESISTO R
0
0V
200ns
FIGURE 7. MILLER PLATEAU SINK CURRENT
7
200ns
FIGURE 8. MILLER PLATEAU SOURCE CURRENT
FN7727.1
October 8, 2012
ISL89367
Test Waveforms and Circuits
(Continued)
Rising VDD
This duration is dependant
on rise time of VDD
3.3V UV Threshold
This duration is
independent on
rise time of VDD
~1V
10k to
ground
Ω
outputs controlled by
logical inputs
outputs
active low
OUTA, OUTB
OUTPUT STATE
Up to 400µs
<1 to ground
FIGURE 9. START-UP SEQUENCE
Typical Performance Curves
3.5
35
+125°C
1MHz BIAS CURRENT (mA)
STATIC BIAS CURRENT (mA)
+125°C
3.0
+25°C
-40°C
2.5
2.0
4
8
12
VDD
FIGURE 10. IDD vs VDD (STATIC)
8
16
30
+25°C
25
-40°C
20
15
10
5
4
8
12
16
VDD
FIGURE 11. IDD vs VDD (1MHz)
FN7727.1
October 8, 2012
ISL89367
Typical Performance Curves (Continued)
1.1
50
16V
NO LOAD
0.9
10V
30
rDS(ON) (Ω)
IDD (mA)
40
VOUT LOW
1.0
12V
20
5V
0.7
10
0
VOUT HIGH
0.8
0.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.5
-45
2.0
1.8
-20
5
FREQUENCY (MHz)
80
105
130
30
25
PROPAGATION DELAY (ns)
FALL TIME, CLOAD = 10nF
20
RISE TIME, CLOAD = 10nF
-20
5
30
55
80
TEMPERATURE (°C)
105
OUTPUT FALLING PROP DELAY
25
OUTPUT RISING PROP DELAY
20
15
5
130
7
9
11
13
15
VDD
FIGURE 15. PROPAGATION DELAY vs VDD
FIGURE 14. OUTPUT RISE/FALL TIMES
350
RISING OR FALLING EDGE DELAY (ns)
RISE/FALL TIME (ns)
55
FIGURE 13. rDS(ON) vs TEMPERATURE
FIGURE 12. IDD vs FREQUENCY (+25°C)
15
-45
30
TEMPERATURE (°C)
300
+125°C (WORST CASE)
250
200
150
+25°C (TYPICAL)
100
50
0
-40°C (WORST CASE)
0
5
10
15
20
RDT (2k TO 20k)
FIGURE 16. PROGRAMMABLE DELAY vs RDEL AND FDEL
9
FN7727.1
October 8, 2012
ISL89367
Functional Description
Overview
Note: In the following discussion, when a lower case “n” or “x” is
used in a pin name, the “n” can be replaced by “1” or “2” and “x”
can be replaced by “A” or “B”.
The ISL89367 drivers are designed specifically for Synchronous
Rectifier (SR) applications but can also be used for any MOSFET
driver application especially when a precision propagation time
delay is required for the output rising for falling edge (or both).
The fast rising (or falling) output drive current of the ISL89367
minimizes the turn-on (or off) delay due to the input capacitance
of the driven FET. The switching transition period at the Miller
plateau is also minimized by the high amplitude drive currents.
(See the specified Miller plateau currents in the AC Electrical
Specifications on page 6).
The start-up sequence for is designed to prevent unexpected
glitches when VDD is being turned on or turned off. When
VDD < ~1V, an internal 10kΩ resistor connected between the
output and ground, help to keep the gate voltage close to ground.
When ~1V < VDD < UV, both outputs are driven low while ignoring
the logic inputs. This low state has the same current sinking
capacity as during normal operation. This insures that the driven
FETs are held off even if there is a switching voltage on the drains
that can inject charge into the gates via the Miller capacitance.
When VDD > UVLO, and after a 400µs delay, the outputs now
respond to the logic inputs. See Figure 9 for complete details.
For the negative transition of VDD through the UV lockout voltage,
the outputs are active low when VDD < ~3.2VDC regardless of the
input logic states.
Input Logic Voltage Levels
The input logic (INnx) has thresholds of 37% (falling input) and
63% (rising input). The maximum VREF+ relative to VREF- is
10VDC. For typical 5V logic applications VREF+ = 5V, VREF- = 0V.
In a similar manner, applications with 3.3V logic VREF+ = 3.3V
and VREF- = 0V. Note that the INVx inputs have TTL compatible
thresholds, are VDD tolerant, and do not have precision
thresholds.
linearly between ~40ns and ~265ns for values from 2kΩ to
20kΩ. If no time delay is required, short RDELx and FDELx to VSS.
Programmed delays for resistor values <2k are not specified or
recommended. Resistor values >20k are also not recommended.
Delays Greater than 270ns
For application requiring delay durations longer than 270ns, the
ISL89367 also offers a solution. The input logic pins have
precision thresholds which are designed for precision time delays
of either the rising of falling edge of OUTx by using the time
constant of a resistor and capacitor. The logic inputs pins of the
driver, INnx, are connected to the positive inputs of the input
comparators. The positive and negative transition threshold
voltages are established on the negative inputs of these
comparator by a resistor divider that is biased by VREF+ and
VREF-. If VREF+ is connected to the bias voltage of the input logic
and if VREF- is connected to the ground of the input logic, then
the threshold transitions are proportional to the bias voltage of
the input logic. Consequently, the time delays are independent of
the accuracy of the input logic bias voltage.
Figure 17 illustrates a circuit that is used to delay the rising edge
of OUTA relative to the rising edge of the signal source. The value
of C should also be substantially larger than the input
capacitance of the input pin of the ISL89367, the parasitic
capacitance associated with the traces, and the output
capacitance, CDS of the signal FET Q1.
If the signal source is TTL or open drain, Ra is required but not for
CMOS.
The calculation of the rising delay is simply shown by Equation 1:
t delay = R b  C
(EQ. 1)
This is a consequence of the 37%/63% thresholds.
VREF+
INVA
Q1
Ra
IN1A
IN2A
OUTA
Rb
SIGNAL
SOURCE
VDD
FDELA
RDELA
ISL89367
C
only section A is shown
VREF-
VSS
Programmable Delays
The propagation time delays are programmed by resistors
connected between RDELx or FDELx and VSS. A resistor
connected to RDELx delays the rising edge of OUTx. Likewise, a
resistor connected to FDELx delays the falling edge of OUTx. The
resistors should be connected as close as possible to the pins to
prevent noise coupling into these connections. In extremely noisy
applications, it may be necessary to bypass the resistors with a
0.01µF or smaller decoupling capacitor. The time delay varies
10
SIGNAL
SOURCE
IN2A
OUTA
FIGURE 17. RISING OUTA TIME DELAY
FN7727.1
October 8, 2012
Ra
Rb
VREF+
INVA
FDELA
IN1A
RDELA
IN2A
OUTA
VDD
ISL89367
SIGNAL
SOURCE
Q1
only section A is shown
C
VREF-
VSS
SIGNAL
SOURCE
IN2A
OUTA
VGS GATE-TO-SOURCE VOLTAGE (V)
ISL89367
12
ID = 12A
VDS = 0V
10
VDS = 64V
8
6
VDS = 40V
4
2
0
0
2
4 6 8 10 12 14 16 18 20 22 24
QG, TOTAL GATE CHARGE (nC)
FIGURE 19. CHARGE OF A TYPICAL MOSFET
FIGURE 18. FALLING OUTA TIME DELAY
Figure 18 is used to delay the falling edge of OUTx. In this case
the rising time constant is Rb x C.
Logic States
The combinational control logic of the ISL89367 is very flexible.
The state of OUTx is the ANDed logic of both inputs, IN1x and
IN2x. The INVx input to the exclusive-OR gate is used to invert the
logic state of OUTx. Frequently, for SR applications, it is desirable
to have a logic control that can force OUTA = 0 for the purpose of
diode emulation. This “enable” control input can be either of the
IN1x or IN2x inputs of one channel. In Figure 1 on page 1, IN1A is
used as the enabled input for channel A. When this input is tied
to VREF+, OUTA follows the state of IN2x. If INA1 is connected to
VREF-, with INVA = 0, OUTA remains low no matter what state
IN2A is in.
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL89367 is less than
1ns. Note that the propagation matching is only valid when
FDELA = RDELA = 0kΩ and FDELB = RDELB = 0kΩ. The matching
is so precise that carefully matched and calibrated scopes
probes and scope channels must be used to make this
measurement. Because of this excellent performance, these
driver outputs can be safely paralleled to double the current drive
capacity. It is important that the INA and INB inputs be
connected together on the PCB with the shortest possible trace.
This is also required of OUTA and OUTB.
Figure 19 illustrates how the gate charge varies with gate
voltage, VGS, and the VDS of the driven MOSFET. Because an SR
is switched on and off when VDS = 0 and if we use VGS = 12V,
from the graph, QG = 13.5nC. In this example the dissipation of
the driver with frequency = 1MHz is shown by Equation 2:
P gate = 2  Qg  freq  V GS
= 2  17nC  1MHz  12
= 0.408W
(EQ. 2)
Notice that the dissipation of the driver is not a function of the
peak drive rating of the driver. Also if an external gate resistor is
used to limit the peak current output, the dissipation is
proportionally shared between the value of the gate resistor and
the rDS(ON) of the ISL89367 output.
Another parameter that must be considered is the dissipation
resulting from the bias current at the frequency of operation. For
the ISL89367 the bias current @ VDD = 12V and 1MHz is 24mA.
P bias = V DS  I bias = 12V  24mA = 0.288W
(EQ. 3)
P total = P gate + P bias + 0.408W + 0.288W = 0.696W
(EQ. 4)
The Thermal impedances of the ISL89367 are:
JC = 3°C/W
JA = 36°C/W
The temperature rise is:
T riseJC =  JC  P total = 2.09C
(EQ. 5)
TriseJC is the temperature rise referenced to the temperature of
the PCB ground plane under the part.
Power Dissipation and Die Temp
T riseJA =  JA  P total = 25C
The following is an example of how to calculate the power
dissipated by the ISL89367 driver. These calculations are
intended to give an approximate temperature rise of the die
junction. Because operating conditions such as air flow can
influence the actual temperatures, it is absolutely necessary to
confirm the operating temperatures in a specific application by
measuring the ISL89367 temperatures with an infra-red
temperature sensor or camera. Using a thermal couple to
measure the temperature of small devices is not recommended
because the thermal couple wire will act as a heat sink reducing
the temperature of the measured device to values less than what
will actually occur. See Tech Brief TB379 for more information.
In this example the temperature rise is relatively small for JC
and JA. Obviously the ISL89367 could drive significantly larger
FETs than what is used in this example.
11
(EQ. 6)
Output Current Rating
While the ISL89367 has a very high peak output current rating of
6A sourcing and sinking, there are limitations to the average
output current. With the high peak output current of the
ISL89367, it is tempting to use the driver as a general purpose
switch to drive loads that are not capacitive as are the gates of
MOSFETs. It is important to note that the maximum average
output current rating of the ISL89367 of 150mA must not be
FN7727.1
October 8, 2012
ISL89367
overlooked. While this value seems low, it is more than adequate
to drive very high gate charge values at high frequencies.
The average output current (sinking or sourcing) into a capacitive
load is:
Iavg = Qg x freq
or Qg = Iavg/freq
for a frequency of 1MHz and for the maximum average current of
150mA:
Q g = 150mA  1MHz = 150nC
(EQ. 7)
This charge is approximately 10x the value of the gate charge as
in the example of Figure 2 on page 1. Obviously, with lower
frequencies, this margin is even greater. It is likely that the
greater limitation of driving a large capacitive load could be the
power dissipation. If the driver dissipation is recalculated with a
value of 150nC, then:
P gate = 2  150nC  1MHz  12V = 3.6W
(EQ. 8)
T riseJA = 33  3.6W = 119C
(EQ. 9)
PCB Layout Guidelines
The AC performance of the ISL89367 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance:
• Place the driver as close as possible to the driven power FET.
• Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they are usually more effective
than parallel traces.
• Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
• It may be necessary to add resistance to dampen resonating
parasitic circuits especially on OUTA and OUTB. If an external
gate resistor is unacceptable, then the layout must be
improved to minimize lead inductance.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the ISL89367.
• Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated.
This must be accounted for in the PCB layout and circuit
design.
• If you simulate your circuits, consider including parasitic
components especially parasitic inductance.
EPAD Heatsinking
Considerations
The thermal pad is electrically connected to the GND supply
through the IC substrate. The EPAD of the ISL89367 has two
main functions: to provide a quiet GND for the input threshold
comparators and to provide heat sinking for the IC. The EPAD
must be connected to a ground plane and no switching currents
from the driven FET should pass through the ground plane under
the IC.
Figure 20 is a PCB layout example of how to use vias to remove
heat from the IC through the EPAD.
EPAD GND
PLANE
EPAD GND
PLANE
• When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
• The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
12
COMPONENT
LAYER
BOTTOM
LAYER
FIGURE 20. TYPICAL PCB PATTERN FOR THERMAL VIAS
For maximum heatsinking, it is recommended that a ground
plane, connected to the EPAD, be added to both sides of the PCB.
A via array, within the area of the EPAD, will conduct heat from
the EPAD to the GND plane on the bottom layer. The number of
vias and the size of the GND planes required for adequate
heatsinking is determined by the power dissipated by the
ISL89367, the air flow and the maximum temperature of the air
around the IC.
FN7727.1
October 8, 2012
ISL89367
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
October 2, 2012
FN7727.1
(page 1) Related literature added (AN1603)
(page 1) Last paragraph of the product description is changed to better describe the improved turn on
characteristics.
(page 1) Features list is revised to improve readability and to add new product specific features.
(page 4) Note and figure references are added to the VDD Under-voltage lock-out parameter.
(page 4) Thermal Information, removed Pb-Free Reflow link.
(page 5) Note 11 is revised to more clearly describe the turn-on characteristics.
(page 6) Test conditions added to the rising and falling propagation matching parameters.
(page 8) Figure 9 added to clearly define the startup characteristics.
(page 10) The paragraphs of the Functional Description Overview describing the turn-on sequence is replaced
by 3 paragraphs to more clearly describe the under voltage and turn-on and turn-off characteristics.
(page 11) A new section is added to the application information describing how the drivers outputs can be
paralleled.
January 31, 2011
FN7727.0
Initial Release
Products
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13
FN7727.1
October 8, 2012
ISL89367
Package Outline Drawing
L16.5x3
16 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 05/07
2.20
3.00
A
B
1.65
6
PIN 1
INDEX AREA
16
1
0.50
3.50
5.00
4.40
6
PIN 1
INDEX AREA
0.25
8 b 4
9
(4X)
0.15
0.10 M C A B
0.40 ± 0.1
TOP VIEW
BOTTOM VIEW
(16X 0.60)
0.10 C
0.75
SEE DETAIL "X"
(16X 0.25)
C
BASE PLANE
0.05 MAX
SEATING PLANE
0.08 C
4.40
SIDE VIEW
C
0.20 REF
5
0.05 MAX
(14X 0.50)
DETAIL "X"
1.65
2.20
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
14
FN7727.1
October 8, 2012