MOTOROLA PC33888APNBR2

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33888
Rev 3.0, 10/2004
SEMICONDUCTOR TECHNICAL DATA
Product Preview
33888
33888A
Quad High-Side and Octal Low-Side
Switch for Automotive
Freescale Semiconductor, Inc...
The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mΩ and two 40 mΩ) and an integrated
IC control die consisting of eight low-side drivers (600 mΩ each) with
appropriate control, protection, and diagnostic features.
SOLID STATE RELAY FOR
AUTOMOTIVE APPLICATIONS
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.
The 33888 is available in two power packages.
Features
• Dual 10 mΩ High Side, Dual 40 mΩ High Side, Octal 600 mΩ Low Side
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High Side Current Sense,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout
• SPI Reporting of Program Status and Fault
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection
Bottom View
Top View
PNB SUFFIX
APNB SUFFIX
CASE 1438-06
36-TERMINAL PQFN
(12 x 12)
FB SUFFIX
CASE 1315-03
64-TERMINAL PQFP
ORDERING INFORMATION
Device
Temperature
Range (TA)
PC33888PNB/R2
PC33888APNB/R2
-40°C to 125°C
MC33888FB/R2
VPWR
+5.0 V
8 x Relay or LED
33888
4
MCU
A/D
A/D
4
VPWR
FS VDD
IHS0:IHS3
LS4:LS11
ILS
RST
SPI
HS3
WDIN
HS2
CSNS2-3
HS1
CSNS0-1
HS0
FSI
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
For More Information On This Product,
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36 PQFN
64 PQFP
33888 Simplified Application Diagram
+5.0 V
Package
Loads
Freescale Semiconductor, Inc.
Table 1. Features Comparison: 33888 and 33888A
Symbol
Condition
33888
33888A
For details,
see page
Undervoltage Low-Side Output Shutdown
VPWRUV
–
5.0 V
3.0 V
11
Low-Side Drain-to-Source ON Resistance
RDS(ON)
VPWR = 4.5 V;
VDD = 3.5 V
Not specified
8.0 Ω
14
f SPI
Extended Mode,
VDD = 3.4 V
Not specified
2.1 MHz
(max)
17
Parameter
Recommended Frequency of SPI Operation
Freescale Semiconductor, Inc...
VDD
VPWR
VIC
Internal
Regulator
IUP
Over/Undervoltage
Protection
10 mΩ
CS
SCLK
Gate Driver
SPI
3.0 MHz
IDWN
HS0
Selectable Current Limit
SO
SI
RST
WAKE
FS
IN0
Open Load
Detection
Overtemperature
Detection
Logic
IN1
IN2
IN3
ILS
Gate Control and Fault 10 mΩ
HS0
Selectable Output Current
Recopy (Analog MUX)
HS1
HS1
Gate Control and Fault 40 mΩ
RDWN
HS2
HS2
IDWN
CSNS0-1
Selectable Output Current
Recopy (Analog MUX)
CSNS2-3
Gate Control and Fault 40 mΩ
HS3
HS3
VIC
WDIN
Watchdog
Gate
Control
FSI
Clamp
Overtemperature
ILIM
Open Load
x8
LS4
LS5
LS6
LS7
LS8
LS9
LS10
LS11
GND
Figure 1. 33888 Simplified Internal Block Diagram
33888
2
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SO
VDD
LS11
GND
LS10
LS9
LS8
LS7
LS6
LS5
GND
LS4
VPWR
FS
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CS
16
SCLK
17
SI
18
ILS
GND
36
WDIN
35
FSI
34
RST
19
33
WAKE
20
32
GND
21
IHS2
22
(Control Die)
Internally Connected to VPWR
23
31
IHS1
30
IHS0
29
CSNS0-1
(Power Die)
VPWR
25
26
27
HS0
24
HS1
CSNS2-3
GND
28
HS2
IHS3
15
HS3
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Transparent Top View of Package
TERMINAL DEFINITIONS FOR PQFN
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
1
Formal Name
Definition
FS
Fault Status
(Active Low)
This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.
2, 24
VPWR
Positive Power Supply
These terminal connects to the positive power supply and are the source input of
operational power for the device.
3
6
8
10
LS4
LS6
LS8
LS10
Low-Side Output 4
Low-Side Output 6
Low-Side Output 8
Low-Side Output 10
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.
4, 11, 15,
20, 32
GND
Ground
5
7
9
12
LS5
LS7
LS9
LS11
Low-Side Output 5
Low-Side Output 7
Low-Side Output 9
Low-Side Output 11
13
VDD
Digital Drain Voltage (Power)
These terminals serve as the ground for the source of the low-side output
transistors as well as the logic portion of the device.
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.
This is an external input terminal used to supply power to the SPI circuit.
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33888
3
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TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Name
Formal Name
Definition
14
SO
Serial Output
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low CS terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
16
CS
Chip Select
(Active Low)
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the CS
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
17
SCLK
Serial Clock
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, fSPI, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
18
SI
Serial Input
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
19
ILS
Low-Side Input
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
21
22
30
31
IHS3
IHS2
IHS0
IHS1
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Each high-side input terminal is used to directly control only one designated highside output. These inputs may or may not be activated depending on the configured
state of the internal logic.
23
29
CSNS2-3
CSNS0-1
Current Sense 2-3
Current Sense 0-1
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
25
28
HS3
HS2
High-Side Output 3
High-Side Output 2
Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
26
27
HS1
HS0
High-Side Output 1
High-Side Output 0
Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
33
WAKE
Wake
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
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33888
4
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TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
Formal Name
Definition
34
RST
Reset (Active Low)
This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until VDD is in regulation. This input has an
internal passive pulldown.
35
FSI
Fail-Safe Input
The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
36
WDIN
Watchdog Input
This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
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33888
5
VPWR
HS2
HS2
NC
NC
NC
58
57
56
55
54
53
WAKE
IHS1
IHS0
CSNS0-1
VPWR
64
63
62
61
60
59
RST
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52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
NC
HS0
HS0
HS0
HS0
HS0
HS0
HS0
HS1
HS1
HS1
HS1
HS1
HS1
HS1
NC
NC
NC
VPWR 27
HS3 28
HS3 29
NC 30
NC 31
NC 32
1
2
FS 3
VPWR 4
LS4 5
GND 6
LS5 7
LS6 8
GND 9
LS7 10
LS8 11
GND 12
LS9 13
LS10 14
GND 15
LS11 16
VDD 17
SO 18
CS 19
SCLK 20
SI 21
ILS 22
IHS3 23
IHS2 24
CSNS2-3 25
VPWR 26
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FSI
WDIN
TERMINAL DEFINITIONS FOR PQFP
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
Formal Name
Definition
1
FSI
Fail-Safe Input
The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
2
WDIN
Watchdog Input
This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
3
FS
Fault Status
(Active Low)
This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.
4, 26, 27,
58, 59
VPWR
Positive Power Supply
These terminal connects to the positive power supply and are the source input of
operational power for the device.
5
8
11
14
LS4
LS6
LS8
LS10
Low-Side Output 4
Low-Side Output 6
Low-Side Output 8
Low-Side Output 10
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.
6, 9, 12, 15
GND
Ground
33888
6
These terminals serve as the ground for the source of the low-side output
transistors as well as the logic portion of the device.
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TERMINAL DEFINITIONS FOR PQFP (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
Formal Name
Definition
7
10
13
16
LS5
LS7
LS9
LS11
Low-Side Output 5
Low-Side Output 7
Low-Side Output 9
Low-Side Output 11
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.
17
VDD
Digital Drain Voltage (Power)
18
SO
Serial Output
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low CS terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
19
CS
Chip Select
(Active Low)
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the CS
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
20
SCLK
Serial Clock
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, fSPI, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
21
SI
Serial Input
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
22
ILS
Low-Side Input
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
23
24
61
62
IHS3
IHS2
IHS0
IHS1
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Each high-side input terminal is used to directly control only one designated highside output. These inputs may or may not be activated depending on the configured
state of the internal logic.
25
60
CSNS2-3
CSNS0-1
Current Sense 2-3
Current Sense 0-1
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
28, 29
56, 57
HS3
HS2
High-Side Output 3
High-Side Output 2
Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
30–35,
50–55
NC
Not Connected
This is an external input terminal used to supply power to the SPI circuit.
These terminals are not connected internally.
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TERMINAL DEFINITIONS FOR PQFP (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Name
Formal Name
Definition
36–42
43–49
HS1
HS0
High-Side Output 1
High-Side Output 0
Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
63
WAKE
Wake
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
64
RST
Reset (Active Low)
This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until VDD is in regulation. This input has an
internal passive pulldown.
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33888
8
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
VPWR
Power Supply Voltage
Input Terminal Voltage (Note 1)
WAKE Input Terminal Clamp Current
VIN
-0.3 to 7.0
V
IWICI
2.5
mA
IOUTLS
Continuous per Output Current (Note 2)
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V
-16 to 41
Steady State
mA
Low-Sides 4, 6, 8, 10
500
Low-Sides 5, 7, 9, 11
800
IOUTHS
Continuous per Output Current (Note 3)
A
High-Sides 0, 1
10
High-Sides 2, 3
5.0
mJ
Output Clamp Energy
High-Sides 0, 1 (Note 4)
EHS
450
High-Sides 2, 3 (Note 5)
EHS
120
Low-Sides (Note 6)
ELS
50
Human Body Model (Note 7)
VESD1
±2000
Machine Model (Note 8)
VESD2
±200
V
ESD Voltage
Notes
1. Exceeding voltage limits on SCLK, SI, CS, WDIN, RST, IHS, FSI, or ILS terminals may cause a malfunction or permanent damage to the
device.
2. Continuous low-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.
3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.
4. Active HS0 and HS1 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 40 mH, TJ = 150°C.
5.
Active HS2 and HS3 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 10 mH, TJ = 150°C.
6.
Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, TJ = 150°C.
7.
ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP = 1500 Ω).
8.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
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9
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MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Ambient
TA
-40 to 125
Junction
TJ
-40 to 150
Storage Temperature
TSTG
-55 to 150
Control Die Thermal Resistance (Note 9)
RθCJC
Unit
THERMAL RATINGS
°C
Operating Temperature
°C
°C/W
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PQFP
One Low-Side ON
12.5
Two Low-Side ON
9.3
Three Low-Side ON
7.3
Four Low Side ON
5.9
All Low-Sides ON
3.2
PQFN
One Low-Side ON
8.6
Two Low-Side ON
6.0
Three Low-Side ON
4.6
Four Low Side ON
3.8
All Low-Sides ON
2.0
RθPJC
Power Die Thermal Resistance (Note 9)
°C/W
PQFP
One High-Side 2, 3 ON
0.5
All High-Sides ON
0.15
PQFN
One High-Side 2, 3 ON
0.5
All High-Sides ON
0.1
Thermal Resistance, Junction to Ambient, Natural Convection, Four-Layer
Board (Note 9)
RθJA
°C/W
33
PQFP
37
PQFN
Peak Terminal Reflow Temperature During Solder Mounting (Note 10)
°C
TSOLDER
PQFP
225
PQFN
240
Notes
9.
10.
33888
10
Board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm2 copper area on the bottom layer.
Terminal soldering temperature limit is 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
VPWR
Supply Voltage Range
Fully Operational
6.0
–
27
–
17
25
–
–
20
mA
IPWR(ON)
VPWR Supply Current
TJ > 125°C
TJ ≤ 125°C
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V
VPWR Standby Current (All Outputs OFF, Open Load Detection Disabled,
WAKE = H, RST = H)
mA
IPWR(SBY)
TJ > 125°C
–
4.2
7.0
TJ ≤ 125°C
–
2.9
5.0
Sleep State Supply Current (VPWR < 12.6 V, RST < 0.5 V, WAKE < 0.5 V,
HS[0:3] = 0 V) (Note 11)
µA
IPWR(SS)
TJ = 85°C
–
–
80
TJ = 25°C
–
1.0
25
4.5
5.0
5.5
TJ > 125°C
–
4.2
7.0
TJ ≤ 125°C
–
2.9
5.0
–
–
5.0
VDD
Logic Supply Voltage Range
mA
IDD(ON)
Logic Supply Current
Logic Supply Sleep State Current
IDD(SS)
Sleep State Low-Side Output Leakage Current (per Low-Side Output,
RST = LOW)
ISLK(SS)
V
µA
µA
TJ = 85°C
–
–
3.0
TJ = 25°C
–
–
1.0
Overvoltage Shutdown Threshold
VPWROV
28.5
32
36
V
Overvoltage Shutdown Hysteresis
VPWROV(HYS)
0.2
0.6
1.5
V
Undervoltage High-Side Output Shutdown (Note 12)
VPWRUV
5.0
5.6
6.0
V
Undervoltage Low-Side Output Shutdown
VPWRUV
APNB Suffix Only (Note 12)
3.0
4.0
4.4
PNB and FB Suffixes
5.0
5.6
6.0
0.1
0.3
0.5
Undervoltage High-Side Shutdown Hysteresis
VPWRUV(HYS)
V
V
Notes
11. This parameter is tested at 125°C with a maximum value of 10 µA.
12. SPI/IO and internal logic operational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the level
does not go below VPWRUV.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
–
1/1400
–
Unit
POWER INPUT (continued)
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
CSR[0:1]
–
CSNS0-1/HS0, CSNS0-1/HS1
%
CSR[0:1]_ACC
Current Sense Ratio (CSR[0:1] ) Accuracy
Freescale Semiconductor, Inc...
HS[0:1] Output Current
1.0 A
-35
–
35
2.0 A
-19
–
19
5.0 A
-14
–
14
6.5 A
-12
–
12
10 A
-12
–
12
–
1/880
–
Current Sense Ratio (VPWR = 9.0 V – 16 V, CSNS < 4.5 V)
CSR
–
CSNS2-3/HS2, CSNS2-3/HS3
%
CSR[2:3]_ACC
Current Sense Ratio (CSR[2:3] ) Accuracy
HS[2:3] Output Current
30
-30
–
1.0 A
-19
–
19
3.0 A
-13.5
–
13.5
3.7 A
-12
–
12
5.0 A
-9.0
–
9.0
4.5
6.0
7.0
0.5 A
VSENSE
Current Sense Clamp Voltage
ICNS = 15 mA Generated by the Device
V
HS0 AND HS1 POWER OUTPUTS
Drain-to-Source ON Resistance (IOUT = 5.5 A)
Ω
RDS(ON)
TJ = 25°C
VPWR = 6.0 V
–
–
0.02
VPWR = 9.0 V
–
–
0.01
VPWR = 13 V
–
–
0.01
VPWR = 6.0 V
–
–
0.034
VPWR = 9.0 V
–
–
0.017
VPWR = 13 V
–
–
0.017
–
–
0.02
TJ = 150°C
Reverse Battery Source-to-Drain ON Resistance (IOUT = -5.5 A, TJ = 25°C)
Ω
RDS(ON)REV
VPWR = -12 V
Output Self-Limiting Peak Current
ILIM(PK)
Outputs ON, VOUT = VPWR -2.0 V
Output Self-Limiting Sustain Current
33
49
66
13
25
34
30
–
100
ILIM(SUS)
Outputs ON, VOUT = VPWR -2.0 V
Open Load Detection Current (Note 13)
A
IOLDC
A
µA
Notes
13. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
33888
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
2.0
3.0
4.0
-20
–
–
TSD
160
175
190
°C
TSD(HYS)
10
–
30
°C
HS0 AND HS1 POWER OUTPUTS (continued)
Output Fault Detection Threshold (Note 14)
VOFD(THRES)
Output Programmed OFF
VCL
Output Negative Clamp Voltage
0.5 A < IOUT < 2.0 A, Output OFF
Overtemperature Shutdown (Outputs OFF) (Note 15)
Overtemperature Shutdown Hysteresis (Note 15)
Freescale Semiconductor, Inc...
V
V
HS2 AND HS3 POWER OUTPUTS
Drain-to-Source ON Resistance (IOUT = 4.5 A)
Ω
RDS(ON)
TJ = 25°C
VPWR = 6.0 V
–
–
0.08
VPWR = 9.0 V
–
–
0.04
VPWR = 13 V
–
–
0.04
VPWR = 6.0 V
–
–
0.136
VPWR = 9.0 V
–
–
0.068
VPWR = 13 V
–
–
0.068
–
–
0.08
15
23
35
6.0
10
15
25
–
100
2.0
3.0
4.0
TJ = 150°C
Reverse Battery Source-to-Drain ON Resistance (IOUT = 4.5 A, TJ = 25°C)
Ω
RDS(ON)REV
VPWR = -12 V
ILIM(PK)
Output Self-Limiting Peak Current
Outputs ON, VOUT = VPWR -2.0 V
A
A
ILIM(SUS)
Output Self-Limiting Sustain Current
Outputs ON, VOUT = VPWR -2.0 V
IOLDC
Open Load Detection Current (Note 16)
Output Fault Detection Threshold (Note 17)
VOFD(THRES)
Outputs Programmed OFF
V
VCL
Output Negative Clamp Voltage
Overtemperature Shutdown Hysteresis (Note 18)
V
-20
–
–
TSD
160
170
190
°C
TSD(HYS)
10
–
30
°C
0.5 A < IOUT < 2.0 A, Outputs OFF
Overtemperature Shutdown (Outputs OFF) (Note 18)
µA
Notes
14. Output fault detection threshold with outputs programmed OFF. For the Low-Side Outputs, fault detection thresholds are the same for output
open and battery shorts.
15. Guaranteed by design. Not production tested.
16. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
17. Output fault detection threshold with outputs programmed OFF.
18. Guaranteed by design. Not production tested.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LOW-SIDE POWER OUTPUTS
Drain-to-Source ON Resistance (IOUT = 0.3 A)
Ω
RDS(ON)
TJ = 25°C
VPWR = 4.5 V; VDD = 3.5 V, 33888A Only
–
–
8.0
VPWR = 6.0 V
–
–
1.0
VPWR = 9.0 V
–
–
0.7
VPWR = 13 V
–
–
0.6
VPWR = 4.5 V; VDD = 3.5 V, 33888A Only
–
–
8.0
VPWR = 6.0 V
–
–
1.8
VPWR = 9.0 V
–
–
1.1
VPWR = 13 V
–
–
0.9
Low-Side 4, 6, 8, 10
0.5
0.9
1.5
Low-Side 5, 7, 9, 11
0.8
1.3
2.0
25
50
100
2.0
3.0
4.0
41
53
60
Freescale Semiconductor, Inc...
TJ = 150°C
Output Self-Limiting Current (Outputs Programmed ON, VOUT = 3.0 V)
Output OFF Open Load Detection Current (Note 19)
ILIM
A
µA
IOLDC
Output Programmed OFF, VOUT = 3.0 V
VOFD(THRES)
Output Fault Detection Threshold (Note 20)
Output Programmed OFF
V
VCL
Output Clamp Voltage
2.0 mA < IOUT < 200 mA, Outputs OFF
V
Low-Side Body Diode Voltage (I = -300 mA, TJ = 125°C)
VBD
0.5
0.7
0.9
V
Overtemperature Shutdown (Outputs OFF) (Note 21)
TLIM
160
170
190
°C
TLIM(HYS)
10
20
30
°C
Overtemperature Shutdown Hysteresis (Note 21)
Notes
19. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
20. Output fault detection threshold with outputs programmed OFF. For the low-side outputs, fault detection thresholds are the same for output
open and battery shorts.
21. Guaranteed by design. Not production tested.
33888
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Logic High Voltage (Note 22)
VIH
0.7 VDD
–
–
V
Input Logic Low Voltage (Note 22)
VIL
–
–
1.0
V
VIN(HYS)
100
350
750
mV
Input Logic Pulldown Current (SI, SCLK, IHS[0:3], ILS, WDIN)
IDWN
5.0
–
20
µA
Input Logic Pulldown Resistor (WAKE, RST)
RDWN
100
200
400
kΩ
Input Logic Pullup Current (CS, VIN = 0.7 VDD) (Note 24)
IUPC
5.0
–
20
µA
Input Logic Pullup Current (FSI, VIN = 3.5 V)
IUPF
5.0
–
20
µA
Wake Input Clamp Voltage (IWICI < 2.5 mA) (Note 25)
VWIC
7.0
–
14
V
Wake Input Forward Voltage (IWICI = -2.5 mA)
VWIF
-2.0
–
-0.3
V
SO High-State Output Voltage (IOH = 1.0 mA)
VSOH
0.8 VDD
–
–
V
FS, SO Low-State Output Voltage (IOL = -1.6 mA)
VSOL
–
0.2
0.4
V
SO Tri-State Leakage Current (CS ≥ 3.5 V)
ISOLK
-5.0
0
5.0
µA
Input Capacitance (Note 26)
CIN
–
4.0
12
pF
SO, FS Tri-State Capacitance (Note 23)
CSO
–
–
20
pF
CONTROL INTERFACE
Freescale Semiconductor, Inc...
Input Logic Voltage Hysteresis (SI, CS, SCLK, IHS[0:3], ILS) (Note 23)
Notes
22. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN input signals. The WAKE,
FSI, and RST signals are derived from an internal supply.
23. Parameter is guaranteed by design but is not production tested.
24. CS is pulled up to VDD.
25.
The current must be limited by a series resistor when using voltages higher than the WICV.
26.
Input capacitance of SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN. This parameter is guaranteed by process monitoring but is not
production tested.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
High-Side Output Rising Fast Slew Rate (Note 27)
6.0 V < VPWR < 9.0 V
0.03
–
0.6
9.0 V < VPWR < 16 V
0.05
0.5
0.8
16 V < VPWR < 27 V
0.1
–
1.1
6.0 V < VPWR < 9.0 V
0.01
–
0.14
9.0 V < VPWR < 16 V
0.01
0.08
0.18
16 V < VPWR < 27 V
0.01
–
0.2
6.0 V < VPWR < 9.0 V
0.2
–
1.0
9.0 V < VPWR < 16 V
0.3
0.8
1.5
16 V < VPWR < 27 V
0.5
–
2.2
6.0 V < VPWR < 9.0 V
0.05
–
0.3
9.0 V < VPWR < 16 V
0.08
0.15
0.4
16 V < VPWR < 27 V
0.08
–
0.5
High-Side Output Rising Slow Slew Rate (Note 28)
Freescale Semiconductor, Inc...
V/µs
SRR_FAST
High-Side Output Falling Fast Slew Rate (Note 27)
High-Side Output Falling Slow Slew Rate (Note 28)
V/µs
SRR_SLOW
V/µs
SRF_FAST
V/µs
SRF_SLOW
High-Side Output Turn ON Delay Time (Note 29)
t DLY(ON)
5.0
30
150
µs
High-Side Output Turn OFF Delay Time (Note 30)
t DLY(OFF)
5.0
80
150
µs
Low-Side Output Falling Slew Rate (Note 31)
SRF
0.5
3.0
10
V/µs
Low-Side Output Rising Slew Rate (Note 31)
SRR
1.0
6.0
20
V/µs
Low-Side Output Turn ON Delay Time (Note 32)
t DLY(ON)
0.5
2.0
10
µs
Low-Side Output Turn OFF Delay Time (Note 33)
t DLY(OFF)
0.5
4.0
10
µs
t DLY(FS)
70
150
250
µs
t WDTO
340
584
770
ms
Low-Side Output Fault Delay Timer (Note 34)
Watchdog Timeout (Note 35)
Notes
27. High-side output rise and fall fast slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.0 V (see Figure 2,
page 18). These parameters are guaranteed by process monitoring.
28. High-side output rise and fall slow slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.0 V (see
Figure 2, page 18). These parameters are guaranteed by process monitoring.
29. High-side output turn-ON delay time measured from 50% of the rising IHS to 0.5 V of output OFF with RL = 27 Ω resistive load (see Figure 2,
page 18).
30. High-side output turn-OFF delay time measured from 50% of the falling IHS to VPWR -2.0 V of the output OFF with RL = 27 Ω resistive load
(see Figure 2, page 18).
31. Low-side output rise and fall slew rates measured across a 5.0 Ω resistive load at low-side output = 10% to 90% (see Figure 3, page 18).
32. Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of VOUT with RL = 27 Ω resistive load (see Figure 3,
page 18).
33. Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of VOUT with RL = 27 Ω resistive load (see Figure 3,
page 18). These parameters are guaranteed by process monitoring.
34. Propagation time of Short Fault Disable Report Delay measured from rising edge of CS to output disabled, low-side = 5.0 V, and device
configured for low-side output overcurrent latchoff using CLOCCR.
35. Watchdog timeout delay is measured from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs
driven OFF and the FSI floating. The accuracy of t WDTO is maintained for all configured watchdog timeouts.
33888
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Peak Current Limit Timer (Note 36)
t PCT
40
70
100
ms
Direct Input Switching Frequency (Note 37)
f PWM
–
125
–
Hz
POWER OUTPUT TIMING (continued)
SPI INTERFACE TIMING (Note 38)
Freescale Semiconductor, Inc...
Recommended Frequency of SPI Operation
f SPI
MHz
Normal Mode
–
–
3.0
Extended Mode: VDD = 3.4 V; VPWR = 4.5 V, APNB Suffix Only
–
–
2.1
t WRST
–
50
167
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 40)
t CS
–
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 40)
t ENBL
–
–
5.0
µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 40)
t LEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time) (Note 40)
t WSCLKh
–
–
167
ns
Required Low State Duration of SCLK (Required Setup Time) (Note 40)
t WSCLKl
–
–
167
ns
t LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (Note 40)
t SI(SU)
–
25
83
ns
Falling Edge of SCLK to SI (Required Hold Time) (Note 40)
t SI(HOLD)
–
25
83
ns
Required Low State Duration for RST (Note 39)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 40)
t RSO
SO Rise Time
CL = 200 pF
ns
–
25
50
–
25
50
t FSO
SO Fall Time
CL = 200 pF
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 41)
t RSI
–
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 41)
t FSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 42)
t SO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High Impedance (Note 43)
t SO(DIS)
–
65
145
ns
–
65
105
Time from Rising Edge of SCLK to SO Data Valid (Note 44)
t VALID
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
ns
Notes
36. t PCT measured from the rising edge of CS to 90% of ILIMPKHS[x,x] when the peak current limit is enabled.
37.
38.
39.
40.
41.
42.
43.
44.
This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall
times, and the maximum allowable junction temperature.
Symmetrical 50% duty cycle SCLK clock period of 333 ns.
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU.
Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ pullup on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ pullup on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Timing Diagrams
Direct
input
Direct
Inputor
or spi
SPI bit
Bit
V
PWR
VPWR
- 0.5V
VVPWR
V
PWR -0.5
SRF_SLOW
SRf_slow
SRR_SLOW
SRr_slow
VPWR
-3.0- 3V
V
VPWR
SR
F_FAST
SRf_fast
Freescale Semiconductor, Inc...
SRR_FAST
SRr_fast
0.5
V
0.5V
Tdly(off)
t DLY(OFF)
t DLY(ON)
Tdly
(on)
Figure 2. Output Slew Rates and Time Delays, High Side
Direct
input
bit
Direct
Inputor
orSPI
SPI Bit
V
PWR
VPWR
90%
90%
SRf
SR
F
SRr
SRR
10%
10%
t DLY(ON)
Tdly(on)
tTdly(off)
DLY(OFF)
Figure 3. Output Slew Rates and Time Delays, Low Side
33888
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Freescale Semiconductor, Inc...
This 33888 is a single-package combination of a power die
with four discrete high-side MOSFETs and an integrated IC
control die consisting of eight low-side drivers with appropriate
control, protection, and diagnostic features. The high-side
drivers are useful for both internal and external vehicle lighting
applications as well as capable of driving inductive solenoid
loads. The low-side drivers are capable of controlling lowcurrent on/off type inductive loads, such as relays and
solenoids as well as LED indicators and small lamps (see
simplified application diagram, page 2). The device is useful in
body control, instrumentation, and other high-power switching
applications and systems.
The 33888 is available in two packages: a power-enhanced
12 x 12 nonleaded Power QFN package with exposed tabs and
a 64-lead Power QFP plastic package. Both packages are
intended to be soldered directly onto the printed circuit board.
The 33888 differs from the 33888A as explained in Table 1,
page 2.
FUNCTIONAL DESCRIPTION
SPI Interface and Protocol Description
Serial Output (SO)
The SPI interface has full duplex, three-wire synchronous
data transfer and has four I/O lines associated with it: Serial
Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip
Select (CS).
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data
report the status of the outputs as well as provide the capability
to reflect the state of the direct inputs. The SO terminal changes
states on the rising edge of SCLK and reads out on the falling
edge of SCLK. When an output is ON or OFF and not faulted,
the corresponding SO bit, OD11:OD0, is a logic [0]. If the output
is faulted, the corresponding SO state is a logic [1]. SO
OD14:OD12 reflect the state of six various inputs (three at a
time) depending upon the reported state of the previously
written watchdog bit OD15.
The SI/SO terminals of the 33888 follow a first-in first-out
(D15/D0) protocol with both input and output words transferring
the most significant bit first. All inputs are compatible with 5.0 V
CMOS logic levels. During SPI output control, a logic [0] in a
message word will result in the designated output being turned
off. Similarly, a logic [1] will turn on a corresponding output.
The SPI lines perform the following functions:
Serial Clock (SCLK)
Chip Select (CS)
The SCLK terminal clocks the internal shift registers of the
33888. The serial input (SI) terminal accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output terminal (SO) shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is important
that the SCLK terminal be in a logic [0] state whenever the chip
select (CS) makes any transition. For this reason, it is
recommended that the SCLK terminal be kept in a logic [0] state
as long as the device is not accessed (CS in logic [1] state).
SCLK has an active internal pulldown, IDWN. When CS is
logic [1], signals at the SCLK and SI terminals are ignored and
SO is tri-stated (high impedance). (See Figures 4 and 5 on
page 20.)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the 33888 is capable of transferring information to and receiving
information from the MCU. The 33888 latches in data from the
input shift registers to the addressed registers on the rising
edge of CS. The 33888 transfers status information from the
power outputs to the shift registers on the falling edge of CS.
The output driver on the SO terminal is enabled when CS is
logic [0]. CS is only transitioned from a logic [1] state to a
logic [0] state when SCLK is a logic [0]. CS has an active
internal pullup, IUP.
Serial Interface (SI)
The 33888 is capable of communicating directly with the
MCU via the 16-bit SPI protocol as described in the next
section.
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The 12 outputs of the 33888 are configured and controlled
using the 3-bit addressing scheme and the 12 assigned data
bits designed into the 33888. SI has an active internal pulldown,
IDWN.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33888
19
Freescale Semiconductor, Inc.
CSB
CS
SCLK
SI
Freescale Semiconductor, Inc...
SO
D15
D14
OD15
D13
OD14 OD13
D12
D11
D10
OD12 OD11 OD10
D9
OD9
D8
OD8
D7
D6
OD7
D5
OD6
D4
OD5
OD4
D3
OD3
D2
D1
OD2
D0
OD1
OD0
Notes 1. RST is in a logic [1] state during the above operation.
2. D15:D0 relate to the most recent ordered entry of program data into the 33888.
3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.
Figure 4. Single 16-Bit Word SPI Communication
CS
CSB
SCLK
SI
SO
D15
D14
OD15
D13
OD14 OD13
D2
OD2
D1
OD1
D0
OD0
D15*
D15
D14*
D14
D13*
D13
D2*
D1*
D2
D1
D0*
D0
Notes 1. RST is a logic [1] state during the above operation.
2. D15:D0 relate to the most recent ordered entry of program data into the 33888.
3. D15*:D0* relate to the first 16 bits of ordered entry data out of the 33888.
4. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.
Figure 5. Multiple 16-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 16-bit messages.
A message is transmitted by the MCU starting with the MSB,
D15, and ending with the LSB, D0 (refer to Table 2, page 21).
Each incoming command message on the SI terminal can be
interpreted using the following bit assignments: the first twelve
LSBs, D11:D0, control each of the twelve outputs; the next
three bits, D14:D12, determine the command mode; and the
MSB, D15, is the watchdog bit.
33888
20
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to latch
in a message that is not 16 bits will be ignored.
The 33888 has six registers that are used to configure the
device and control the state of the four high-side and eight
low-side outputs (Table 3, page 21). The registers are
addressed via D14:D12 of the incoming SPI word (Table 2,
page 21).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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.
Table 2. SI Message Bit Assignment (continued)
Table 2. SI Message Bit Assignment
Bit Sig
SI Msg Bit
MSB
D15
Message Bit Description
SI Msg Bit
D5
Used to configure Low-Side Output LS5
(Watchdog timeout MSB during WDCSCR
configuration).
D4
Used to configure Low-Side Output LS4
(Watchdog timeout LSB during WDCSCR
configuration).
Watchdog in: toggled to satisfy watchdog
requirements.
D14:12
Freescale Semiconductor, Inc...
Bit Sig
Message Bit Description
Register address bits.
D11
Used to configure Low-Side Output LS11.
D10
Used to configure Low-Side Output LS10.
D3
Used to configure High-Side Output HS3.
D9
Used to configure Low-Side Output LS9.
D2
Used to configure High-Side Output HS2.
D8
Used to configure Low-Side Output LS8.
D1
Used to configure High-Side Output HS1.
D7
Used to configure Low-Side Output LS7.
D0
Used to configure High-Side Output HS0.
D6
Used to configure Low-Side Output LS6.
LSB
Table 3. Serial Input Address and Configuration Bit Map
WD
Address
Low-Side
High-Side
SI
Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SOCR
x
0
0
0
LS11
LS10
LS9
LS8
LS7
LS6
LS5
LS4
HS3
HS2
HS1
HS0
DICR
x
1
0
0
PWB11 PWB10 PWB9
PWB8
PWB7
PWB6
PWB5
PWB4
PWB3
PWB2
PWB1
PWB0
LFCR
x
0
1
0
A/OB11 A/OB10 A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0
WDCSCR
x
1
1
0
NA
NA
NA
NA
NA
NA
WDH
WDL
CS3
CS2
CS1
CS0
OLCR
x
0
0
1
OL11
OL10
OL9
OL8
OL7
OL6
OL5
OL4
OLB3
OLB2
OLB1
OLB0
CLOCCR
x
1
0
1
OC11
OC10
OC9
OC8
OC7
OC6
OC5
OC4
ILIM3
ILIM2
ILIM1
ILIM0
NOT
USED
x
0
1
1
–
–
–
–
–
–
–
–
–
–
–
–
TEST
x
1
1
1
–
–
–
–
–
–
–
–
ILIMPK
WD
ILIM
OT
x=Don’t care.
NA=Not applicable.
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address 000—SPI Output Control Register (SOCR)
The SOCR register allows the MCU to control the outputs via
the SPI. Incoming message bits D3:D0 reflect the desired
states of high-side outputs HS3:HS0. Message bits D11:D4
reflect the desired state of low-side outputs LS11:LS4,
respectively.
Address 100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable direct input
control of the outputs. For the outputs, a logic [0] on bits D11:D0
will enable the corresponding output for direct control. A
logic [1] on a D11:D0 bit will disable the output from direct
control.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Address 010—Logic Function Control Register (LFCR)
The LFCR register is used by the MCU to configure the
relationship between SOCR bits D11:D0 and the direct inputs
IHS[0:3] and ILS. While addressing this register (if the direct
inputs were enabled for direct control with the DICR), a logic [1]
on any or all of the D3:D0 bits will result in a Boolean AND of
the IHS[0:3] terminal(s) with its (their) corresponding D3:D0
message bit(s) when addressing the SOCR. A logic [1] on any
or all of the D11:D4 bits will result in a Boolean AND of the ILS
and the corresponding D11:D4 message bits when addressing
the SOCR. Similarly, a logic [0] on the D3:D0 bits will result in
a Boolean OR of the IHS[0:3] terminal(s) with their
corresponding message bits when addressing the SOCR
register, and the ILS will be Boolean ORed with message bits
D11:D4 when addressing the SOCR register (if ILS is enabled).
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21
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Address 110—Watchdog and Current Sense Configuration
Register (WDCSCR)
The WDCSCR register is used by the MCU to configure the
watchdog timeout and the CSNS0-1 and CSNS2-3 terminals.
The watchdog timeout is configured using bits D4 and D5. The
state of D4 and D5 determine the divided value of the WDTO.
For example, if D5 and D4 are logic [0] and logic [0],
respectively, then the WDTO will be in the default state as
specified in Table 3, page 21. A D5 and a D4 of logic [0] and
logic [1] will result in a watchdog timeout of WDTO ÷ 2.
Similarly, a D5 and a D4 of logic [1] and logic [0] result in a
watchdog timeout of WDTO ÷ 4, and a D5 and a D4 of logic [1]
and logic [1] result in a watchdog timeout of WDTO ÷ 8. Note
that when D5 and D4 bits are programmed for the desired
watchdog timeout period, the WD bit (D15) should be toggled
as well to ensure that the new timeout period is programmed at
the beginning of a new count sequence.
CSNS0-1 is the current sense output for the HS0 and HS1
outputs. Similarly, the CSNS2-3 terminal is the current sense
output for the HS2 and HS3 outputs. In this mode, a logic [1] on
any or all of the message bits that control the high-side outputs
will result in the sensed current from the corresponding output
being directed out of the appropriate CSNS output. For
example, if D1 and D0 are both logic [1], then the sensed
current from HS0 and HS1 will be summed into the CSNS0-1.
If D2 is logic [1] and D3 is logic [0], then only the sensed current
from HS2 will be directed out of CSNS2-3.
Address 001—Open Load Configuration Register (OLCR)
The OLCR register allows the MCU to configure each of the
outputs for open load fault detection. While in this mode, a
logic [1] on any of the D3:D0 message bits will disable the
corresponding outputs’ circuitry that allows the device to detect
open load faults while the output is OFF. For the low-side
drivers, a logic [1] on any of the D11:D4 bits will enable the
open load detection circuitry. This feature allows the MCU to
minimize load current in some applications and may be useful
to diagnose output shorts to battery (for HS).
Address 101—Current Limit Overcurrent Configuration
Register (CLOCCR)
The CLOCCR register allows the MCU to individually
override the peak current limit levels for each of the high-side
outputs. A logic [1] on any or all of the D3:D0 bit(s) results in the
corresponding HS3:HS0 output terminals to current limit at the
sustain current limit level. This register also allows the MCU to
enable or disable the overcurrent shutdown of the low-side
output terminals. A logic [1] on any or all of the D11:D4
message bit(s) will result in the corresponding LS11:LS4
terminals latching off if the current exceeds ILIM after a timeout
of t DLY(FS).
Address 011—Not Used
Not currently used.
Address 111—TEST
The TEST register is reserved for test and is not accessible
via SPI during normal operation.
Serial Output Communication (Devise Status
Return Data)
When the CS terminal is pulled low, the output status register
for each output is loaded into the output register and the fault
data is clocked out MSB (OD15) first as the new message data
is clocked into the SI terminal.
OD15 reflects the state of the watchdog bit (D15) that was
addressed during the prior SOCR communication (refer to
Table 4, page 23). If bit OD15 is logic [0], then the three MSBs
OD14:OD12 will reflect the logic states of the IHS0, IHS1, and
FSI terminals, respectively. If bit OD15 is logic [1], then the
same three MSB bits will reflect the logic states of the IHS2,
IHS3, and WAKE terminals. The next twelve bits clocked out of
SO following a low transition of the CS terminal (OD11:OD0)
will reflect the state of each output, with a logic [1] in any of the
33888
22
bits indicating that the respective output experienced a fault
condition prior to the CS transition. Any bits clocked out of the
SO terminal after the first 16 will be representative of the initial
message bits that were clocked into the SI terminal since the CS
terminal first transitioned to a logic [0]. This feature is useful for
daisy chaining devices as well as message verification.
Following a CS transition logic [0] to logic [1], the device
determines if the message was of a valid length (a valid
message length is one that is a multiple of 16 bits) and if so,
latches the data into the appropriate registers. At this time, the
SO terminal is tri-stated and the fault status register is now able
to accept new fault status information.
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Table 4. Serial Output Bit Assignment (continued)
Table 4. Serial Output Bit Assignment
Message Bit Description
OD9
Reports the absence or presence of a fault on LS9.
OD8
Reports the absence or presence of a fault on LS8.
OD7
Reports the absence or presence of a fault on LS7.
OD6
Reports the absence or presence of a fault on LS6.
If OD15 is logic [0], then this bit will reflect the state
of the direct input IHS1. If OD15 is logic [1], then this
bit will reflect the state of IHS3.
OD5
Reports the absence or presence of a fault on LS5.
OD4
Reports the absence or presence of a fault on LS4.
If OD15 is logic [0], then this bit will reflect the state
of the input FSI. If OD15 is logic [1], then this bit will
reflect the state of the input WAKE.
OD3
Reports the absence or presence of a fault on HS3.
OD2
Reports the absence or presence of a fault on HS2.
OD1
Reports the absence or presence of a fault on HS1.
OD0
Reports the absence or presence of a fault on HS0.
SO
Msg Bit
MSB
OD15
Reflects the state of the Watchdog bit from the
previously clocked-in message.
OD14
If OD15 is logic [0], then this bit will reflect the state
of the direct input IHS0. If OD15 is logic [1], then this
bit will reflect the state of IHS2.
OD13
OD12
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SO
Msg Bit
Bit Sig
Message Bit Description
OD11
Reports the absence or presence of a fault on LS11.
OD10
Reports the absence or presence of a fault on LS10.
Bit Sig
LSB
MODES OF OPERATION
Watchdog and Fail-Safe Operation
The watchdog is enabled and a timeout is started when the
WAKE or RST transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series limiting
resistance that limits the internal clamp current. The timeout is
a multiple of an internal oscillator. As long as the WDIN terminal
or the WD bit (D15) of an incoming SPI message is toggled
within the minimum watchdog timeout, WDTO (or a divided
value configured during a WDCSCR message), then the device
will operate normally. If the watchdog timeout occurs before the
WD bit or the WDIN terminal is toggled, then the device will
revert to a Fail-Safe mode until the device is reinitialized (if the
FSI terminal is left disconnected).
During Fail-Safe mode, all outputs will be OFF except for
HS0 and HS2, which will be driven ON regardless of the state
of the various direct inputs and modes (Table 5). The device
can be brought out of the Fail-Safe mode by transitioning the
WAKE and RST terminals from logic [1] to logic [0]. In the event
the WAKE terminal was not transitioned to a logic [1] during
normal operation and the watchdog times out, then the device
can be brought out of fail-safe by bringing the RST to a logic [0].
If the FSI terminal is tied to GND, then the watchdog, and
therefore fail-safe operation, will be disabled.
Table 5. Fail-Safe Operation and Transitions
to Other 33888 Modes
WAKE RST WDTO HS0 HS2
LS[4:11],
HS[1,3]
Comments
0
0
x
OFF OFF
OFF
Device in Sleep mode.
1
0
NO
OFF OFF
OFF
All outputs are OFF.
When RST transitions
to logic [1], device is in
default.
1
0
YES
ON
ON
OFF
Fail-Safe mode.
Device reset into
Default mode by
transitioning WAKE to
logic [0].
0
1
NO
S
S
S
0
1
YES
ON
ON
OFF
1
1
NO
S
S
S
1
1
YES
ON
ON
OFF
Device in Normal
operating mode.
Fail-Safe mode.
Device reset into
Default mode by
transitioning RST to
logic [0].
Device in Normal
operating mode.
Fail-Safe mode.
Device reset into
Default mode by
transitioning RST and
WAKE to logic [0].
Assumptions: Normal operating voltage and junction temperatures,
FSI terminal floating.
x=Don’t care.
S=State determined by SPI and/or direct input configurations.
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23
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Default Mode
Overtemperature Fault
The default mode describes the state of the device after first
applying VPWR voltage or a reset transition from logic [0] to
logic [1] prior to SPI communication. In the default mode, all
outputs will be off (assuming that the direct inputs ILS and
IHS[0:3] and the WAKE terminal are at logic [0]). All of the
specific terminal functions will operate as though all of the
addressable configuration register bits were set to logic [0]. This
means, for example, that all of the low-side outputs will be
controllable by the ILS terminal, and that all high-side outputs
will be controllable via their respective IHS terminals. During the
default mode, all high-side drivers will default with open load
detection enabled. All low-side drivers will default with open
load detection disabled. This mode allows limited control of the
33888 with the direct inputs in the absence of an SPI.
The 33888 incorporates overtemperature detection and
shutdown circuitry into each individual output structure.
Overtemperature detection occurs when an output is in the ON
state. When an output is shut down due to an overtemperature
condition, no other output is affected. The output experiencing
the fault is shut down to protect itself from damage. A fault bit is
loaded into the status register if the overtemperature condition
is removed, and the fault bit is cleared upon the rising edge of
CS.
Returning the device to the default state after a period of
normal operation, followed by the removal of the VPWR voltage,
requires that the RST input be held at a logic [0] state until VPWR
falls to a level below 2.0 V. If the RST and VDD input levels are
normal, then failure to allow VPWR to fall below 2.0 V will result
in an internal bias circuit clamping the VPWR terminal to
approximately 3.5 V. Once VPWR falls below 2.0 V, the RST can
be returned to 5.0 V without re-enabling the bias circuit.
Fault Logic Requirements
The 33888 indicates all of the following faults as they occur:
•
•
•
•
Overtemperature Fault
Overvoltage Fault
Open Load Fault
Overcurrent Fault
With the exception of the overvoltage, these faults are output
specific. The overvoltage fault is a global fault. The overcurrent
fault is only reported for the low-side outputs.
The 33888 low-side outputs incorporate an internal fault
filter, t DLY(FS). The fault timer filters noise and switching
transients for overcurrent faults when the output is ON and
open load faults when the output is OFF. All faults are latched
and indicated by a logic [1] for each output in the 33888 status
word (Table 4, page 23). If the fault is removed, the status bit for
the faulted output will be cleared by a rising edge on CS.
The FS terminal is driven to a logic [0] when a fault exists on
any of the outputs. FS provides real time monitoring of the
overvoltage fault. For the high-side outputs, FS provides real
time monitoring of the open load and overtemperature. For the
low-side outputs, the FS is latched to a logic [0] for open load,
overtemperature, and overcurrent faults. The latch is cleared by
toggling the state of the faulted output or by bringing RST low.
33888
24
For the low-side outputs, the faulted output is latched OFF
during an overtemperature condition. If the temperature falls
below the recovery level, TLIM(HYS), then the output can be
turned back ON only after the output has first been commanded
OFF either through the SPI or the ILS, depending on the logic
configuration.
For the high-side output(s), an overtemperature condition will
result in the output(s) turning OFF until the temperature falls
below the TLIM(HYS). This cycle will continue indefinitely until
action is taken by the MCU to shut the output(s) OFF.
Overvoltage Fault
The 33888 shuts down all outputs during an overvoltage
condition on the VPWR terminal. The outputs remain in the OFF
state until the overvoltage condition is removed. Fault status for
all outputs is latched into the status register. Following an
overvoltage condition, the next write cycle sent by the SO
terminal of the 33888 is logic [1] on OD11:OD0, indicating all
outputs have shut down. If the overvoltage condition is
removed, the status register can be cleared by a rising edge on
CS.
Open Load Fault
The 33888 incorporates open load detection circuitry on
every output. A high-side or low-side output open load fault is
detected and reported as a fault condition when the
corresponding output is disabled (OFF) if it was configured for
open load detection by setting the appropriate bit to logic [0]
(HS3:HS0) or logic [1] (LS11:LS4) in the OLFCR register
(Figure 6, page 25).
The high-side open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn off the output. If the open load fault is removed
or if the faulted output is commanded ON, the status register
can be cleared by a rising edge on CS. Note that the device
default state will enable the high-side open load detection and
disable the low-side open load detection circuits, respectively.
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VPWR
33888
RL
LOW = Logic 0
+
–
VTHRES
MOSFET
VPWR
RL
OUT
OUTPUT
50 mA
VOFD(THRES)LS
2.0 V–4.0 V
Freescale Semiconductor, Inc...
Figure 6. Low-Side Output OFF Open Load Detection
Overcurrent Fault Requirements: Low-Side Output
An overcurrent condition is defined as any current value
greater than ILIM (500 mA minimum value for LS5, LS7, LS9,
LS11, and 800 mA minimum value for LS4, LS6, LS8, LS10).
The status of the corresponding bit in the CLOCCR register
determines whether a specific output shuts down or continues
to operate in an analog current limited mode until either the
overcurrent condition is removed or the thermal shutdown limit
is reached (Figure 7, page 26). If the overcurrent shutdown
mode is disabled, the fault reporting is disabled as well.
For the low-side output of interest, if a D11:D4 bit was set to
a logic [1] in the OLCR register, the overcurrent protection
shutdown circuitry will be enabled for that output. When a lowside output is commanded ON either from the SPI or the ILS
terminal, the drain of the low-side driver will be monitored for a
voltage greater than the fault detection threshold (3.0 V typical).
If the drain voltage exceeds this threshold, a timer will start and
the output will be turned off and a fault latched in the status
register after the timeout expires. The faulted output can be
retried only by commanding the output OFF and back ON either
through the SPI or the ILS terminal, depending on the logic
configuration. If the fault is gone, the retried output will return to
normal operation and the status register can be cleared on a
rising edge of CS. If the fault remains, the retried output will
latch off after the fault timer expires and the fault bit will remain
set in the status register.
For the low-side output of interest, if a D11:D4 bit was set to
a logic [0] in the OLCR register, the output experiencing an
overcurrent condition is not disabled until an overtemperature
fault threshold has been reached. The specific output goes into
an analog current limit mode of operation, ILIM. The 33888 uses
overtemperature shutdown to protect all outputs in this mode of
operation. If the overcurrent condition is removed before the
output has reached its overtemperature limit, the output will
function as if no fault has occurred.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Note that each pair of low-side drivers, LS4:LS5, LS6:LS7,
LS8:LS9, and LS10:LS11, consists of a 500 mA and a 800 mA
output. Each pair of outputs shares ground bondwires. The
bondwires are not rated to handle both outputs in current limit
mode simultaneously.
Overcurrent Fault Requirements: High-Side Output
For the high-side output of interest, the output current is
limited to one of four levels depending on the type of high-side
output, the amount of time that has elapsed since the output
was switched on, and the state of the CLOCCR register.
Assuming that bits D3:D0 of the CLOCCR register are at
logic [0], the current limit levels of the outputs will be initially at
their peak levels as specified by the ILIM(PK)HS[0:3]. After the
high-side output is switched on, the peak current timer starts.
After a period of time t PCT, the current limit level changes to the
sustain levels ILIMSUSHS[x,x].
For the high-side output of interest, if a D3:D0 bit of the
CLOCCR is at logic [1], then the assigned output will only
current limit at the sustain level specified by ILIMSUSHS[x,x].
Current is limited until the overtemperature circuitry shuts
OFF the device. The device turns ON automatically when the
temperature fails below the TLIM(HYS). This cycle continues
indefinitely until action is taken by the master to shut the
output(s) OFF.
Reverse Battery Requirements
The low-side and high-side outputs survive the application of
reverse battery as low as -16 V.
Ground Disconnect Protection
In the event that the 33888 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
outputs, regardless of the state of the output at the time of
disconnection.
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25
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VPWR
33888
HIGH = Fault
MOSFET ON
RL
OUT
+
Digital
–
+
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Analog
VTHRES
–
VREF
VOFD(THRES)LS
2.0 V–4.0 V
Figure 7. Low-Side Short Circuit Detection and Analog Current Limit
Undervoltage Shutdown Requirements
Output Voltage Clamping
All outputs turn off at some battery voltage below 6.0 V; For
the A version, the low side shutdown at a lower value, VPWRUV.
however, as long as the level stays above 5.0 V, the internal
logic states within the device are designed to be sustained. This
ensures that when the battery level then rises above 6.0 V, the
device will return to the state that it was in prior to the excursion
between 5.0 V and 6.0 V (assuming that there was no SPI
communication or direct input changes during the event). If the
battery voltage falls to a level below 5.0 V, then the internal
logic is reinitialized and the device is then in the default state
upon the return of levels in excess of 6.0 V.
Each output has an internal clamp to provide protection and
dissipate the energy stored in inductive loads. Each clamp
independently limits the drain-to-source voltage to the range
specified in the Power Outputs section of the STATIC
ELECTRICAL CHARACTERISTICS table beginning on
page 12. Also see Figure 8.
Drain-Source
Clamp Voltage
(VCL = 53 V)
Drain Voltage
Drain Current
(ID = 0.5 A)
Clamp Energy
(EJ = IA x VCL x t)
Drain-Source
ON Voltage
(VDS(ON))
Current
Area (IA)
VPWR
Time
GND
Figure 8. Low-Side Output Voltage Clamping
33888
26
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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PACKAGE INFORMATION
Soldering Information
The maximum peak temperature during the soldering
process should not exceed 230°C. The time at maximum
temperature should range from 10 seconds to 40 seconds
maximum.
The 33888 is packaged in a surface mount power package
intended to be soldered directly onto the printed circuit board.
The device was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
• Convection: 225°C +5.0°C/-0°C
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR)/Convection: 225°C +5.0°C/-0°C
Freescale Semiconductor, Inc...
APPLICATIONS
Typical Application
Figure 9 shows a typical application for the 33888.
VPWR
+5.0 V
+5.0 V
VDD
33888
10 kΩ
4
4
MCU
A/D
A/D
RC2
8 x Relay or LED
FS
VDD
VPWR
IHS0:IHS3
ILS
RST
8 x 0.5 Ω
SPI
WDIN
CSNS2-3
CSNS0-1
40 mΩ
FSI
Loads
40 mΩ
10 mΩ
GND
10 mΩ
65 W
21 W 5.0 W
21 W 5.0 W
65 W
RC1
Figure 9. 33888 Typical Application Diagram
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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27
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
PNB SUFFIX
APNB SUFFIX
36-TERMINAL PQFN
NONLEADED PACKAGE
CASE 1438-06
ISSUE E
(Top View)
12
A
14
Freescale Semiconductor, Inc...
M
0.1 C
1
16
36
PIN 1
INDEX AREA
12
23
29
25
28
M
PIN NUMBER
REFERENCE ONLY
0.1 C
2X
B
0.1 C
2.2 2.20
2.0 1.95
0.05 C
4
DETAIL G
0.05
0.00
10X
7.3
6.9
0.1 A B C
1.60
1.35
30X
2X 4.05
6
1
13X
0.8
C
0.90
0.65
0.4±0.2
5
0.1 A B C
X0.5±0.2
2.875
0.6
3
3.85
3.45
0.1 A B C
15
1.25
6X
1.00
29
1.45
1.05
4.45
4.05
0.1 A B C
23
1.625
24
2X
2.8
2.3
(0.25)
28
27
26
2X
0.2
0.0
4X
2.0
1.5
3.75
8.70
8.30
0.1 A B C
2.2
1.8
0.1 M
C A B
0.05
C
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR
THIS PACKAGE IS: HF-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND
CORNER LEADS.
5. METAL PADS CONNECTED TO THE GND.
6. MINIMUM METAL GAP SHOULD BE 0.25MM.
2X
(2X 0.5)
(2X 0.75)
0.5
(2X 0.75)
(0.3)
25
4X
(2X 1.25)
(0.05)
SEATING PLANE
16
0.8
1
C A B
M
14
2 PLACES
7X
M
0.05
4X
36
6
0.62
0.48
0.1
0.4
1.20
10X
0.95
C
DETAIL G
M
2.95
2.55
0.1 M C A B
2X
0.05
M
C
11.7
11.3
0.1 A B C
VIEW M-M
(Bottom View)
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28
CASE 1438-06
ISSUE E
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
FB SUFFIX
64-TERMINAL PQFP
PLASTIC PACKAGE
CASE 1315-03
ISSUE B
4
E1
h
PIN ONE
ID
A
6
52
58X
2X
64
53
E2
h
D4
1
D3
Freescale Semiconductor, Inc...
e
E3
D1 D2
4
D
bbb M C B
2X
BOTTOM VIEW
e/2
b
c
20
c1
33
b1
6
B
4X
21
SECTION W-W
32
e1
E
bbb
M
C A
DETAIL Y
3
A
C
H
DATUM
PLANE
A2
5
SEATING
PLANE
64X
b
aaa
M
A4
C A B
E3
W
GAUGE
PLANE
0.35
θ
W
A1
A3
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.15 PER SIDE. DIMENSION "D1" AND "E1" DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSION "b" DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. DATUMS -A- AND -B- TO BE DETERMINED AT
DATUM PLANE -H-.
ccc
L
(1.6)
DETAIL Y
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
DIM
A
A1
A2
A3
A4
D
D1
D2
D3
D4
E
E1
E2
E3
L
b
b1
c
c1
e
e1
h
θ
aaa
bbb
ccc
MILLIMETERS
MIN
MAX
--3.15
--0.25
2.5
2.9
0
0.1
0.8
1
16.95
17.45
13.9
14.1
12.5
12.9
9.3
9.7
13.4
13.6
16.95
17.45
13.9
14.1
2.35
2.65
9.3
9.7
0.8
1.1
0.22
0.38
0.22
0.33
0.23
0.32
0.23
0.29
0.65 BSC
2.925 BSC
--0.8
0˚
7˚
0.12
0.2
0.1
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29
Freescale Semiconductor, Inc.
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NOTES
33888
30
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
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NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
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Freescale Semiconductor, Inc.
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MC33888