DATASHEET

ISL6506BI
SIGNS
DED FOR NEW DE
EN
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Data
Sheet
PLAC
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contact our Tech
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1-888-INTERSIL or
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6506BIBZ complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates the control of the 5VDUAL and 3.3VDUAL rails into
an 8 Ld EPAD SOIC package. The ISL6506BIBZ operating
mode (active outputs or sleep outputs) is selectable through
two digital control pins; S3 and S5.
A completely integrated linear regulator generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output
during sleep states (S3, S4/S5). In active states (during S0
and S1/S2), the ISL6506BIBZ uses an external N-Channel
pass MOSFET to connect the outputs directly to the 3.3V
input supplied by an ATX power supply, for minimal losses.
The ISL6506BIBZ powers up the 5VDUAL plane by switching
in the ATX 5V output through an NMOS transistor in active
states, or by switching in the ATX 5VSB through a PMOS (or
PNP) transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6506BIBZ 5VDUAL output is shut down.
September 12, 2013
FN7814.2
Features
• Provides 2 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
• Excellent 3.3VDUAL Regulation in S3/S4/S5
- ±2.0% Over-Temperature
- 2A Capability
• Small Size; Very Low External Component Count
• Over-Temperature Shutdown
• Pb-Free Available (RoHS Compliant)
Applications
• ACPI-Compliant Power Regulation for Motherboards
- 5VDUAL is shut down in S4/S5 sleep states
Pinout
ISL6506BIBZ
(8 LD EPSOIC)
TOP VIEW
The ISL6506BIBZ features a 2A current limit on the internal
3.3V LDO.
VCC
1
3V3AUX
2
8
N/C
7
5VDLSB
GND
S3
3
6
DLA
S5
4
5
GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL6506BIBZ
6506B IBZ
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
8 Ld EPSOIC
PKG.
DWG. #
M8.15C
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6506BI. For more information on MSL please see techbrief TB363.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6506BI
Block Diagram
DLA
S3
VCC
12V POR
SENSE
3.5Ω
S5
10µA
10µA
MONITOR
AND
CONTROL
5VDLSB
TEMPERATURE
MONITOR
SOFT-START
7.5µA
VCC
DIGITAL
( SOFT-START )
+
-
UV DETECTOR
EA1
3V3AUX
GND
Typical Application
12VATX
5VSBY
3V3ATX
5VSBY
5VATX
1kΩ
Cg
(OPTIONAL)
ISL6506BIBZ
2
SLP_S3
SLP_S5
3
4
VCC
NC
3V3AUX
5VDLSB
S3
EPAD
1
S5
9
2
DLA
GND
8
5VDUAL
7
Q2
6
Q3
5
Q1
3V3DUAL
FN7814.2
September 12, 2013
ISL6506BI
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4000V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
EPSOIC Package (Notes 4, 5) . . . . . .
40
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions. Boldface limits apply over the operating temperature range, -40°C
to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
VS3 = 5V, VS5 = 5V (S0 State)
-
3.60
-
mA
VS3 = 0V, VS5 = 5V (S3 State)
-
4.60
-
mA
VS5 = 0V (S5 State)
-
4.60
-
mA
Rising 5VSB POR Threshold
-
-
4.5
V
Falling 5VSB POR Threshold
3.60
-
3.95
V
8.9
9.8
11
V
POWER-ON RESET
Rising 12V POR Threshold
1.00kΩ resistor between DLA and 12V Rail
3.3VAUX LINEAR REGULATOR
-
-
2.0
%
V3V3SB
V5VSBY = 5.0V, I3V3SB = 0A
-
3.3
-
V
3V3SB Undervoltage Threshold
V3V3SB_UV
-
2.5
-
V
3V3SB Overcurrent Trip
I3V3SB_TRIP
-
-
2
A
20
-
35
mA
-
58
-
µs
6.55
8.2
9.85
ms
-
-7.5
-
µA
High Level Input Threshold
-
-
2.2
V
Low Level Input Threshold
0.8
-
-
V
-
10
-
µA
-
140
-
°C
Regulation
3V3SB Nominal Voltage Level
5VDUAL SWITCH CONTROLLER
5VDLSB Output Drive Current
I5VDLSB
V5VDLSB = 4V, V5VSB = 5V
TIMING INTERVAL
S0 to S3 Transition Delay
SOFT-START
Soft-start Interval
tSS
5VDLSB Soft-start Current Source
CONTROL I/O (S3, S5)
S3, S5 Internal Pull-down Current to GND
TEMPERATURE MONITOR
Shutdown-Level Threshold
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
3
FN7814.2
September 12, 2013
ISL6506BI
Functional Pin Description
VCC (Pin 1)
Provide a very well decoupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
Initialization
The ISL6506BIBZ automatically initializes upon receipt of
input power. The Power-On Reset (POR) function
continually monitors the 5VSB input supply voltage. The
ISL6506BIBZ also monitors the 12V rail to insure that the
ATX rails are up before entering into the S0 state even if
both SLP_S3 and SLP_S5 are both high.
Dual Outputs Operational Truth Table
GND (Pin 5, Pad)
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
S3 and S5 (Pins 3 and 4)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull-down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3 and S5 to the computer
system’s SLP_S3 and SLP_S5 signals, respectively.
3V3AUX (Pin 2)
Table 1 describes the truth combinations pertaining to the
3.3VDUAL and 5VDUAL outputs. The internal circuitry does
not allow the transition from an S4/S5 state to an S3 state.
TABLE 1. 5VDUAL OUTPUT TRUTH TABLE
S5
S3
3.3AUX
5VDL
COMMENTS
1
1
3.3V
5V
S0/S1/S2 States (Active)
1
0
3.3V
5V
S3
0
1
0
0
Note
3.3V
Maintains Previous State
0V
S4/S5
NOTE: Combination Not Allowed.
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
DLA (Pin 6)
This pin is an open-drain output. A 1kΩ resistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3VAUX and 5VDUAL outputs, respectively. This pin
is also used to monitor the 12V rail during POR. If a resistor
other than 1kΩ is used, the POR level will be affected.
Functional Timing Diagram
Figure 1 is a simplified timing diagram, detailing the powerup/down sequences of all the outputs in response to the status
of the sleep-state pins (S3, S5), as well as the status of the
input ATX supply. Not shown in this diagram is the deglitching
feature used to protect against false sleep state tripping.
Additionally, the ISL6506BIBZ features a 60µs delay in
transitioning from S0 to S3 states. The transition from the S0
state to S4/S5 state is immediate.
5VSB
S3
S5
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
In S3 sleep state, this transistor is switched on, connecting
the ATX 5VSB output to the 5VDUAL regulator output.
Description
3.3V, 5V, 12V
DLA
3V3AUX
5VDLSB
Operation
5VDL
The ISL6506BIBZ controls 2 output voltages, 3.3VDUAL and
5VDUAL. It is designed for microprocessor computer
applications requiring 3.3V, 5V, 5VSB, and 12V bias input
from an ATX power supply. The IC is composed of one linear
controller/regulator supplying the computer system’s
3.3VDUAL power, a dual switch controller supplying the
5VDUAL voltage, as well as all the control and monitoring
functions necessary for complete ACPI implementation.
4
FIGURE 1. 5VDUAL AND 3.3VAUX TIMING DIAGRAM;
ISL6506BIBZ
Soft-Start
Figures 2 and 3 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5VSB (bias)
is applied to the circuit. At time t1, the 5VSB surpasses POR
level. Time t2, one soft-start interval after t1, denotes the
FN7814.2
September 12, 2013
ISL6506BI
initiation of soft-start. The 3.3VDUAL rail is brought up
through the internal standby LDO through an internal digital
soft-start function. Figure 3 shows the 5VDUAL rail initiating a
soft-start at time t2 as well.
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506BIBZ
(Figure 2), the 5VDUAL rail will begin to ramp-up from the
5VATX rail through the body diode of the N-MOSFET (Q3). At
time t5, the 12VATX rail has surpassed the 12V POR level.
Time t6 is three soft-start cycles after the 12V POR level has
been surpassed. At time t6, three events occur
simultaneously. The DLA pin is forced to a high impedance
state which allows the 12V rail to enhance the two NMOSFETs (Q1 and Q3) that connect the ATX rails to the
3.3VDUAL and 5VDUAL rails. The 5VDLSB pin is actively
pulled high, which will turn the P-MOSFET (Q2) off. Finally,
the internal LDO which regulates the 3.3VAUX rail in sleep
states is put in standby mode.
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
5VSB
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
0V
5VDLSB
(5V/DIV)
t0
t1
t2
DLA
(10V/DIV)
t3
t4 t5
TIME
t6
FIGURE 3. SOFT-START INTERVAL FOR S3 TO S0
TRANSITION FOR ISL6506BIBZ
Internal Linear Regulator Undervoltage Protection
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
0V
DLA
(10V/DIV)
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft-start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft-start interval later, the 3.3V linear
regulator is retried with a soft-start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
Internal Linear Regulator Overcurrent Protection
t0
t1
t2
t3
t4 t5
TIME
t6
FIGURE 2. ISL6506BIBZ SOFT-START INTERVAL IN S4/S5
STATE AND S5 TO S0 TRANSITION
Sleep to Wake State Transitions
Figures 2 and 3, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 2 shows the
transition of the ISL6506BIBZ from the S4/S5 state to the S0
state. Figure 3 shows how the ISL6506BIBZ will transition
from the S3 sleep state into S0 state. For all transitions, t4
depicts the system transition into the S0 state. Here, the ATX
supplies are enabled and begin to ramp up. At time t5, the
12VATX rail has exceeded the POR threshold. Three softstart periods after time t5, at time t6, three events occur
simultaneously. The DLA pin is forced to a high impedance
state, which allows the 12V rail to enhance the two NMOSFETs (Q1 and Q3) that connect the ATX rails to the
3.3VDUAL and 5VDUAL rails. The 5VDLSB pin is actively
pulled high, which will turn the P-MOSFET (Q2) off. Finally,
the internal LDO which regulates the 3.3VDUAL rail in sleep
states is put in standby mode.
5
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced, which
causes the output voltage of the linear regulator to be
reduced. When the output voltage is reduced to the
undervoltage trip point, the undervoltage protection is
initiated and the output will shutdown.
Layout Considerations
The typical application employing an ISL6506BIBZ is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3VDUAL island or the I/O circuitry. Ensure the
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5VSB) carries a similar level
of current (for best results, ensure it is connected to its
respective source through an adequately sized trace and is
FN7814.2
September 12, 2013
ISL6506BI
properly decoupled). The pass transistors should be placed
on pads capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
Placement of the decoupling and bulk capacitors should
reflect their purpose. As such, the high-frequency
decoupling capacitors should be placed as close as possible
to the load they are decoupling; the ones decoupling the
controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
electrolytics or tantalum capacitors) placement is not as
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
Component Selection Guidelines
Locate all small signal components close to the respective
pins of the control IC, and connect them to ground, if
applicable, through a via placed close to the ground pad.
12VATX
5VSB
CIN
5VDLSB
C5VSB
5VDUAL
+3.3VIN
Also, during the transition between active and sleep states
on the 5VDUAL output, there is a short interval of time during
which none of the power pass elements are conducting.
During this time the output capacitors have to supply all the
output current. The output voltage drop during this brief
period of time can be easily approximated using Equation 1:
(EQ. 1)
C5V
CHF5V
LOAD
where:
ISL6506BIBZ
ΔVOUT = output voltage drop
ESROUT = output capacitor bank ESR
Q2
DLA
Q4
IOUT = output current during transition
3V3DUAL
3V3AUX
LOAD
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0/S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
tt ⎞
⎛
ΔV OUT = I OUT × ⎜ ESR OUT + ----------------⎟
C
⎝
OUT⎠
Q3
VCC
Output Capacitors Selection
CHF3V
5VATX
C3V
GND
EPAD
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended.
Figure 4 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. The EPAD should be
tied to the ground plane with three to five vias for good
thermal management. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
6
COUT = output capacitor bank capacitance
tt = active-to-sleep/sleep-to-active transition time (10µs
typical)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an ISL6506BIBZ application must
have a sufficiently low ESR so as not to allow the input
voltage to dip excessively when energy is transferred to the
output capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6506BIBZ’s regulation levels could have
as a result a brisk transfer of energy from the input
capacitors to the supplied outputs. At the transition between
active and sleep states, such phenomena could be
responsible for the 5VSB voltage drooping excessively and
affecting the output regulation. The solution to such a
potential problem is using larger input capacitors with a
lower total combined ESR.
FN7814.2
September 12, 2013
ISL6506BI
Transistor Selection/Considerations
The ISL6506BIBZ usually requires one P-Channel and two
N-Channel MOSFETs. All three of these MOSFETs are
utilized as ON/OFF switching elements.
One important criteria for selection of transistors for all the
switching elements is package selection for efficient removal
of heat. The power dissipated in a switch element while on is
shown in Equation 2:
2
P LOSS = I o × r DS ( ON )
(EQ. 2)
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1, Q3
These N-Channel MOSFETs are used to switch the 3.3V and
5V inputs provided by the ATX supply into the 3.3VAUX and
5VDUAL outputs while in active (S0, S1) state. The main
criteria for the selection of these transistors is output voltage
budgeting. The maximum rDS(ON) allowed at highest junction
temperature can be expressed using Equation 3:
V INmin – V OUTmin
r DS ( ON )max = --------------------------------------------------I OUTmax
(EQ. 3)
where:
VINmin = minimum input voltage
VOUTmin = minimum output voltage allowed
IOUTmax = maximum output current
Q2
This is a P-Channel MOSFET used to switch the 5VSB
output of the ATX supply into the 5VDUAL output during
sleep states. The selection criteria of this device, as with the
N-Channel MOSFETs, is proper voltage budgeting. The
maximum rDS(ON) , however, has to be achieved with only
4.5V of gate-to-source voltage, so a true logic level
MOSFET needs to be selected.
7
FN7814.2
September 12, 2013
ISL6506BI
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15C
N
INDEX
AREA
H
0.25(0.010) M
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
TOP VIEW
L
SEATING PLANE
-A-
A
D
-C-
e
α
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
SIDE VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.056
0.066
1.43
1.68
-
A1
0.001
0.005
0.03
0.13
-
B
0.0138
0.0192
0.35
0.49
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.811
3.99
4
e
h x 45°
MIN
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N
α
8
0°
8
7
8°
-
P
-
0.126
-
3.200
11
P1
-
0.099
-
2.514
11
Rev. 1 6/05
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
N
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7814.2
September 12, 2013