Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 SN6501-Q1 Transformer Driver for Isolated Power Supplies 1 Features 3 Description • • The SN6501-Q1 is a monolithic oscillator/powerdriver, specifically designed for small form factor, isolated power supplies in isolated interface applications. The device drives a low-profile, centertapped transformer primary from a 3.3-V or 5-V DC power supply. The secondary can be wound to provide any isolated voltage based on transformer turns ratio. 1 • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C4B Push-Pull Driver for Small Transformers Single 3.3-V or 5-V Supply High Primary-side Current Drive: – 5-V Supply: 350 mA (Max) – 3.3-V Supply: 150 mA (Max) Low Ripple on Rectified Output Permits Small Output Capacitors Small 5-Pin SOT-23 Package 2 Applications • • • • Isolated Interface Power Supply for CAN, RS-485, RS-422, RS-232, SPI, I2C, Low-Power LAN Industrial Automation Process Control Medical Equipment The SN6501-Q1 consists of an oscillator followed by a gate drive circuit that provides the complementary output signals to drive the ground referenced Nchannel power switches. The internal logic ensures break-before-make action between the two switches. The SN6501-Q1 is available in a small SOT-23 (5) package, and is specified for operation at temperatures from –40°C to 125°C. Device Information(1) PART NUMBER SN6501-Q1 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space Simplified Schematic Output Voltage and Efficiency vs Output Current 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 3 4 4 4 4 5 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 11 Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application .................................................. 15 10 Power Supply Recommendations ..................... 26 11 Layout................................................................... 26 11.1 Layout Guidelines ................................................. 26 11.2 Layout Example .................................................... 26 12 Device and Documentation Support ................. 27 12.1 12.2 12.3 12.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 13 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History Changes from Original (June 2013) to Revision A Page • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 • Changed Equation 10........................................................................................................................................................... 18 • Changed Equation 11........................................................................................................................................................... 18 • Changed Table 4, From: Wuerth-Elektronik / Midcom To: Wurth Electronics Midcom Inc .................................................. 21 • Changed Figure 54............................................................................................................................................................... 24 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 5 Pin Configuration and Functions 5-Pin SOT-23 DBV Package Top View D1 1 VCC 2 D2 3 5 GND 4 GND Pin Functions PIN NAME NUMBER TYPE D1 1 OD VCC 2 P D2 3 OD GND 4,5 P DESCRIPTION Open Drain output 1. Connect this pin to one end of the transformer primary side. Supply voltage input. Connect this pin to the center-tap of the transformer primary side. Buffer this voltage with a 1 μF to 10 μF ceramic capacitor. Open Drain output 2. Connect this pin to the other end of the transformer primary side. Device ground. Connect this pin to board ground. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.3 6 V Output switch voltage 14 V ID1P, ID2P Peak output switch current 500 mA PTOT Continuous power dissipation 250 mW TJ Junction temperature 170 °C VCC Supply voltage VD1, VD2 (1) Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability. 6.2 Handling Ratings Tstg Storage temperature range V(ESD) Electrostatic discharge Human body model (HBM) AEC-Q100 Classification Level H2, all pins Charged device model (CDM) AEC-Q100 Classification Level C4B, all pins MIN MAX UNIT –65 150 °C –2 2 kV –750 750 V Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 3 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com 6.3 Recommended Operating Conditions VCC MIN TYP MAX 3 5.5 0 11 0 7.2 Supply voltage VD1, VD2 Output switch voltage ID1, ID2 D1 and D2 output switch current – Primary-side TA VCC = 5 V ± 10%, VCC = 3.3 V ± 10% When connected to Transformer with primary winding Center-tapped VCC = 5 V ± 10% VD1, VD2 Swing ≥ 3.8 V, see Figure 32 for typical characteristics 350 VCC = 3.3 V ± 10% VD1, VD2 Swing ≥ 2.5 V, see Figure 31 for typical characteristics 150 UNIT V V mA Ambient temperature –40 125 °C 6.4 Thermal Information SN6501 THERMAL METRIC (1) DBV 5-PINS θJA Junction-to-ambient thermal resistance 208.3 θJCtop Junction-to-case (top) thermal resistance 87.1 θJB Junction-to-board thermal resistance 40.4 ψJT Junction-to-top characterization parameter 5.2 ψJB Junction-to-board characterization parameter 39.7 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over full-range of recommended operating conditions, unless otherwise noted PARAMETER RON Switch-on resistance ICC Average supply current (1) fST Startup frequency fSW D1, D2 Switching frequency (1) TEST CONDITIONS MIN TYP MAX 1 3 VCC = 5 V ± 10%, See Figure 36 0.6 2 VCC = 3.3 V ± 10%, no load 150 400 VCC = 5 V ± 10%, no load 300 700 VCC = 2.4 V, See Figure 36 300 VCC = 3.3 V ± 10%, See Figure 36 UNIT Ω µA kHz VCC = 3.3 V ± 10%, See Figure 36 250 360 495 VCC = 5 V ± 10%, See Figure 36 300 410 620 MIN TYP kHz Average supply current is the current used by SN6501 only. It does not include load current. 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER tr-D D1, D2 output rise time tf-D D1, D2 output fall time tBBM Break-before-make time 4 TEST CONDITIONS VCC = 3.3 V ± 10%, See Figure 36 70 VCC = 5 V ± 10%, See Figure 36 80 VCC = 3.3 V ± 10%, See Figure 36 VCC = 5 V ± 10%, See Figure 36 VCC = 3.3 V ± 10%, See Figure 36 VCC = 5 V ± 10%, See Figure 36 Submit Documentation Feedback 110 60 150 50 MAX UNIT ns ns ns Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 6.7 Typical Characteristics TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35 (TA = 25°C unless otherwise noted). See Table 3 for Transformer Specifications. 90 80 5 TP1 70 Efficiency - % VOUT - V 4 TP1 3 2 0 0 50 40 30 20 T1 = 760390011 (2.5kV) VIN = 3.3V, VOUT = 3.3V 1 60 T1 = 760390011 (2.5kV) VIN = 3.3V, VOUT = 3.3V 10 0 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA ILOAD - mA Figure 1. Output Voltage vs Load Current Figure 2. Efficiency vs Load Current 90 6 TP1 80 5 Efficiency - % 70 VOUT - V 4 3 2 0 TP1 60 50 40 30 20 T1 = 760390012 (2.5kV) VIN = 5V, VOUT = 5V 1 0 T1 = 760390012 (2.5kV) VIN = 5V, VOUT = 5V 10 0 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA Figure 3. Output Voltage vs. Load Current Figure 4. Efficiency vs Load Current 90 TP1 80 5 TP1 Efficiency - % 70 4 VOUT - V 10 20 30 40 50 60 70 80 90 100 ILOAD - mA 6 3 2 60 50 40 30 20 T1 = 760390013 (2.5kV) VIN = 3.3V, VOUT = 5V 1 0 10 20 30 40 50 60 70 80 90 100 0 0 T1 = 760390013 (2.5kV) VIN = 3.3V, VOUT = 5V 10 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA ILOAD - mA Figure 5. Output Voltage vs Load Current Figure 6. Efficiency vs Load Current Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 5 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics (continued) TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35 (TA = 25°C unless otherwise noted). See Table 3 for Transformer Specifications. 90 5 TP1 3 Efficiency - % VOUT - V 4 TP2 2 0 0 TP1 70 TP2 60 50 40 30 20 T1 = 760390014 (2.5kV) VIN = 3.3V, VOUT = 3.3V 1 80 T1 = 760390014 (2.5kV) VIN = 3.3V, VOUT = 3.3V 10 0 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA 10 20 30 40 50 60 70 80 90 100 ILOAD - mA Figure 7. Output Voltage vs Load Current Figure 8. Efficiency vs Load Current 8 90 TP1 80 7 TP1 70 5 Efficiency - % VOUT - V 6 TP2 4 3 2 50 40 30 20 T1 = 760390014 (2.5kV) VIN = 5V, VOUT = 5V 1 0 TP2 60 0 T1 = 760390014 (2.5kV) VIN = 5V, VOUT = 5V 10 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA Figure 9. Output Voltage vs Load Current Figure 10. Efficiency vs Load Current 7 TP1 VOUT - V 6 5 TP2 4 3 2 T1 = 760390015 (2.5kV) VIN = 3.3V, VOUT = 5V 1 0 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA Figure 11. Output Voltage vs Load Current 6 Submit Documentation Feedback Figure 12. Efficiency vs Load Current Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 Typical Characteristics (continued) TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35 (TA = 25°C unless otherwise noted). See Table 3 for Transformer Specifications. 90 80 5 TP1 4 TP1 3 TP2 Efficiency - % VOUT - V 70 2 0 0 50 40 30 20 T1 = 750313710 (2.5kV) VIN = 5V, VOUT = 3.3V 1 TP2 60 T1 = 750313710 (2.5kV) VIN = 5V, VOUT = 3.3V 10 0 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA 10 20 30 40 50 60 70 80 90 100 ILOAD - mA Figure 13. Output Voltage vs Load Current Figure 14. Efficiency vs Load Current 90 6 80 5 TP1 70 Efficiency - % VOUT - V 4 TP1 3 2 T1 = 750313734 (5kV) VIN = 3.3V, VOUT = 3.3V 1 0 60 50 40 30 20 T1 = 750313734 (5kV) VIN = 3.3V, VOUT = 3.3V 10 0 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA 0 Figure 15. Output Voltage vs Load Current Figure 16. Efficiency vs Load Current 90 6 TP1 80 5 Efficiency - % 70 VOUT - V 4 3 2 50 40 30 T1 = 750313734 (5kV) VIN = 5V, VOUT = 5V 10 0 0 TP1 60 20 T1 = 750313734 (5kV) VIN = 5V, VOUT = 5V 1 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA ILOAD - mA Figure 17. Output Voltage vs Load Current Figure 18. Efficiency vs Load Current Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 7 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics (continued) TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35 (TA = 25°C unless otherwise noted). See Table 3 for Transformer Specifications. Figure 19. Output Voltage vs Load Current Figure 20. Efficiency vs Load Current 90 6 Efficiency - % VOUT - V TP2 70 TP1 4 3 TP2 2 60 50 40 30 20 1 0 TP1 80 5 T1 = 750313638 (5kV) VIN = 3.3V, VOUT = 3.3V 0 T1 = 750313638 (5kV) VIN = 3.3V, VOUT = 3.3V 10 0 10 20 30 40 50 60 70 80 90 100 0 Figure 21. Output Voltage vs Load Current Figure 22. Efficiency vs Load Current 8 90 80 7 TP1 Efficiency - % VOUT - V 5 TP2 4 3 2 TP2 60 50 40 30 20 T1 = 750313638 (5kV) VIN = 5V, VOUT = 5V 1 0 T1 = 750313638 (5kV) VIN = 5V, VOUT = 5V 10 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA Figure 23. Output Voltage vs Load Current 8 TP1 70 6 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA ILOAD - mA Submit Documentation Feedback Figure 24. Efficiency vs Load Current Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 Typical Characteristics (continued) TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35 (TA = 25°C unless otherwise noted). See Table 3 for Transformer Specifications. 90 8 80 7 6 VOUT - V TP2 60 5 TP2 50 4 40 3 30 2 20 T1 = 750313626 (5kV) VIN = 3.3V, VOUT = 5V 1 0 TP1 70 TP1 0 0 T1 = 750313626 (5kV) VIN = 3.3V, VOUT = 5V 10 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 ILOAD - mA ILOAD - mA Figure 26. Efficiency vs Load Current Figure 25. Output Voltage vs Load Current 90 6 80 5 TP1 4 TP1 3 TP2 Efficiency - % VOUT - V 70 2 1 0 50 40 30 20 T1 = 750313638 (5kV) VIN = 5V, VOUT = 3.3V 0 TP2 60 T1 = 750313638 (5kV) VIN = 5V, VOUT = 3.3V 10 10 20 30 40 50 60 70 80 90 100 0 ILOAD - mA 0 Figure 28. Efficiency vs Load Current Figure 27. Output Voltage vs Load Current 460 350 300 440 VCC = 5V f - Frequency - kHz ICC – Supply Current - µA 10 20 30 40 50 60 70 80 90 100 250 200 150 VCC = 3.3V 100 VCC = 5V 420 400 380 VCC = 3.3V 360 340 50 0 -55 -35 -15 5 25 45 65 85 105 125 320 -55 -35 -15 5 25 45 65 85 105 125 TA - Free Air Temperature - oC TA - Free Air Temperature - oC Figure 29. Average Supply Current vs Free-Air Temperature Figure 30. D1, D2 Switching Frequency vs Free-Air Temperature Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 9 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics (continued) TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35 (TA = 25°C unless otherwise noted). See Table 3 for Transformer Specifications. 5.00 VD1, VD2 - Voltage Swing - V VD1, VD2 - Voltage Swing - V 3.30 3.25 VCC = 3.3V 3.20 3.15 3.10 3.05 3.00 0 10 50 100 150 200 4.95 VCC = 5V 4.90 4.85 4.80 4.75 4.70 4.65 4.60 4.55 0 100 200 300 400 ID1, ID2 - Switching Current - mA ID1, ID2 - Switching Current - mA Figure 31. D1, D2 Primary-Side Output Switch Voltage Swing vs Current Figure 32. D1, D2 Primary-Side Output Switch Voltage Swing vs Current Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 7 Parameter Measurement Information Figure 33. Measurement Circuit for Unregulated Output (TP1) Figure 34. Timing Diagram Figure 35. Measurement Circuit for regulated Output (TP1 and TP2) Figure 36. Test Circuit For RON, FSW, FSt, Tr-D, Tf-D, TBBM 8 Detailed Description 8.1 Overview The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 11 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Overview (continued) The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, present the gate-drive signals for the output transistors. As shown in the functional block diagram, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are highimpedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Push-Pull Converter Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary (see Figure 37). CR1 C VIN CR1 VOUT C RL RL VIN CR2 Q2 VOUT Q1 CR2 Q2 Q1 Figure 37. Switching Cycles of a Push-Pull Converter When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative voltage potential at the lower primary end with regards to the VIN potential at the center-tap. At the same time the voltage across the upper half of the primary is such that the upper primary end is positive with regards to the center-tap in order to maintain the previously established current flow through Q2, which now has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a voltage potential at the open end of the primary of 2×VIN with regards to ground. Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance RL back to the center-tap. 12 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 Feature Description (continued) When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse. Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2 is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2, charging the capacitor and returning through the load to the center-tap. 8.3.2 Core Magnetization Figure 38 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2 conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON. B VIN A’ VP H RDS VDS A VIN = VP + VDS Figure 38. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on) This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle. If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the transformer slowly creeps toward the saturation region. Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the SN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VP is gradually reduced and V-t balance restored. 8.4 Device Functional Modes The functional modes of the SN6501 are divided into start-up, operating, and off-mode. 8.4.1 Start-Up Mode When the supply voltage at Vcc ramps up to 2.4V typical, the internal oscillator starts operating at a start frequency of 300 kHz. The output stage begins switching but the amplitude of the drain signals at D1 and D2 has not reached its full maximum yet. 8.4.2 Operating Mode When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations over supply voltage and operating temperature can vary the switching frequencies at D1 and D2 between 250 kHz and 495 kHz for VCC = 3.3 V ±10%, and between 300 kHz and 620 kHz for VCC = 5 V ±10%. 8.4.3 Off-Mode The SN6501 is deactivated by reducing VCC to 0 V. In this state both drain outputs, D1 and D2, are highimpedance. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 13 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off. Figure 39. SN6501-Q1 Block Diagram The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gatedrive signals for the output transistors Q1 and Q2. As shown in Figure 40, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary. fOSC S S G1 G2 Q1 Q2 Figure 40. Detailed Output Signal Waveforms 14 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 9.2 Typical Application Figure 41. Typical Application Schematic (SN6501-Q1) 9.2.1 Design Requirements For this design example, use the parameters listed in Table 1 as design parameters. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 3.3 V ± 3% Output voltage 5V Maximum load current 100 mA 9.2.2 Detailed Design Procedure The following recommendations on components selection focus on the design of an efficient push-pull converter with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter output drops significantly over a wide range in load current. The characteristic curve in Figure 11 for example shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a transceiver’s supply range. Therefore, in order to provide a stable, load independent supply while maintaining maximum possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised. The final converter circuit is shown in Figure 45. The measured VOUT and efficiency characteristics for the regulated and unregulated outputs are shown in Figure 1 to Figure 28. 9.2.2.1 SN6501 Drive Capability The SN6501 transformer driver is designed for low-power push-pull converters with input and output voltages in the range of 3 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken that higher turns ratios don’t lead to primary currents that exceed the SN6501 specified current limits. 9.2.2.2 LDO Selection The minimum requirements for a suitable low dropout regulator are: • Its current drive capability should slightly exceed the specified load current of the application to prevent the LDO from dropping out of regulation. Therefore for a load current of 100 mA, choose a 100 mA to 150 mA LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout voltages that will reduce overall converter efficiency. • The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain efficiency. For a low-cost 150 mA LDO, a VDO of 150 mV at 100 mA is common. Be aware however, that this lower value is usually specified at room temperature and can increase by a factor of 2 over temperature, which in turn will raise the required minimum input voltage. • The required minimum input voltage preventing the regulator from dropping out of line regulation is given with: VI-min = VDO-max + VO-max (1) Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 15 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 • www.ti.com This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO and VO specified in the LDO data sheet for rated output current (i.e., 100 mA) and add them together. Also specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than VImin. If it is not, the LDO will lose line-regulation and any variations at the input will pass straight through to the output. Hence below VI-min the output voltage will follow the input and the regulator behaves like a simple conductor. The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this condition there is no secondary current reflected back to the primary, thus making the voltage drop across RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point the secondary reaches its maximum voltage of VS-max = VIN-max × n (2) with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the LDO from damage the maximum regulator input voltage must be higher than VS-max. Table 2 lists the maximum secondary voltages for various turns ratios commonly applied in push-pull converters with 100 mA output drive. Table 2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations PUSH-PULL CONVERTER LDO CONFIGURATION VIN-max [V] TURNS-RATIO VS-max [V] VI-max [V] 3.3 VIN to 3.3 VOUT 3.6 1.5 ± 3% 5.6 6 to 10 3.3 VIN to 5 VOUT 3.6 2.2 ± 3% 8.2 10 5 VIN to 5 VOUT 5.5 1.5 ± 3% 8.5 10 9.2.2.3 Diode Selection A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output as possible. When used in high-frequency switching applications, such as the SN6501 however, the diode must also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperatures of up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher DC blocking voltage of 30 V. Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as RB168M-40. 1 Forward Current, IF - A Forward Current, IF - A 1 0°C TJ = 100°C 75°C 25°C -25°C 0.1 0.01 TJ = 125°C 75°C 25°C -40°C 0.1 0.01 0.1 0.2 0.3 0.4 Forward Voltage, VF - V 0.5 0.2 0.3 0.4 Forward Voltage, VF - V 0.5 Figure 42. Diode Forward Characteristics for MBR0520L (Left) and MBR0530 (Right) 16 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 9.2.2.4 Capacitor Selection The capacitors in the converter circuit in Figure 45 are multi-layer ceramic chip (MLCC) capacitors. As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF. The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a reference plane or to the primary center-tap. The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 1 μF to 10 μF. The small capacitor at the regulator input is not necessarily required. However, good analog design practice suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection. The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements. 9.2.2.5 Transformer Selection 9.2.2.5.1 V-t Product Calculation To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input plus 10%. The maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified input voltage. Therefore, the transformer’s minimum V-t product is determined through: Vtmin ³ VIN-max ´ Tmax 2 = VIN-max 2 ´ fmin (3) Inserting the numeric values from the data sheet into the equation above yields the minimum V-t products of Vtmin ³ 3.6 V = 7.2 Vμs 2 ´ 250 kHz Vtmin ³ 5.5 V = 9.1 Vμs for 5 V applications. 2 ´ 300 kHz for 3.3 V, and (4) Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only. While Vt-wise all of these transformers can be driven by the SN6501, other important factors such as isolation voltage, transformer wattage, and turns ratio must be considered before making the final decision. 9.2.2.5.2 Turns Ratio Estimate Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the transformer choosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer websites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull converter to operate flawlessly over the specified current and temperature range. This minimum transformation ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction factor that takes the transformer’s typical efficiency of 97% into account: VP-min = VIN-min - VDS-max (5) VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still provide sufficient input voltage for the regulator to remain in regulation. From the LDO SELECTION section, this minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with: VS-min = VF-max + VDO-max + VO-max (6) Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 17 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com VF VI VDO VO VS VIN RL VP VDS RDS Q Figure 43. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible drainsource voltage of the SN6501, VDS-max, from the minimum converter input voltage VIN-min: VP-min = VIN-min – VDS-max (7) VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the SN6501 data sheet: VDS-max = RDS-max × IDmax (8) Then inserting Equation 8 into Equation 7 yields: VP-min = VIN-min - RDS-max x IDmax (9) and inserting Equation 9 and Equation 6 into Equation 5 provides the minimum turns ration with: V + VDO-max + VO-max nmin = 1.031 ´ F-max VIN-min - RDS-max ´ ID-max (10) Example: For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO TPS76350, the data sheet values taken for a load current of 100 mA and a maximum temperature of 85°C are VF-max = 0.2 V, VDO-max = 0.2 V, and VO-max = 5.175 V. Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2% accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at 3.3 V are taken from the SN6501 data sheet with RDS-max = 3 Ω and ID-max = 150 mA. Inserting the values above into Equation 10 yields a minimum turns ratio of: 0.2V + 0.2V + 5.175 V nmin = 1.031 ´ =2 3.234 V - 3 Ω ´ 150 mA (11) Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3 with a common tolerance of ±3%. 9.2.2.5.3 Recommended Transformers Depending on the application, use the minimum configuration in Figure 44 or standard configuration in Figure 45. 18 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 Figure 44. Unregulated Output for Low-Current Loads With Wide Supply Range Figure 45. Regulated Output for Stable Supplies and High Current Loads The Wurth Electronics Midcom isolation transformers in Table 3 are optimized designs for the SN6501, providing high efficiency and small form factor at low-cost. The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents. These applications operate without LDO, thus achieving further cost-reduction. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 19 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Table 3. Recommended Isolation Transformers Optimized for SN6501 Turns Ratio VxT (Vμs) 1:1.1 ±2% 7 Isolation (VRMS) Dimensions (mm) Application LDO 3.3 V → 3.3 V Figures Order No. Figure 1 Figure 2 760390011 Figure 3 Figure 4 760390012 1:1.1 ±2% 5V→5V 1:1.7 ±2% 3.3 V → 5 V Figure 5 Figure 6 760390013 3.3 V → 3.3 V 5V→5V Figure 7 Figure 8 Figure 9 Figure 10 760390014 2500 1:1.3 ±2% 6.73 x 10.05 x 4.19 11 No Yes 1:2.1 ±2% 3.3 V → 5 V Figure 11 Figure 12 760390015 1.23:1 ±2% 5 V → 3.3 V Figure 13 Figure 14 750313710 1:1.1 ±2% 3.3 V → 3.3 V Figure 15 Figure 16 750313734 1:1.1 ±2% 5V→5V Figure 17 Figure 18 750313734 1:1.7 ±2% 3.3 V → 5 V Figure 19 Figure 20 750313769 1:1.3 ±2% 3.3 V → 3.3 V 5V→5V Figure 21 Figure 22 Figure 23 Figure 24 750313638 1:2.1 ±2% 3.3 V → 5 V Figure 25 Figure 26 750313626 1.3:1 ±2% 5 V → 3.3 V Figure 27 Figure 28 750313638 11 5000 9.14 x 12.7 x 7.37 No Yes 20 Submit Documentation Feedback Manufacturer Wurth Electronics/ Midcom Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 9.2.3 Application Curve See Table 3 for application curves. 9.2.4 Higher Output Voltage Designs The SN6501 can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to 5, requires different rectifier topologies to achieve high output voltages. Figure 46 to Figure 49 show some of these topologies together with their respective open-circuit output voltages. n n VOUT+ = n·VIN VIN VOUT = 2n·VIN VIN VOUT- = n·VIN Figure 46. Bridge Rectifier With Center-Tapped Secondary Enables Bipolar Outputs Figure 47. Bridge Rectifier Without Center-Tapped Secondary Performs Voltage Doubling VOUT+ = 2n·V IN n VIN n VOUT = 4n·VIN VIN VOUT- = 2n·V IN Figure 48. Half-Wave Rectifier Without CenterTapped Secondary Performs Voltage Doubling, Centered Ground Provides Bipolar Outputs Figure 49. Half-Wave Rectifier Without Centered Ground and Center-Tapped Secondary Performs Voltage Doubling Twice, Hence Quadrupling VIN 9.2.5 Application Circuits The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated micro-controller supply. For 5 V input voltages requiring different turn ratios refer to the transformer manufacturers and their websites listed in Table 4. Table 4. Transformer Manufacturers Coilcraft Inc. http://www.coilcraft.com Halo-Electronics Inc. http://www.haloelectronics.com Murata Power Solutions http://www.murata-ps.com Wurth Electronics Midcom Inc http://www.midcom-inc.com Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 21 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Certain components might not possess AEC-Q100 Q1 qualification. For more detailed information on qualified components for automotive applications please refer to the automotive web page: http://www.ti.com/lsds/ti/apps/automotive/applications.page. Figure 50. Isolated RS-485 Interface 22 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 Figure 51. Isolated Can Interface Figure 52. Isolated RS-232 Interface Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 23 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com Figure 53. Isolated Digital Input Module Figure 54. Isolated SPI Interface for an Analog Input Module With 16 Inputs 24 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 Figure 55. Isolated I2C Interface for an Analog Data Acquisition System With 4 Inputs and 4 Outputs Figure 56. Isolated 4-20 mA Current Loop Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 25 SN6501-Q1 SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 www.ti.com 10 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 3.3 V and 5 V nominal. This input supply must be regulated within ±10%. If the input supply is located more than a few inches from the SN6501 a 0.1μF by-pass capacitor should be connected as possible to the device VCC pin, and a 10 μF capacitor should be connected close to the transformer center-tap pin. 11 Layout 11.1 Layout Guidelines • • • • • • • • The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and a X5R or X7R dielectric. The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 57 for a PCB layout example. The connections between the device D1 and D2 pins and the transformer primary endings, and the connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum trace inductance. • The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a lowESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric. The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance. The ground connections of the capacitors and the ground plane should use two vias for minimum inductance. The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range to maximize efficiency. The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric. 11.2 Layout Example Figure 57. Layout Example of a 2-Layer Board (SN6501) 26 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 SN6501-Q1 www.ti.com SLLSEF3A – JUNE 2013 – REVISED SEPTEMBER 2014 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: SN6501-Q1 27 PACKAGE OPTION ADDENDUM www.ti.com 23-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) SN6501QDBVRQ1 ACTIVE Package Type Package Pins Package Drawing Qty SOT-23 DBV 5 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 125 SBRQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Sep-2014 OTHER QUALIFIED VERSIONS OF SN6501-Q1 : • Catalog: SN6501 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN6501QDBVRQ1 Package Package Pins Type Drawing SPQ SOT-23 3000 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 9.0 Pack Materials-Page 1 3.23 B0 (mm) K0 (mm) P1 (mm) 3.17 1.37 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN6501QDBVRQ1 SOT-23 DBV 5 3000 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated