ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 ISOLATED CAN TRANSCEIVER Check for Samples: ISO1050 FEATURES 1 • • • • • • • • • • • • Meets the Requirements of ISO11898-2 5000-VRMS Isolation (ISO1050DW) 2500-VRMS Isolation (ISO1050DUB) Failsafe Outputs Low Loop Delay: 150ns (Typ), 210ns (Max) 50 kV/μs Typical Transient Immunity Bus-Fault Protection of –27 V to 40 V Driver (TXD) Dominant Time Out Function IEC 60747-5-2 (VDE 0884, Rev. 2) and IEC 61010-1 Approved UL 1577 Double Protection Approved; See Regulatory Information Section IEC 60601-1 (Medical) and CSA Approved 5 KVRMS Reinforced Insulation per TUV Approved for EN/UL/CSA 60950-1 (ISO1050DW) • • I/O Voltage Range Supports 3.3V and 5V Microprocessors Typical 25-Year Life at Rated Working Voltage (see Application Report SLLA197 and Figure 18) APPLICATIONS • • • • • • • Industrial Automation, Control, Sensors and Drive Systems Building and Climate Control (HVAC) Automation Security Systems Transportation Medical Telecom CAN Bus Standards Such as CANopen, DeviceNet, NMEA2000, ARINC825, ISO11783, CAN Kingdom, CANaerospace DESCRIPTION The ISO1050 is a galvanically isolated CAN transceiver that meets the specifications of the ISO11898-2 standard. The device has the logic input and output buffers separated by a silicon oxide (SiO2) insulation barrier that provides galvanic isolation of up to 5000 VRMS for ISO1050DW and 2500 VRMS for ISO1050DUB. Used in conjunction with isolated power supplies, the device prevents noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. As a CAN transceiver, the device provides differential transmit capability to the bus and differential receive capability to a CAN controller at signaling rates up to 1 megabit per second (Mbps). Designed for operation in especially harsh environments, the device features cross-wire, overvoltage and loss of ground protection from –27 V to 40 V and over-temperature shut-down, as well as –12 V to 12 V common-mode range. The ISO1050 is characterized for operation over the ambient temperature range of –55°C to 105°C. DW PACKAGE GND1 GND1 1 2 16 15 VCC2 GND2 3 4 5 6 7 8 14 13 12 nc CANH CANL nc 11 10 9 RXD TXD GALVANIC ISOLATION VCC1 GND1 RXD nc nc TXD DUB PACKAGE FUNCTION DIAGRAM CANH VCC1 RXD 1 2 TXD GND1 3 4 8 7 6 5 VCC2 CANH CANL GND2 CANL GND2 GND2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS PRODUCT RATED ISOLATION PACKAGE MARKED AS ISO1050DUB 2500 VRMS DUB-8 ISO1050 ISO1050DW 5000 VRMS DW-16 ISO1050 ORDERING NUMBER ISO1050DUB (rail) ISO1050DUBR (reel) ISO1050DW (rail) ISO1050DWR (reel) PIN FUNCTIONS PIN NAME PACKAGE DW TYPE DESCRIPTION DUB VCC1 1 1 Supply Digital side supply voltage (3 to 5.5V) GND1 2 NA GND1 Digital side ground connection RXD 3 2 O NC 4 NA NC No connect NC 5 NA NC No connect TXD 6 3 I GND1 7 4 GND1 Digital side ground connection GND1 8 NA GND1 Digital side ground connection GND2 9 5 GND2 Transceiver side ground connection GND2 10 NA GND2 Transceiver side ground connection NC 11 NA NC No connect CANL 12 6 I/O Low level CAN bus line CANH 13 7 I/O High level CAN bus line NC 14 NA NC No connect GND2 15 NA GND2 Transceiver side ground connection VCC2 16 8 Supply Transceiver side supply voltage (5V) 2 CAN receive data output (LOW for dominant and HIGH for recessive bus states) CAN transmit data input (LOW for dominant and HIGH for recessive bus states) Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 FUNCTIONAL DESCRIPTION CAN BUS STATES The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a common mode of VCC / 2 via the high-resistance internal input resistors of the receiver, equivalent to a logic high. The host microprocessor of the CAN node will use the TXD pin to drive the bus and will receive data from the bus on the RXD pin. See Figure 1 and Figure 2. Typical Bus Voltage (V) Normal & Silent Mode 4 CANH 3 Vdiff(D) 2 Vdiff(R) CANL 1 Recessive Logic H Dominant Logic L Recessive Logic H Time, t Figure 1. Bus States (Physical Bit Representation) GALVANIC ISOLATION CANH VCC/2 RXD CANL Figure 2. Simplified Recessive Common Mode Bias and Receiver Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 3 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com DRIVER AND RECEIVER FUNCTION TABLES Table 1. Driver Function Table INPUT (1) OUTPUTS DRIVEN BUS STATE TXD (1) CANH (1) CANL (1) L H L Dominant H Z Z Recessive H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See Figure 1 and Figure 2 for bus state and common mode bias information. Table 2. Receiver Function Table DEVICE MODE Normal or Silent (1) CAN DIFFERENTIAL INPUTS VID = VCANH – VCANL BUS STATE RXD PIN (1) VID ≥ 0.9 V Dominant L 0.5 V < VID < 0.9 V ? ? VID ≤ 0.5 V Recessive H Open (VID ≈ 0 V) Open H H = high level, L = low level, ? = indeterminate. DIGITAL INPUTS AND OUTPUTS TXD (Input) and RXD (Output): VCC1 for the isolated digital input and output side of the device maybe supplied by a 3.3 V or 5 V supply and thus the digital inputs and outputs are 3.3 V and 5 V compatible. NOTE TXD is very weakly internally pulled up to VCC1. An external pull up resistor should be used to make sure that TXD is biased to recessive (high) level to avoid issues on the bus if the microprocessor doesn't control the pin and TXD floats. TXD pullup strength and CAN bit timing require special consideration when the device is used with an open-drain TXD output on the microprocessor's CAN controller. An adequate external pullup resistor must be used to ensure that the TXD output of the microprocessor maintains adequate bit timing input to the input on the transceiver. PROTECTION FEATURES TXD Dominant Timeout (DTO) TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the timeout period tTXD_DTO. The TXD DTO circuit timer starts on a falling edge on TXD. The TXD DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a recessive signal is seen on the TXD pin, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD dominant timeout. NOTE The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / tTXD_DTO. 4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 Fault is repaired and local node transmission capability restored TXD INPUT TXD fault stuck dominant: example PCB failure or bad software CAN BUS OUTPUT WITH TXD DTO TXD %XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ communication for the whole network but TXD DTO prevents this and frees the bus for communication after the time tTXD_DTO. Normal CAN communication CAN Bus Signal tTXD_DTO Communication from other network nodes Communication from repaired local node Figure 3. Example Timing Diagram for Devices With TXD DTO Thermal Shutdown If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the junction temperature drops below the thermal shutdown temperature of the device. If the fault condition is still present, the temperature may rise again and the device would enter thermal shut down again. Prolonged operation with thermal shutdown conditions may affect device reliability. NOTE During thermal shutdown the CAN bus drivers turn off; thus no transmission is possible from TXD to the bus. The CAN bus pins are biased to recessive level during a thermal shutdown, and the receiver to RXD path remains operational. Undervoltage Lockout and Failsafe The supply pins have undervoltage detection that places the device in protected or failsafe mode. This protects the bus during an undervoltage event on VCC1 or VCC2 supply pins. If the bus-side power supply Vcc2 is lower than about 2.7V, the power shutdown circuits in the ISO1050 will disable the transceiver to prevent false transmissions due to an unstable supply. If Vcc1 is still active when this occurs, the receiver output (RXD) will go to a failsafe HIGH (recessive) value in about 6 microseconds. Table 3. Undervoltage Lockout and Failsafe VCC1 VCC2 DEVICE STATE BUS OUTPUT RXD GOOD GOOD Functional Per Device State and TXD Mirrors Bus BAD GOOD Protected Recessive High Impedance (3-state) GOOD BAD Protected High Impedance Recessive (Failsafe High) NOTE After an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically resumes normal operation in 300 µs Floating Pins Pull ups and pull downs should be used on critical pins to place the device into known states if the pins float. The TXD pin should be pulled up via a resistor to VCC1 to force a recessive input level if the microprocessor output to the pin floats. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 5 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com CAN Bus Short Circuit Current Limiting The device has several protection features that limit the short circuit current when a CAN bus line is shorted. These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to prevent permanent higher short circuit current of the dominant state during a system fault. During CAN communication the bus switches between dominant and recessive states with the data and control fields bits, thus the short circuit current may be viewed either as the instantaneous current during each bus state, or as a DC average current. For system current (power supply) and power considerations in the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at certain times: • Control fields with set bits • Bit stuffing • Interframe space • TXD dominant time out (fault case limiting) These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits. NOTE The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents. The average short circuit current may be calculated with the following formula: IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC] Where • IOS(AVG) is the average short circuit current • %Transmit is the percentage the node is transmitting CAN messages • %Receive is the percentage the node is receiving CAN messages • %REC_Bits is the percentage of recessive bits in the transmitted CAN messages • %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages • IOS(SS)_REC is the recessive steady state short circuit current • IOS(SS)_DOM is the dominant steady state short circuit current NOTE Consider the short circuit current and possible fault cases of the network when sizing the power ratings of the termination resistance and other network components. 6 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) VALUE / UNIT (3) VCC1, VCC2 Supply voltage VI Voltage input (TXD) –0.5 V to 6 V VCANH or VCANH Voltage range at any bus terminal (CANH, CANL) –27 V to 40 V IO Receiver output current ESD –0.5 V to 6 V ±15 mA Bus pins and GND2 (4) ±4 kV All pins ±4 kV ±1.5 kV Human Body Model JEDEC Standard 22, Method A114-C.01 Charged Device Model JEDEC Standard 22, Test Method C101 All pins Machine Model ANSI/ESDS5.2-1996 All pins ±200 V Tstg Storage temperature –65°C to 150°C TJ Junction temperature –55°C to 150°C (1) (2) (3) (4) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This isolator is suitable for basic isolation within the safety limiting data. Maintenance of the safety data must be ensured by means of protective circuitry. All input and output logic voltage values are measured with respect to the GND1 logic side ground. Differential bus-side voltages are measured to the respective bus-side GND2 ground terminal. Tested while connected between Vcc2 and GND2. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX Supply voltage, controller side VCC2 Supply voltage, bus side VI or VIC Voltage at bus pins (separately or common mode) VIH High-level input voltage VIL Low-level input voltage VID Differential input voltage IOH High-level output current IOL Low-level output current TA Ambient Temperature –55 105 °C TJ Junction temperature (see THERMAL CHARACTERISTICS) –55 125 °C (1) 3 UNIT VCC1 5.5 V 5.25 V –12 (1) 12 V TXD 2 5.25 V TXD 0 0.8 V –7 7 V 4.75 Driver 5 –70 Receiver mA –4 Driver 70 Receiver 4 mA The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. SUPPLY CURRENT over recommended operating conditions (unless otherwise noted) PARAMETER ICC1 VCC1 Supply current ICC2 VCC2 Supply current (1) TEST CONDITIONS MIN TYP (1) MAX VI = 0 V or VCC1 , VCC1 = 3.3V 1.8 2.8 VI = 0 V or VCC1 , VCC1 = 5V 2.3 3.6 Dominant VI = 0 V, 60-Ω Load 52 73 Recessive VI = VCC1 8 12 UNIT mA mA All typical values are at 25°C with VCC1 = VCC2 = 5V. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 7 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com DEVICE SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tloop1 Total loop delay, driver input to receiver output, Recessive to Dominant See Figure 12 112 150 210 ns tloop2 Total loop delay, driver input to receiver output, Dominant to Recessive See Figure 12 112 150 210 ns DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VO(D) Bus output voltage (Dominant) VO(R) Bus output voltage (Recessive) VOD(D) TEST CONDITIONS CANH CANL Differential output voltage (Dominant) MIN TYP MAX 2.9 3.5 4.5 0.8 1.2 1.5 See Figure 4 and Figure 5, VI = 2 V, RL= 60Ω 2 2.3 3 See Figure 4, Figure 5 and Figure 6, VI = 0 V, RL = 60Ω 1.5 3 See Figure 4, Figure 5, and Figure 6 VI = 0 V, RL = 45Ω, Vcc > 4.8V 1.4 3 See Figure 4 and Figure 5, VI = 3 V, RL = 60Ω –0.12 0.012 –0.5 0.05 See Figure 4 and Figure 5, VI = 0 V, RL = 60Ω VOD(R) Differential output voltage (Recessive) VOC(D) Common-mode output voltage (Dominant) VOC(pp) Peak-to-peak common-mode output voltage IIH High-level input current, TXD input VI at 2 V IIL Low-level input current, TXD input VI at 0.8 V IO(off) Power-off TXD leakage current VCC1, VCC2 at 0 V, TXD at 5 V VI = 3 V, No Load 2.3 3 0.3 5 10 –105 See Figure 14, VCANH = 12 V, CANL Open IOS(ss) Short-circuit steady-state output current CO Output capacitance See receiver input capacitance CMTI Common-mode transient immunity See Figure 16, VI = VCC or 0 V See Figure 14, VCANL =–12 V, CANH Open V See Figure 14, VCANL = 12 V, CANH Open 1 –0.5 71 25 V μA μA –72 0.36 –1 V μA –5 See Figure 14, VCANH = –12 V, CANL Open V V 2 See Figure 11 UNIT mA 105 50 kV/μs DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, recessive-to-dominant output tPHL Propagation delay time, dominant-to-recessive output tr Differential output signal rise time tf tdom (1) 8 See Figure 7 MIN TYP MAX 31 74 110 25 44 75 20 50 Differential output signal fall time (1) Dominant time-out ↓ CL=100 pF, See Figure 13 300 20 50 450 700 UNIT ns μs The TXD dominant time out (tdom) disables the driver of the transceiver once the TXD has been dominant longer than (tdom) which releases the bus lines to recessive preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults locking the bus dominant it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case where five successive dominant bits are followed immediately by an error frame. This along with the (tdom) minimum limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ (tdom) = 11 bits / 300 µs = 37 kbps. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ Positive-going bus input threshold voltage VIT– Negative-going bus input threshold voltage Vhys Hysteresis voltage (VIT+ – VIT–) VOH High-level output voltage with Vcc = 5V VOH High-level output voltage with Vcc1 = 3.3V VOL Low-level output voltage CI TEST CONDITIONS See Table 4 MIN 500 TYP (1) MAX UNIT 750 900 mV 650 mV 150 mV IOH = –4 mA, See Figure 9 VCC – 0.8 4.6 IOH = –20 μA, See Figure 9 VCC – 0.1 5 IOL = 4 mA, See Figure 9 VCC – 0.8 3.1 IOL = 20 μA, See Figure 9 VCC – 0.1 3.3 V V IOL = 4 mA, See Figure 9 0.2 0.4 IOL = 20 μA, See Figure 9 0 0.1 Input capacitance to ground, (CANH or CANL) TXD at 3 V, VI = 0.4 sin (4E6πt) + 2.5V 6 CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) RID Differential input resistance TXD at 3 V 30 RIN Input resistance (CANH or CANL) TXD at 3 V 15 RI(m) Input resistance matching (1 – [RIN (CANH) / RIN (CANL)]) × 100% VCANH = VCANL CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 16 (1) V pF 3 pF 80 kΩ 30 40 kΩ –3% 0% 3% 25 50 kV/μs All typical values are at 25°C with VCC1 = VCC2 = 5V. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from bus-side power loss TXD at 3 V, See Figure 9 VCC1 at 5 V, See Figure 15 MIN TYP MAX 66 90 130 51 80 105 3 6 3 6 6 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 UNIT ns μs 9 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Dominant » 3.5 V IO(CANH) VO (CANH) CANH II 0 or Vcc1 Recessive TXD GND1 VOD CANL RL IO(CANL) GND2 » 2.5 V VO(CANH) + VO(CANL) 2 » 1.5 V VOC VO (CANL) VI VO(CANH) VO(CANL ) GND1 GND2 Figure 4. Driver Voltage, Current and Test Definitions Figure 5. Bus Logic State Voltage Definitions 330 W ±1% CANH 0V TXD VOD 60 W ±1% + _ CANL -2 V < V test < 7 V GND2 330 W ±1% Figure 6. Driver VOD with Common-mode Loading Test Circuit Vcc VI CANH TXD 60 W ±1% VO VI t PLH VO (SEE NOTE A) Vcc/2 0V CL = 100 pF ± 20% (SEE NOTE B) CANL Vcc/2 t PHL VO(D) 90% 0.9V 0.5V 10% tr tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50Ω. B. CL includes instrumentation and fixture capacitance within ±20%. VO(R) Figure 7. Driver Test Circuit and Voltage Waveforms CANH VIC = VI(CANH) + VI(CANL) 2 IO RXD VID CANL VI(CANH) VO VI(CANL) GND2 GND1 Figure 8. Receiver Voltage and Current Definitions 10 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 PARAMETER MEASUREMENT INFORMATION (continued) CANH IO 3.5 V RXD V I 2.4 V 2 V CANL 1.5 V t pHL t pLH VI CL = 15 pF ± 20 % (SEE NOTE B) VO (SEE NOTE A) 1 .5 V 0.3 Vcc 1 V O 10 % tf tr GND 2 V OH 90 % 0.7 Vcc 1 V OL GND 1 A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50Ω. B. CL includes instrumentation and fixture capacitance within ±20%. Figure 9. Receiver Test Circuit and Voltage Waveforms Table 4. Differential Input Voltage Threshold Test INPUT OUTPUT VCANH VCANL |VID| –11.1 V –12 V 900 mV L R 12 V 11.1 V 900 mV L –6 V –12 V 6V L 12 V 6V 6V L –11.5 V –12 V 500 mV H 12 V 11.5 V 500 mV H –12 V –6 V –6 V H 6V 12 V –6 V H Open Open X H 1 nF VOL VOH CANH RXD CANL 15 pF 1 nF TXD + VI _ GND2 GND1 The waveforms of the applied transients are in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, and 3b. Figure 10. Transient Over-Voltage Test Circuit Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 11 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com 27 W ±1 % CANH TXD CANL 47 nF VI 27 W ±1 % V OC ± 20% GND 1 = V (CANH) + V (CANL) O O 2 GND 2 V OC(pp) V OC Figure 11. Peak-to-Peak Output Voltage Test Circuit and Waveform CANH VI TXD 60 W ±1% Vcc TXD Input CANL 50% 0V tloop 2 RXD RXD Output + VO _ t loop1 50% VOH 50% VOL 15 pF ± 20% GND1 Figure 12. tLOOP Test Circuit and Voltage Waveforms Vcc VI CANH TXD RL= 60 W ± 1 % CL 0V VOD V OD (D) (see Note B ) (see Note A ) CANH VOD VI 900 mV 500 mV t dom GND 1 A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50Ω. B. CL includes instrumentation and fixture capacitance within ±20%. 0V Figure 13. Dominant Timeout Test Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 IOS (SS) I OS (P) I OS 15 s CANH TXD 0V 0 V or VCC 1 12 V CANL VI -12 V or 12 V VI 0V GND2 or 10 ms 0V VI -12 V Figure 14. Driver Short-Circuit Current Test Circuit and Waveforms VI VCC 2 CANH 0V TXD VCC2 CL 60 W ±1% VI VO RXD 0V t fs CANL + VO 2.7 V VOH 50% VOL 15pF ± 20% GND 1 NOTE: CL = 100pF includes instrumentation and fixture capacitance within ± 20%. Figure 15. Failsafe Delay Time Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 13 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com C = 0.1 mF ± 1% 2.0 V VCC 1 VCC2 CANH C = 0.1 mF ±1% GND2 GND1 TXD 60 W S1 VOH or VOL CANL 0.8 V RXD VOH or VOL 1 kW GND 1 GND 2 CL = 15 pF (includes probe and jig capacitance) V TEST Figure 16. Common-Mode Transient Immunity Test Circuit CANH ISO1050 47nF 30 W Spectrum Analyzer 6.2 kW 10 nF 30 W TXD 500kbps CANL 6.2 kW Figure 17. Electromagnetic Emissions Measurement Setup DEVICE INFORMATION FUNCTION TABLE (1) DRIVER INPUTS (1) (2) 14 OUTPUTS RECEIVER BUS STATE DIFFERENTIAL INPUTS VID = CANH–CANL OUTPUT RXD BUS STATE L DOMINANT VID ≥ 0.9 V L DOMINANT TXD CANH CANL L (2) H H Z Z RECESSIVE 0.5 V < VID < 0.9 V ? ? Open Z Z RECESSIVE VID ≤ 0.5 V H RECESSIVE X Z Z RECESSIVE Open H RECESSIVE H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance Logic low pulses to prevent dominant time-out. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 ISOLATOR CHARACTERISTICS (1) (2) over recommended operating conditions (unless otherwise noted) PARAMETER L(I01) TEST CONDITIONS Minimum air gap (Clearance) Shortest terminal to terminal distance through air, per JEDEC package dimensions L(I02) Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface, per JEDEC package dimensions L(I01) Minimum air gap (Clearance) Shortest terminal to terminal distance through air, per JEDEC package dimensions L(I02) RIO Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface, per JEDEC package dimensions Minimum Internal Gap (Internal Clearance) Distance through the insulation Isolation resistance MIN TYP MAX UNIT 6.1 mm 6.8 mm 8.34 mm 8.10 mm 0.014 mm DUB-8 DW-16 Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, Tamb < 100°C >1012 Ω Input to output VIO = 500 V, 100°C ≤Tamb ≤Tamb max >1011 Ω CIO Barrier capacitance VI = 0.4 sin (4E6πt) 1.9 pF CI Input capacitance to ground VI = 0.4 sin (4E6πt) 1.3 pF (1) (2) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. INSULATION CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIORM Maximum working insulation voltage per DIN EN 60747-5-2 VPR Input to output test voltage per DIN EN 60747-5-2 VIOTM Transient overvoltage per DIN EN 60747-5-2 TEST CONDITIONS 560 ISO1050DW 1200 ISO1050DUB VP R = 1.875 x VIORM, t = 1 sec (100% production) Partial discharge < 5 pC ISO1050DW t = 60 sec (qualification) t = 1 sec (100% production) ISO1050DUB - Double Protection VISO Isolation voltage per UL 1577 ISO1050DW - Single Protection RS SPECIFICATION ISO1050DUB Isolation resistance Vpeak 1050 Vpeak 2250 4000 t = 60 sec (qualification) 2500 t = 1 sec (100% production) 3000 t = 60 sec (qualification) 4243 t = 1 sec (100% production) 5092 VIO = 500 V at TS > 109 Pollution Degree UNIT Vpeak Vrms Vrms Ω 2 IEC 60664-1 RATINGS PARAMETER Basic isolation group Installation classification TEST CONDITIONS Material group SPECIFICATION II Rated mains voltage ≤ 150 Vrms I–IV Rated mains voltage ≤ 300 Vrms I–III Rated mains voltage ≤ 400 Vrms I–II Rated mains voltage ≤ 600 Vrms (ISO1050DW only) I-II Rated mains voltage ≤ 848 Vrms (ISO1050DW only) I Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 15 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com IEC SAFETY LIMITING VALUES safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS DUB-8 IS Safety input, output, or supply current DW-16 TS MIN TYP MAX UNIT θJA = 73.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 310 θJA = 73.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 474 θJA = 76 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 299 θJA = 76 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 457 Maximum case temperature mA mA 150 °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assured junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. REGULATORY INFORMATION VDE TUV CSA UL Certified according to DIN EN 60747-5-2 Certified according to EN/UL/CSA 60950-1 Approved under CSA Component Acceptance Notice #5A Recognized under 1577 (1) Component Recognition Program Basic Insulation Transient Overvoltage, 4000 VPK Surge Voltage, 4000 VPK Maximum Working Voltage, 1200 VPK (ISO1050DW) and 560 VPK (ISO1050DUB) ISO1050DW: 5000 VRMS Reinforced Insulation, 400 VRMS maximum working voltage 5000 VRMS Basic Insulation, 600 VRMS maximum working voltage ISO1050DUB: 2500 VRMS Reinforced Insulation, 400 VRMS maximum working voltage 2500 VRMS Basic Insulation, 600 VRMS maximum working voltage 5000 VRMS Reinforced Insulation 2 Means of Patient Protection at 125 VRMS per IEC 60601-1 (3rd Ed.) ISO1050DUB: 2500 VRMS Double Protection ISO1050DW: 3500 VRMS Double Protection, 4243 VRMS Single Protection File Number: 40016131 Certificate Number: U8V 11 09 77311 008 File Number: 220991 File Number: E181974 (1) Production tested ≥ 3000 VRMS (ISO1050DUB) and 5092 VRMS (ISO1050DW) for 1 second in accordance with UL 1577. THERMAL INFORMATION (DUB-8 PACKAGE) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K Thermal Resistance (1) 120 °C/W High-K Thermal Resistance 73.3 °C/W θJA Junction-to-air θJB Junction-to-board thermal resistance Low-K Thermal Resistance 10.2 °C/W θJC Junction-to-case thermal resistance Low-K Thermal Resistance 14.5 °C/W PD Device power dissipation Tj shutdown Thermal shutdown temperature (2) (1) (2) 16 VCC1= 5.5V, VCC2= 5.25V, TA=105°C, RL= 60Ω, TXD input is a 500kHz 50% duty-cycle square wave 200 190 mW °C Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. Extended operation in thermal shutdown may affect device reliability. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 THERMAL INFORMATION (DW-16 PACKAGE) ISO1050 THERMAL METRIC (1) DW UNITS 16 θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance 47.7 ψJT Junction-to-top characterization parameter 14.4 ψJB Junction-to-board characterization parameter 38.2 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) 76.0 41 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. LIFE EXPECTANCY vs WORKING VOLTAGE (ISO1050DUB) Life Expectancy – Years 100 VIORM at 560 V 28 Years 10 0 120 250 500 750 880 1000 VIORM – Working Voltage – V G001 Figure 18. Life Expectancy vs Working Voltage Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 17 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com EQUIVALENT I/O SCHEMATICS TXD Input VCC1 RXD Output VCC1 VCC1 VCC1 1 MW IN 8W 500 W OUT 13 W CANL Input CANH Input Vcc2 Vcc2 10 kW 10 kW 20 kW 20 kW Input Input 10 kW 10 kW CANH and CANL Outputs Vcc2 CANH CANL 18 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS RECESSIVE-TO-DOMINANT LOOP TIME vs FREE-AIR TEMPERATURE (across Vcc) DOMINANT-TO-RECESSIVE LOOP TIME vs FREE-AIR TEMPERATURE (across Vcc) 163 200 161 VCC1 = 3 V, VCC2 = 4.75 V 190 159 VCC1 = 3 V, VCC2 = 4.75 V 157 Loop Time - ns Loop Time - ns 180 VCC1 = 5 V, VCC2 = 5 V 170 160 155 VCC1 = 5.5 V, VCC2 = 5.25 V 153 151 149 150 140 -60 VCC1 = 5.5 V, VCC2 = 5.25 V -40 147 VCC1 = 5 V, VCC2 = 5 V 145 -60 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C Figure 19. Figure 20. SUPPLY CURRENT (RMS) vs SIGNALING RATE (kbps) DRIVER OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 100 3.5 VO = CANH 3 VO - Output Voltage - V ICC - Supply Current - mA ICC2 = 5 V 10 ICC1 = 5 V 1 250 450 550 650 750 850 2 1.5 ICC1 = 3.3 V 350 2.5 950 1 -60 Signaling Rate - kbps Figure 21. VO = CANL -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C Figure 22. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 19 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 20 EMISSIONS SPECTRUM TO 10 MHz EMISSIONS SPECTRUM TO 50 MHz Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 APPLICATION INFORMATION SN6501 GND2 D2 VCC 4 8 3 2 7 6 TPS76350 1 IN OUT 3 2 1 D1 GND1 5 5 EN GND NC 4 ISO1050 1 2 4 3 Vdd L1 N RXD 3.3V TXD MCU PSU PE 0V 5 6 7 8 VCC1 VCC2 16 GND1 NC RXD NC CANH NC CANL TXD NC 14 13 12 11 15 GND1 GND1 GND2 Optional Bus protection function 9,10 DGND Protective Earth Chasis Ground Digital Ground Galvanic Isolation Barrier ISO Ground Figure 25. Application Circuit BUS LOADING, LENGTH AND NUMBER OF NODES The ISO11898 Standard specifies a maximum bus length of 40m and maximum stub length of 0.3m with a maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as the ISO1050. Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO11898 standard. They have made system level trade offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and NMEA200. A CAN network design is a series of tradeoffs, but these devices operate over wide –12-V to 12-V commonmode range. In ISO11898-2 the driver differential output is specified with a 60Ω load (the two 120Ω termination resistors in parallel) and the differential output must be greater than 1.5V. The ISO1050 is specified to meet the 1.5V requirement with a 60Ω load, and additionally specified with a differential output of 1.4V with a 45Ω load. The differential input resistance of the ISO1050 is a minimum of 30KΩ. If 167 ISO1050 transceivers are in parallel on a bus, this is equivalent to a 180Ω differential load. That transceiver load of 180Ω in parallel with the 60Ω gives a total 45Ω. Therefore, the ISO1050 theoretically supports over 167 transceivers on a single bus segment with margin to the 1.2V minimum differential input at each node. However for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much lower. Bus length may also be extended beyond the original ISO11898 standard of 40m by careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate. This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the responsibility of good network design. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 21 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com CAN TERMINATION The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with 120Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that it is not removed from the bus. Node n (with termination) Node 1 Node 2 Node 3 MCU or DSP MCU or DSP MCU or DSP CAN Controller CAN Controller CAN Controller CAN Transceiver CAN Transceiver CAN Transceiver MCU or DSP CAN Controller CAN Transceiver RTERM RTERM Figure 26. Typical CAN Bus Termination may be a single 120 Ω resistor at the end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used. (See Figure 27). Split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions. Standard Termination Split Termination CANH CANH RTERM/2 CAN CAN Transceiver RTERM Transceiver CSPLIT RTERM/2 CANL CANL Figure 27. CAN Bus Termination Concepts 22 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 ISO1050 www.ti.com SLLS983H – JUNE 2009 – REVISED JUNE 2013 REVISION HISTORY Changes from Original (June 2009) to Revision A Page • Added Typical 25-Year Life at Rated Working Voltage to Features ..................................................................................... 1 • Added LIFE EXPECTANCY vs WORKING VOLTAGE section .......................................................................................... 17 Changes from Revision A (Sept 2009) to Revision B Page • Added information that IEC 60747-5-2 and IEC61010-1 have been approved .................................................................... 1 • Changed DW package from preview to production data ...................................................................................................... 1 • Added Insulation Characteristics and IEC 60664-1 Ratings tables .................................................................................... 15 • Added IEC file number ........................................................................................................................................................ 16 • Added DW-16 thermal information table ............................................................................................................................. 17 Changes from Revision B (June 2009) to Revision C Page • Changed the IEC 60747-5-2 Features bullet From: DW package Approval Pending To: VDE approved for both DUB and DW packages ................................................................................................................................................................ 1 • Changed the Minimum Internal Gap value from 0.008 to 0.014 in the Isolator Characteristics table ................................ 15 • Changed VIORM Specification From: 1300 To: 1200 per VDE certification ......................................................................... 15 • Changed VPR Specification From 2438 To: 2250 ............................................................................................................... 15 • Added the Bus Loading paragraph to the Application Information section ......................................................................... 21 Changes from Revision C (July 2010) to Revision D Page • Changed the SUPPLY CURRENT table for ICC1 1st row From: Typ = 1 To: 1.8 and MAX = 2 To: 2.8 ............................... 7 • Changed the SUPPLY CURRENT table for ICC1 2nd row From: Typ = 2 To: 2.8 and MAX = 3 To: 3.6 .............................. 7 • Changed the REGULATORY INFORMATION table .......................................................................................................... 16 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 23 ISO1050 SLLS983H – JUNE 2009 – REVISED JUNE 2013 www.ti.com Changes from Revision D (June 2011) to Revision E Page • Added device ISO1050L ....................................................................................................................................................... 1 • Changed (DW Package) in the Features list to (ISO1050DW) ............................................................................................ 1 • Changed (DUB Package) in the Features list to (ISO1050DUB and ISO1050LDW) ........................................................... 1 • Deleted IEC 60950-1 from the CSA Approvals Feature bullet ............................................................................................. 1 • From: IEC 60601-1 (Medical) and CSA Approvals Pending To: IEC 60601-1 (Medical) and CSA Approved ..................... 1 • Added Feature - 5 KVRMS Reinforced.. .............................................................................................................................. 1 • Changed DW Package to ISO105DW and DUB package to ISO1050DUB and ISO1050LDW in the first paragraph of DESCRIPTION ................................................................................................................................................................. 1 • Added the AVAILABLE OPTIONS table ............................................................................................................................... 2 • Added Note 1 to the INSULATION CHARACTERISTICS table ......................................................................................... 15 • Changed VIORM From: 8-DUB Package to ISO1050DUB and ISO1050LDW ..................................................................... 15 • Changed VIORM From: 16-DW to ISO1050DW .................................................................................................................... 15 • Changed the VISO Isolation voltage per UL section of the INSULATION CHARACTERISTICS table. .............................. 15 • Changed the IEC 60664-1 Ratings Table ........................................................................................................................... 15 • Changed the REGULATORY INFORMATION table .......................................................................................................... 16 • Changed From: File Number: 220991 (Approval Pending) To: File Number: 220991 ....................................................... 16 • Changed in note (1) 3000 to 2500 and 6000 to 5000 ........................................................................................................ 16 • Changed in LIFE EXPECTANCY vs WORKING VOLTAGE (8-DUB PACKAGE TO: LIFE.....(ISO1050DW and ISO1050LDW) ..................................................................................................................................................................... 17 Changes from Revision E (December 2011) to Revision F Page • Deleted ISO1050L device ..................................................................................................................................................... 1 • Deleted ISO1050LDW from Features list ............................................................................................................................. 1 • Deleted ISO1050LDW in first paragraph of DESCRIPTION ................................................................................................ 1 • Deleted ISO1050LDW from AVAILABLE OPTIONS ............................................................................................................ 2 • Added the PIN FUNCTIONS section .................................................................................................................................... 2 • Added the FUNCTIONAL DESCRIPTION section ............................................................................................................... 3 • Added Note 1 to the DRIVER SWITCHING CHARACTERISTICS table ............................................................................. 8 • Deleted ISO1050LDW from INSULATION CHARACTERISTICS ...................................................................................... 15 • Deleted ISO1050LDW from REGULATORY INFORMATION ............................................................................................ 16 • Deleted ISO1050LDW from LIFE EXPECTANCY vs WORKING VOLTAGE ..................................................................... 17 • Deleted 40V from the CANH and CANL input diagrams and output diagrams in the EQUIVALENT I/O SCHEMATICS .................................................................................................................................................................... 18 • Changed the APPLICATION INFORMATION section ........................................................................................................ 21 Changes from Revision F (January 2013) to Revision G Page • Clarified clearance and creepage measurement method in ISOLATOR CHARACTERISTICS ......................................... 15 • Clarified test methods for voltage ratings in INSULATION CHARACTERISTICS .............................................................. 15 • Changed UL Single Protection Certification pending to Single Protection in REGULATORY INFORMATION SECTION (certificate available) .......................................................................................................................................... 16 Changes from Revision G (March 2013) to Revision H • 24 Page Changed title From: LIFE EXPECTANCY vs WORKING VOLTAGE (ISO1050DW To: LIFE EXPECTANCY vs WORKING VOLTAGE (ISO1050DUB) ............................................................................................................................... 17 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ISO1050 PACKAGE OPTION ADDENDUM www.ti.com 3-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) ISO1050DUB ACTIVE SOP DUB 8 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -55 to 105 ISO1050 ISO1050DUBR ACTIVE SOP DUB 8 350 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -55 to 105 ISO1050 ISO1050DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 105 ISO1050 ISO1050DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 105 ISO1050 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO1050DUBR SOP DUB 8 350 330.0 24.4 10.9 10.01 5.85 16.0 24.0 Q1 ISO1050DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing ISO1050DUBR SOP DUB ISO1050DWR SOIC DW Pins SPQ Length (mm) Width (mm) Height (mm) 8 350 358.0 335.0 35.0 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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