DATASHEET

ISL6441
®
Data Sheet
May 26, 2009
1.4MHz Dual, 180° Out-of-Phase,
Step-Down PWM and Single Linear
Controller
Features
The ISL6441 is a high-performance, triple-output controller
optimized for converting wall adapter, battery or network
intermediate bus DC input supplies into the system supply
voltages required for a wide variety of applications. Each
output is adjustable down to 0.8V. The two PWMs are
synchronized 180° out-of-phase reducing the RMS input
current and ripple voltage.
The ISL6441 incorporates several protection features. An
adjustable overcurrent protection circuit monitors the output
current by sensing the voltage drop across the lower
MOSFET. Hiccup mode overcurrent operation protects the
DC/DC components from damage during output
overload/short circuit conditions. Each PWM has an
independent logic-level shutdown input (SD1 and SD2).
A single PGOOD signal is issued when soft-start is complete
on both PWM controllers and their outputs are within 10% of
the set point and the linear regulator output is greater than
75% of its setpoint. Thermal shutdown circuitry turns off the
device if the junction temperature exceeds +150°C.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
ISL6441IRZ* ISL 6441IRZ
TEMP.
RANGE
(°C)
FN9197.3
• Wide Input Supply Voltage Range
- 5.6V to 24V
- 4.5V to 5.6V
• Three Independently Programmable Output Voltages
• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .1.4MHz
• Out-of-Phase PWM Controller Operation
- Reduces Required Input Capacitance and Power
Supply Induced Loads
• No External Current Sense Resistor
- Uses Lower MOSFET’s rDS(ON)
• Bi-directional Frequency Synchronization for
Synchronizing Multiple ISL6441s
• Programmable Soft-Start
• Extensive Circuit Protection Functions
- PGOOD
- UVLO
- Overcurrent
- Over-temperature
- Independent Shutdown for Both PWMs
• Excellent Dynamic Response
- Voltage Feed-Forward with Current Mode Control
PACKAGE
(Pb-Free)
-40 to +85 28 Ld QFN
PKG.
DWG. #
L28.5x5
*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
• QFN Package:
- QFN - Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip-Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies with Multiple Outputs
• xDSL Modems/Routers
• DSP, ASIC, and FPGA Power Supplies
• Set-Top Boxes
• Dual Output Supplies for DSP, Memory, Logic, µP Core
and I/O
• Telecom Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6441
Pinout
2
UGATE2
BOOT2
LGATE2
LGATE1
BOOT1
UGATE1
PHASE1
ISL6441
(28 LD QFN)
TOP VIEW
28
27
26
25
24
23
22
3
19 SD1
VCC_5V
4
18 SS1
SD2
5
17 SGND
SS2
6
16 OCSET1
OCSET2
7
15 FB1
8
9
10
11
12
13
14
SGND
PGOOD
GATE3
20 PGND
FB3
2
SYNC
ISEN2
VIN
21 ISEN1
SGND
1
FB2
PHASE2
FN9197.3
May 26, 2009
Block Diagram
BOOT1
PGOOD
VIN
SD1
SD2
SGND
BOOT2
VCC
UGATE2
UGATE1
PHASE2
PHASE1
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
VCC_5V
VCC
LGATE1
LGATE2
PGND
3
POR
PGND
ENABLE
0.8V REFERENCE
+
GATE3
BIAS SUPPLIES
+
VE
REFERENCE
-
gm*VE
FAULT LATCH
FB3
SOFT-START
UV
PGOOD
OC1
16kΩ
OC2
16kΩ
PWM1
-
PWM2
-
SOFT2
+
+
ERROR AMP 1
+ 0.8V
REF
+
+
ERROR AMP 2
SS1
+
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
ISEN1
+
0.8V
REF
ISEN2
-
CURRENT
SAMPLE
VSEN2
180kΩ
-
-
CURRENT
SAMPLE
CURRENT
SAMPLE
CURRENT
SAMPLE
+
OCSET2
OCSET1
+
0.8V REFERENCE
0.8V REFERENCE
-
OC1
OC2
+
+
VIN
FN9197.3
May 26, 2009
SAME STATE FOR
2 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
-
VCC
SAME STATE FOR
2 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
+
ISL6441
180kΩ
800kΩ
18.5pF
18.5pF
800kΩ
FB1
UV
PGOOD
Typical Application Schematic
+12V
R15
5.1
C35
56µF
R16
5.1
GND
4
C6
1µF
D1
BAT54HT1 R12
10k
+1.2V, 2A
C31
150µF
Q1B
FDS6990S
R7
1.5k
GND
R1
4.02k
23
22
21
25
20
15
14
29
UGATE1
PHASE1
ISEN1
LGATE1
PGND
FB1
SGND
SGND
U1
ISL6441IRZ
UGATE2
PHASE2
ISEN2
LGATE2
FB2
SGND
SD2
28
1
2
26
8
9
5
R2
8.05k
Q2A
C21
10µF
R9
1.5k
+3.3V, 2A
Q2B
FDS6990S
SD2
SD1
R5
120k
R10
120k
C30
150µF
C8
0.1uF
GND
C3
0.01µF
C11
1nF
R4
10k
C4
0.1µF
C2
0.01µF
L2
3.3µH
R3
31.6k
19
18
16
12
13
7
6
C10
1nF
C5
0.1uF
R8
100
Q3
IRF7404
C36
10uF
+2.5V, 2A
C37
47µF
C33
0.1µF
GND
R11
2k
R6
1k
ISL6441
C9
0.1µF
C20
10uF
BOOT1
PGOOD
SYNC
SGND
VIN
VCC_5V
BOOT2
L1
3.3µH
C7
0.1µF
R17
5.1
24
3
11
17
10
4
27
Q1A
C1
4.7µF
PGOOD
SD1
SS1
OCSET1
FB3
GATE3
OCSET2
SS2
R13
5.1
D2
BAT54HT1
FN9197.3
May 26, 2009
ISL6441
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Input Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V
BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V
PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V
BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V
UGATE1, 2. . . . . . . . . . . .(PHASE1, 2 - 0.3V) to (BOOT1, 2 + 0.3V)
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
28 Lead QFN (Notes 1, 2) . . . . . . . .
34
5
Maximum Junction Temperature (Plastic Package) -55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical
Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C, Typical
values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5.6
12
24
V
VIN SUPPLY
Input Voltage Range
VCC_5V SUPPLY (Note 3)
Input Voltage
VIN = VCC_5V
4.5
5.0
5.6
V
Output Voltage
VIN > 5.6V, IL = 20mA
4.5
5.0
5.5
V
Maximum Output Current
VIN = 12V
60
-
-
mA
-
50
375
µA
-
2.0
4.0
mA
-
0.8
-
V
-1.0
-
1.0
%
Rising VCC_5V Threshold
4.25
4.45
4.5
V
Falling VCC_5V Threshold
3.95
4.2
4.4
V
1.25
1.4
1.55
MHz
VIN = 12V
-
1.5
-
V
VIN = 5V
-
0.625
-
V
Ramp Offset (Note 7)
-
1.0
-
V
SYNC Input Rise/Fall Time (Note 7)
-
-
10.0
ns
SYNC Frequency Range
5.1
5.6
6.2
MHz
SYNC Input HIGH Level
3.5
-
-
V
SYNC Input LOW Level
-
-
1.5
V
10
-
-
ns
VCC - 0.6V
-
-
V
SUPPLY CURRENT
SD1 = SD2 = GND
Shutdown Current (Note 4)
Operating Current (Note 5)
REFERENCE SECTION
Nominal Reference Voltage
Reference Voltage Tolerance
POWER-ON RESET
OSCILLATOR
Total Frequency Variation
Peak-to-Peak Sawtooth Amplitude (Note 6)
SYNC Input Minimum Pulse Width (Note 7)
SYNC Output HIGH Level
5
FN9197.3
May 26, 2009
ISL6441
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical
Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C, Typical
values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
2.0
-
-
V
-
-
0.8
V
Output Voltage
-
0.8
-
V
FB Pin Bias Current
-
-
150
nA
PWM1, COUT = 1000p, TA = +25°C
71
-
-
%
PWM2, COUT = 1000pF,
TA = +25°C
73
-
-
%
-
4
-
%
DC Gain (Note 7)
80
88
-
dB
Gain-Bandwidth Product (Note 7)
5.9
-
-
MHz
-
2.0
-
V/µs
Maximum Output Voltage (Note 7)
0.9
-
-
V
Minimum Output Voltage (Note 7)
-
-
3.6
V
-
400
-
mA
SHUTDOWN1/SHUTDOWN2
HIGH Level (Converter Enabled)
Internal Pull-up (3µA)
LOW Level (Converter Disabled)
PWM CONVERTERS
Maximum Duty Cycle
Minimum Duty Cycle
PWM CONTROLLER ERROR AMPLIFIERS
Slew Rate (Note 7)
PWM CONTROLLER GATE DRIVERS (Note 8)
Sink/Source Current
Upper Drive Pull-Up Resistance
VCC_5V = 4.5V
-
8
-
Ω
Upper Drive Pull-Down Resistance
VCC_5V = 4.5V
-
3.2
-
Ω
Lower Drive Pull-Up Resistance
VCC_5V = 4.5V
-
8
-
Ω
Lower Drive Pull-Down Resistance
VCC_5V = 4.5V
-
1.8
-
Ω
Rise Time
COUT = 1000pF
-
18
-
ns
Fall Time
COUT = 1000pF
-
18
-
ns
50
-
-
mA
LINEAR CONTROLLER
Drive Sink Current
FB3 Feedback Threshold
I = 21mA
-
0.8
-
V
Undervoltage Threshold
VFB
-
75
-
%
-
45
150
nA
VFB = 0.8V, I = 21mA
-
2
-
A/V
Pull-up = 100kΩ
-
0.1
0.5
V
-
-
±1.0
µA
FB3 Input Leakage Current
Amplifier Transconductance
POWER GOOD AND CONTROL FUNCTIONS
PGOOD LOW Level Voltage
PGOOD Leakage Current
PGOOD Upper Threshold, PWM 1 and 2
Fraction of set point
105
-
120
%
PGOOD Lower Threshold, PWM 1 and 2
Fraction of set point
80
-
95
%
70
75
80
%
PGOOD for Linear Controller
6
FN9197.3
May 26, 2009
ISL6441
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical
Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C, Typical
values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
32
-
µA
-
64
-
µA
-
1.75
-
V
-
5
-
µA
Rising
-
150
-
°C
Hysteresis
-
20
-
°C
ISEN and CURRENT LIMIT
Full Scale Input Current (Note 9)
ROCSET = 110kΩ
Overcurrent Threshold (Note 9)
OCSET (Current Limit) Voltage
SOFT-START
Soft-Start Current
PROTECTION
Thermal Shutdown
NOTES:
3. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min).
When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the
VCC_5V pin. (Refer to the “Pin Descriptions” on page 10 for more details.)
4. This is the total shutdown current with VIN = VCC_5V = PVCC = 5V.
5. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current.
6. The peak-to-peak sawtooth amplitude is production tested at 12V only
7. Limits should be considered typical and are not production tested.
8. Limits established by characterization and are not production tested.
9. Established by characterization. The full scale current of 32µA is recommended for optimum current sample and hold operation. See the
“Feedback Loop Compensation” on page 13.
7
FN9197.3
May 26, 2009
ISL6441
Oscilloscope plots are taken using the ISL6441AEVAL Evaluation Board, VIN = 12V, Unless
Otherwise Noted.
3.40
3.40
3.39
3.39
PWM2 OUTPUT VOLTAGE (V)
PWM1 OUTPUT VOLTAGE (V)
Typical Performance Curves
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.5
0
LOAD CURRENT (A)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
FIGURE 1. PWM1 LOAD REGULATION
FIGURE 2. PWM2 LOAD REGULATION
PGOOD 5V/DIV
REFERENCE VOLTAGE (V)
0.85
0.84
VOUT3 2V/DIV
0.83
0.82
0.81
VOUT2 2V/DIV
0.80
0.79
0.78
0.77
VOUT1 2V/DIV
0.76
0.75
-40
-20
20
40
0
TEMPERATURE (°C)
60
80
FIGURE 3. REFERENCE VOLTAGE VARIATION OVER
TEMPERATURE
FIGURE 4. SOFT-START WAVEFORMS WITH PGOOD
VOUT2 20mV/DIV, AC COUPLED
VOUT1 20mV/DIV, AC COUPLED
IL2 0.5A/DIV, AC COUPLED
IL1 0.5A/DIV, AC COUPLED
PHASE1 10V/DIV
PHASE2 10V/DIV
FIGURE 5. PWM1 WAVEFORMS
8
FIGURE 6. PWM2 WAVEFORMS
FN9197.3
May 26, 2009
ISL6441
Typical Performance Curves
Oscilloscope plots are taken using the ISL6441AEVAL Evaluation Board, VIN = 12V, Unless
Otherwise Noted. (Continued)
VOUT1 200mV/DIV
AC COUPLED
VOUT2 200mV/DIV
AC COUPLED
IOUT1 1A/DIV
IOUT2 1A/DIV
FIGURE 7. LOAD TRANSIENT RESPONSE VOUT1 (3.3V)
FIGURE 8. LOAD TRANSIENT RESPONSE VOUT2 (3.3V)
VOUT1 2V/DIV
VCC_5V 1V/DIV
IL1 2A/DIV
SS1 2V/DIV
VOUT1 1V/DIV
FIGURE 9. PWM SOFT-START WAVEFORM
FIGURE 10. OVERCURRENT HICCUP MODE OPERATION
100
PWM2 EFFICIENCY (%)
PWM1 EFFICIENCY (%)
100
90
80
70
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
LOAD CURRENT (A)
FIGURE 11. PWM1 EFFICIENCY vs LOAD, VIN = 5V,
VOUT = 3.3V
9
4.0
90
80
70
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
LOAD CURRENT (A)
FIGURE 12. PWM2 EFFICIENCY vs LOAD, VIN = 5V,
VOUT = 3.3V
FN9197.3
May 26, 2009
ISL6441
Pin Descriptions
BOOT2, BOOT1 - These pins power the upper MOSFET
drivers of each PWM converter. Connect this pin to the
junction of the bootstrap capacitor (CBOOT) and the
cathode of the bootstrap diode. The anode of the bootstrap
diode is connected to the VCC_5V pin. It’s highly
recommended to add a 5.1Ω resistor in series with CBOOT
and another 5.1Ω resistor in series with the bootstrap diode
to prevent the overcharge of CBOOT which may cause
overvoltage failure between BOOT and PHASE pin (Figure
15). Refer to “Gate Drivers” on page 12 for detailed
descriptions.
UGATE2, UGATE1 - These pins provide the gate drive for
the upper MOSFETs.
PHASE2, PHASE1 - These pins are connected to the
junction of the upper MOSFET’s source, output filter inductor
and lower MOSFETs drain. A small RC snubber is
suggested to be added at the phase node of the MOSFETs
to improve the system EMI performance. A typical snubber
suggested is 2.2W and 680pF.
side gate drivers, and the external boot circuitry for the high
side gate drivers. The IC may be powered directly from a
single 5V (±10%) supply at this pin. When used as a 5V
supply input, this pin must be externally connected to VIN.
The VCC_5V pin must be always decoupled to power
ground with a minimum of 4.7µF ceramic capacitor, placed
very close to the pin.
SYNC - This pin may be used to synchronize two or more
ISL6441 controllers. This pin requires a 1k resistor to ground
if used; connect directly to VCC_5V if not used.
SS1, SS2 - These pins provide a soft-start function for their
respective PWM controllers. When the chip is enabled, the
regulated 5µA pull-up current source charges the capacitor
connected from this pin to ground. The error amplifier
reference voltage ramps from 0V to 0.8V while the voltage
on the soft-start pin ramps from 0V to 0.8V.
SD1, SD2 - These pins provide an enable/disable function
for their respective PWM output. The output is enabled when
this pin is floating or pulled HIGH, and disabled when the pin
is pulled LOW.
LGATE2, LGATE1 - These pins provide the gate drive for
the lower MOSFETs.
GATE3 - This pin is the open drain output of the linear
regulator controller.
PGND - This pin provides the power ground connection for
the lower gate drivers for both PWM1 and PWM2. This pin
should be connected to the sources of the lower MOSFETs
and the (-) terminals of the external input capacitors.
OCSET2, OCSET1 - A resistor from this pin to ground sets
the overcurrent threshold for the respective PWM.
FB3, FB2, FB1 - These pins are connected to the feedback
resistor divider and provide the voltage feedback signals for
the respective controller. They set the output voltage of the
converter. In addition, the PGOOD circuit uses these inputs
to monitor the output voltage status.
Functional Description
General Description
ISEN2, ISEN1 - These pins are used to monitor the voltage
drop across the lower MOSFET for current loop feedback
and overcurrent protection.
The ISL6441 integrates control circuits for two synchronous
buck converters and one linear controller. The two
synchronous bucks operate out-of-phase to substantially
reduce the input ripple and thus reduce the input filter
requirements. The chip has four control lines (SS1, SD1,
SS2, and SD2), which provide independent control for each
of the synchronous buck outputs.
PGOOD - This is an open drain logic output used to indicate
the status of the output voltages. This pin is pulled low when
either of the two PWM outputs is not within 10% of the
respective nominal voltage, or if the linear controller output is
less than 75% of it’s nominal value.
The buck PWM controllers employ a free-running frequency
of 1.4MHz. The current mode control scheme with an input
voltage feed-forward ramp input to the modulator provides
excellent rejection of input voltage variations and provides
simplified loop compensations.
SGND - This is the small-signal ground, common to all 3
controllers, and must be routed separately from the high
current ground (PGND). All voltage levels are measured with
respect to this pin. Connect the additional SGND pins to this
pin. A small ceramic capacitor should be connected right
next to this pin for noise decoupling.
The linear controller can drive either a PNP or PFET to
provide ultra low-dropout regulation with programmable
voltages.
VIN - Use this pin to power the device with an external
supply voltage with a range of 5.6V to 24V. For 5V ±10%
operation, connect this pin to VCC_5V.
VCC_5V - This pin is the output of the internal 5V linear
regulator. This output supplies the bias for the IC, the low
10
Internal 5V Linear Regulator (VCC_5V)
All ISL6441 functions are internally powered from an
on-chip, low dropout 5V regulator. The maximum regulator
input voltage is 24V. Bypass the regulator’s output
(VCC_5V) with a 4.7µF capacitor to ground. The dropout
voltage for this LDO is typically 600mV, so when VCC_5V is
greater than 5.6V, VCC_5V is typically 5V. The ISL6441 also
employs an undervoltage lockout circuit that disables both
regulators when VCC_5V falls below 4.4V.
FN9197.3
May 26, 2009
ISL6441
The internal LDO can source over 60mA to supply the IC,
power the low side gate drivers, charge the external boot
capacitor and supply small external loads. When driving
large FETs especially at 1.4MHz frequency, little or no
regulator current may be available for external loads.
CSS1/CSS2 = 1.2/3.3 = 0.364. Figure 14 shows that soft-start
waveform with CSS1 = 0.01µF and CSS2 = 0.027µF.
For example, a single large FET with 15nC total gate charge
requires 15nC x 1.4MHz = 21mA. Also, at higher input
voltages with larger FETs, the power dissipation across the
internal 5V will increase. Excessive dissipation across this
regulator must be avoided to prevent junction temperature
rise. Larger FETs can be used with 5V ±10% input
applications. The thermal overload protection circuit will be
triggered if the VCC_5V output is short circuited. Connect
VCC_5V to VIN for 5V ±10% input applications.
VOUT2 1V/DIV
VOUT1 1V/DIV
Soft-Start Operation
When soft-start is initiated, the voltage on the SS pin of the
enabled PWM channels starts to ramp gradually, due to the
5µA current sourced into the external capacitor. The output
voltage follows the soft-start voltage.
When the SS pin voltage reaches 0.8V, the output voltage of
the enabled PWM channel reaches the regulation point, and
the soft-start pin voltage continues to rise. At this point the
PGOOD and fault circuitry is enabled. This completes the
soft-start sequence. Any further rise of SS pin voltage does
not affect the output voltage. By varying the values of the
soft-start capacitors, it is possible to provide sequencing of the
main outputs at start-up. The soft-start time can be obtained
from Equation 1:
C SS
T SOFT = 0.8V ⎛ -----------⎞
⎝ 5μA⎠
(EQ. 1)
VCC_5V 1V/DIV
VOUT1 1V/DIV
SS1 1V/DIV
FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING
START-UP
Output Voltage Programming
A resistive divider from the output to ground sets the output
voltage of either PWM channel. The center point of the
divider shall be connected to FBx pin. The output voltage
value is determined by Equation 2.
⎛ R 1 + R 2⎞
V OUTx = 0.8V ⎜ ---------------------⎟
⎝ R2 ⎠
(EQ. 2)
where R1 is the top resistor of the feedback divider network
and R2 is the resistor connected from FBx to ground.
Out-of-Phase Operation
The two PWM controllers in the ISL6441 operate 180°
out-of-phase to reduce input ripple current. This reduces the
input capacitor ripple current requirements, reduces power
supply-induced noise, and improves EMI. This effectively
helps to lower component cost, save board space and
reduce EMI.
Dual PWMs typically operate in-phase and turn on both
upper FETs at the same time. The input capacitor must then
support the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current. The higher RMS ripple current lowers
the efficiency due to the power loss associated with the ESR
of the input capacitor. This typically requires more low-ESR
capacitors in parallel to minimize the input voltage ripple and
ESR-related losses, or to meet the required ripple current
rating.
FIGURE 13. SOFT-START OPERATION
The soft-start capacitors can be chosen to provide start-up
tracking for the two PWM outputs. This can be achieved by
choosing the soft-start capacitors such that the soft-start
capacitor ration equals the respective PWM output voltage
ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V
then the soft-start capacitor ration should be,
11
With dual synchronized out-of-phase operation, the
high-side MOSFETs of the ISL6441 turn on 180°
out-of-phase. The instantaneous input current peaks of both
regulators no longer overlap, resulting in reduced RMS
ripple current and input voltage ripple. This reduces the
required input capacitor ripple current rating, allowing fewer
or less expensive capacitors, and reducing the shielding
FN9197.3
May 26, 2009
ISL6441
requirements for EMI. The typical operating curves show the
synchronized 180° out-of-phase operation.
Input Voltage Range
The ISL6441 is designed to operate from input supplies
ranging from 4.5V to 24V. However, the input voltage range
can be effectively limited by the available maximum duty
cycle (DMAX = 71%).
V OUT + V d1
V IN ( min ) = ⎛ --------------------------------⎞ + V d2 – V d1
⎝
⎠
0.71
be too big. RBOOT2 only functions solely to prevent the
overcharge of CBOOT. While the RBOOT1 and RBOOT2
will introduce voltage drop and reduce the DC voltage on
CBOOT. So they can’t be too large to affect the DC driving
voltage of upper MOSFET.
VCC_5V
VIN
DBOOT
(EQ. 3)
RBOOT2
5.1Ω
CBOOT
4.7µF
BOOT
where,
Vd1 = Sum of the parasitic voltage drops in the inductor
discharge path, including the lower FET, inductor and PC
board.
Vd2 = Sum of the voltage drops in the charging path,
including the upper FET, inductor and PC board resistances.
The maximum input voltage and minimum output voltage is
limited by the minimum ON-time (tON(min)).
V OUT
V IN ( max ) ≤ ---------------------------------------------------t ON ( min ) × 1.4MHz
UGATE
CBOOT
PHASE
ISL6441
FIGURE 15. GATE DRIVER
(EQ. 4)
where, tON(min) = 30ns
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing amplification, level shifting
and shoot-through protection. The gate drivers have some
circuitry that helps optimize the IC’s performance over a
wide range of operational conditions. As MOSFET switching
times can vary dramatically from type-to-type and with input
voltage, the gate control logic provides adaptive dead time
by monitoring real gate waveforms of both the upper and the
lower MOSFETs. Shoot-through control logic provides a
20ns deadtime to ensure that both the upper and lower
MOSFETs will not turn on simultaneously and cause a
shoot-through condition.
Gate Drivers
The low-side gate driver is supplied from VCC_5V and
provides a peak sink/source current of 400mA. The
high-side gate driver is also capable of 400mA current.
Gate-drive voltages for the upper N-Channel MOSFET are
generated by the flying capacitor boot circuit. A boot
capacitor (CBOOT at Figure 15) connected from the BOOT
pin to the PHASE node provides power to the high side
MOSFET driver. It’s highly recommended to add a small
resistor (RBOOT1 at Figure 15, 5.1Ω typical) in series with
CBOOT and another small resistor (RBOOT2 at Figure 15,
5.1Ω typical) in series with the bootstrap diode to prevent the
overcharge of CBOOT that may cause overvoltage failure
between BOOT and PHASE pin (Figure 15). RBOOT1 also
functions as the resistor in series with the Ugate for damping
the upper gate driving and phase node oscillations, which
helps to improves the EMI performance. But this resistor will
slow down the turn-on of upper MOSFET, so RBOOT1 can’t
12
RBOOT1
5.1Ω
At start-up the low-side MOSFET turns on and forces
PHASE to ground in order to charge the BOOT capacitor to
5V. After the low-side MOSFET turns off, the high-side
MOSFET is turned on by closing an internal switch between
BOOT and UGATE. This provides the necessary
gate-to-source voltage to turn on the upper MOSFET, an
action that boosts the 5V gate drive signal above VIN. The
current required to drive the upper MOSFET is drawn from
the internal 5V regulator.
Protection Circuits
The converter output is monitored and protected against
overload, short circuit and undervoltage conditions. A
sustained overload on the output sets the PGOOD low and
initiates hiccup mode.
Overcurrent Protection
Cycle by cycle current limiting scheme is implemented in
Equation 5. Both PWM controllers use the lower MOSFET’s
ON-resistance, rDS(ON) , to monitor the current in the
converter. The sensed voltage drop is compared with a
threshold set by a resistor connected from the OCSETx pin
to ground.
( 7 ) ( R CS )
R OCSET = ------------------------------------------( I OC ) ( r DS ( ON ) )
(EQ. 5)
where, IOC is the desired overcurrent protection threshold,
and RCS is a value of the current sense resistor connected
to the ISENx pin. If the lower MOSFET current exceeds the
overcurrent threshold, a pulse skipping circuit is activated.
Figure 16 shows the inductor current, output voltage, and the
PHASE node voltage just as an overcurrent trip occurs. The
upper MOSFET will not be turned on as long as the sensed
current is higher than the threshold value. This limits the
current supplied by the DC voltage source. If an overcurrent
FN9197.3
May 26, 2009
ISL6441
is detected for 2 consecutive clock cycles then the IC enters
a hiccup mode by turning off the gate drivers and entering
into soft-start. The IC will cycle 2x through soft-start before
trying to restart. The IC will continue to cycle through
soft-start until the overcurrent condition is removed.
Figure 17 shows this behavior.
.
Implementing Synchronization
The SYNC pin may be used to synchronize two or more
controllers. When the SYNC pins of two controllers are
connected together, one controller becomes the master and
the other controller synchronizes to the master. A pull-down
resistor is required and must be sized to provide a low
enough time constant to pass the SYNC pulse. Connect this
pin to VCC_5V if not used. Figure 18 shows the SYNC pin
waveform operating at 4x the switching frequency.
VOUT2 2V/DIV
SYNC 1V/DIV
IL 2V/DIV
PHASE2 10V/DIV
FIGURE 16. OVERCURRENT TRIP WAVEFORMS
VOUT2 2V/DIV
IOUT2 2V/DIV
FIGURE 18. SYNC WAVEFORM
Feedback Loop Compensation
SS2 2V/DIV
FIGURE 17. OVERCURRENT CONTINUOUS HICCUP MODE
WAVEFORMS
Because of the nature of this current sensing technique, and
to accommodate a wide range of rDS(ON) variations, the
value of the overcurrent threshold should represent an
overload current about 150% to 180% of the maximum
operating current. If more accurate current protection is
desired, place a current sense resistor in series with the
lower MOSFET source.
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit
that shuts the IC down when a die temperature of +150°C
is reached. Normal operation resumes when the die
temperatures drops below +130°C through the initiation of
a full soft-start cycle.
13
To reduce the number of external components and to
simplify the process of determining compensation
components, both PWM controllers have internally
compensated error amplifiers. To make internal
compensation possible several design measures were
taken.
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant with variation in the
input voltage. Second, the load current proportional signal is
derived from the voltage drop across the lower MOSFET
during the PWM time interval and is subtracted from the
amplified error signal on the comparator input. This creates
an internal current control loop. The resistor connected to
the ISEN pin sets the gain in the current feedback loop. The
following expression estimates the required value of the
current sense resistor depending on the maximum operating
load current and the value of the MOSFET’s rDS(ON).
( I MAX ) ( r DS ( ON ) )
R CS ≥ ----------------------------------------------32μA
(EQ. 6)
Choosing RCS to provide 32µA of current to the current
sample and hold circuitry is recommended but can operate
down to 2µA up to 100µA.
FN9197.3
May 26, 2009
ISL6441
Due to the current loop feedback, the modulator has a single
pole response with -20dB slope at a frequency determined
by the load as shown in Equation 7.
upper resistor R1 of the divider that sets the output voltage
value. Please refer to the “Output Inductor Selection” and
the “Input Capacitor Selection on page 17 for further details.
1
F PO = --------------------------------2π ⋅ R O ⋅ C O
Linear Regulator
(EQ. 7)
where RO is load resistance and CO is load capacitance. For
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 19 shows a Type 2 amplifier and it’s response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole as shown in
Equations 8 and 9.
1
F Z = ------------------------------- = 10kHz
2π ⋅ R 2 ⋅ C 1
(EQ. 8)
1
F P = ------------------------------- = 600kHz
2π ⋅ R 1 ⋅ C 2
(EQ. 9)
R2
CONVERTER
C2
C1
R1
EA
TYPE 2 EA
GM = 15.5dB
GEA=13dB
MODULATOR
FZ
FPO
FP
The linear regulator controller is a trans conductance
amplifier with a nominal gain of 2A/V. The N-Channel
MOSFET output device can sink a minimum of 50mA. The
reference voltage is 0.8V. With 0V differential at its input, the
controller sinks 21mA of current. An external PNP transistor
or PFET pass element can be used. The dominant pole for
the loop can be placed at the base of the PNP (or gate of the
PFET), as a capacitor from emitter to base (source to gate of
a PFET). Better load transient response is achieved
however, if the dominant pole is placed at the output, with a
capacitor to ground at the output of the regulator.
Under no-load conditions, leakage currents from the pass
transistors supply the output capacitors, even when the
transistor is off. Generally this is not a problem since the
feedback resistor drains the excess charge. However,
charge may build up on the output capacitor making VLDO
rise above its set point. Care must be taken to insure that the
feedback resistor’s current exceeds the pass transistor’s
leakage current over the entire temperature range.
The linear regulator output can be supplied by the output of
one of the PWMs. When using a PFET, the output of the
linear will track the PWM supply after the PWM output rises
to a voltage greater than the threshold of the PFET pass
device. The voltage differential between the PWM and the
linear output will be the load current times the rDS(ON).
Figure 20 shows the linear regulator (2.5V) start-up
waveform and the PWM (3.3V) start-up waveform.
FC
FIGURE 19. FEEDBACK LOOP COMPENSATION
VOUT2 1V/DIV
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 10kHz to 50kHz range gives
some additional phase ‘boost’. Some phase boost can also
be achieved by connecting capacitor CZ in parallel with the
14
VOUT3 1V/DIV
FIGURE 20. LINEAR REGULATOR START-UP WAVEFORM
FN9197.3
May 26, 2009
ISL6441
Layout Considerations
ERROR AMPLIFIER SINK
CURRENT (mA)
60
1. The Input capacitors, Upper FET, Lower FET, Inductor
and Output capacitor, should be placed first. Isolate these
power components on the topside of the board with their
ground terminals adjacent to one another. Place the input
high frequency decoupling ceramic capacitor very close
to the MOSFETs.
50
40
30
2. Use separate ground planes for power ground and small
signal ground. Connect the SGND and PGND together
close of the IC. Do not connect them together anywhere
else.
20
10
0
0.79
0.80
0.84
0.82
0.83
0.81
FEEDBACK VOLTAGE (V)
0.85
FIGURE 21. LINEAR CONTROLLER GAIN
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system
noise, especially when the linear regulator is lightly loaded.
Capacitively coupled switching noise or inductively coupled
EMI onto the base drive causes fluctuations in the base
current, which appear as noise on the linear regulator’s
output. Keep the base drive traces away from the step-down
converter, and as short as possible, to minimize noise
coupling. A resistor in series with the gate drivers reduces
the switching noise generated by PWM. Additionally, a
bypass capacitor may be placed across the base-to-emitter
resistor. This bypass capacitor, in addition to the transistor’s
input capacitor, could bring in second pole that will
destabilize the linear regulator. Therefore, the stability
requirements determine the maximum base-to-emitter
capacitance.
Layout Guidelines
Careful attention to layout requirements is necessary for
successful implementation of an ISL6441 based DC/DC
converter. The ISL6441 switches at a very high frequency
and therefore the switching times are very short. At these
switching frequencies, even the shortest trace has
significant impedance. Also the peak gate drive current rises
significantly in extremely short time. Transition speed of the
current from one device to another causes voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
generate EMI, increase device over voltage stress and
ringing. Careful component selection and proper PC board
layout minimizes the magnitude of these voltage spikes.
There are two sets of critical components in a DC/DC
converter using the ISL6441; the switching power
components and the small signal components. The
switching power components are the most critical from a
layout point of view because they switch a large amount of
energy so they tend to generate a large amount of noise.
The critical small signal components are those connected to
sensitive nodes or those supplying critical bias currents. A
multi-layer printed circuit board is recommended.
15
3. The loop formed by Input capacitor, the top FET and the
bottom FET must be kept as small as possible.
4. Insure the current paths from the input capacitor to the
MOSFET; to the output inductor and output capacitor are
as short as possible with maximum allowable trace
widths.
5. Place The PWM controller IC close to lower FET. The
LGATE connection should be short and wide. The IC can
be best placed over a quiet ground area. Avoid switching
ground loop current in this area.
6. Place VCC_5V bypass capacitor very close to VCC_5V
pin of the IC and connect its ground to the PGND plane.
7. Place the gate drive components BOOT diode and BOOT
capacitors together near controller IC.
8. The output capacitors should be placed as close to the
load as possible. Use short wide copper regions to
connect output capacitors to load to avoid inductance and
resistances.
9. Use copper filled polygons or wide but short trace to
connect junction of upper FET, lower FET and output
inductor. Also keep the PHASE node connection to the IC
short. Do not unnecessarily oversize the copper islands
for PHASE node. Since the phase nodes are subjected to
very high dv/dt voltages, the stray capacitor formed
between these islands and the surrounding circuitry will
tend to couple switching noise.
10. Route all high speed switching nodes away from the
control circuitry.
11. Create a separate small analog ground plane near the IC.
Connect SGND pin to this plane. All small signal
grounding paths including feedback resistors, current
limit setting resistors and SYNC/SDx pull-down resistors
should be connected to this SGND plane.
12. Ensure the feedback connection to output capacitor is
short and direct.
Component Selection Guidelines
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-Channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon rDS(ON), gate supply requirements,
and thermal management considerations.
FN9197.3
May 26, 2009
ISL6441
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see Equations 10 and 11). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near zero voltage. Equations 10 and 11
assume linear voltage-current transitions and do not model
power loss due to the reverse-recovery of the lower
MOSFET’s body diode.
2
( I O ) ( r DS ( ON ) ) ( V OUT ) ( I O ) ( V IN ) ( t SW ) ( F SW )
P UPPER = --------------------------------------------------------------- + -----------------------------------------------------------V IN
2
(EQ. 10)
2
( I O ) ( r DS ( ON ) ) ( V IN – V OUT )
P LOWER = ------------------------------------------------------------------------------V IN
(EQ. 11)
A large gate-charge increases the switching time, tSW,
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements
including ripple voltage and load transients. Selection of
output capacitors is also dependent on the output inductor,
so some inductor analysis is required to select the output
capacitors.
One of the parameters limiting the converter’s response to a
load transient is the time required for the inductor current to
slew to its new level. The ISL6441 will provide either 0% or
71% duty cycle in response to a load transient.
The response time is the time interval required to slew the
inductor current from an initial current value to the load
current level. During this interval the difference between the
inductor current and the transient current level must be
supplied by the output capacitor(s). Minimizing the response
time can minimize the output capacitance required. Also, if
the load transient rise time is slower than the inductor
response time, as in a hard drive or CD drive, it reduces the
requirement on the output capacitor.
The maximum capacitor value required to provide the full,
rising step, transient load current during the response time of
the inductor is shown in Equation 12:
2
( L O ) ( I TRAN )
C OUT = ----------------------------------------------------------2 ( V IN – V O ) ( DV OUT )
(EQ. 12)
where, COUT is the output capacitor(s) required, LO is the
output inductor, ITRAN is the transient load current step, VIN
16
is the input voltage, VO is output voltage, and DVOUT is the
drop in output voltage allowed during the load transient.
High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Equivalent Series Resistance) and
voltage rating requirements as well as actual capacitance
requirements.
The output voltage ripple is due to the inductor ripple current
and the ESR of the output capacitors as defined by
Equation 13.
V RIPPLE = ΔI L ( ESR )
(EQ. 13)
where, IL is calculated in the “Output Inductor Selection” on
page 17.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load
circuitry for specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications at 1.4MHz for the bulk
capacitors. In most cases, multiple small-case electrolytic
capacitors perform better than a single large-case capacitor.
The stability requirement on the selection of the output
capacitor is that the ‘ESR zero’, f Z, be between 2kHz and
50kHz. This range is set by an internal, single compensation
zero at 10kHz. The ESR zero can be a factor of five on either
side of the internal zero and still contribute to increased
phase margin of the control loop. Therefore, see
Equation 14.
1
C OUT = -----------------------------------2π ( ESR ) ( f Z )
(EQ. 14)
In conclusion, the output capacitors must meet three criteria:
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load
transient,
2. The ESR must be sufficiently low to meet the desired
output voltage ripple due to the output inductor current,
and
3. The ESR zero should be placed in a rather large range,
to provide additional phase margin.
The recommended output capacitor value for the ISL6441 is
between 150µF to 680µF, to meet stability criteria with
external compensation. Use of low ESR ceramic capacitors
is possible but would take more rigorous loop analysis to
ensure stability.
FN9197.3
May 26, 2009
ISL6441
Output Inductor Selection
( V IN – V OUT ) ( V OUT )
ΔI L = ---------------------------------------------------------( f S ) ( L ) ( V IN )
(EQ. 15)
Input Capacitor Selection
The important parameters for the bulk input capacitor(s) are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25x greater than the maximum
input voltage and 1.5x is a conservative guideline. The AC
RMS Input current varies with the load. The total RMS
current supplied by the input capacitance is as shown in
Equations 16 and 17:
2
4.5
4.0
IN PHASE
3.5
3.0
2.5
OUT-OF-PHASE
2.0
1.5
5V
3.3V
1.0
0.5
For the ISL6441, Inductor values between 1µH to 3.3µH is
recommended when using the “Typical Application
Schematic” on page 4. Other values can be used but a more
rigorous stability analysis should be done.
I RMS =
5.0
INPUT RMS CURRENT
The PWM converters require output inductors. The output
inductor is selected to meet the output voltage ripple
requirements. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current and output capacitor(s) ESR. The ripple voltage
expression is given in the “Output Capacitor Selection” on
page 16 or “Input Capacitor Selection” on page 17 and the
ripple current is approximated by Equation 15:
2
(EQ. 16)
2
(EQ. 17)
I RMS1 + I RMS2
0
0
1
2
3
3.3V AND 5V LOAD CURRENT
4
5
FIGURE 22. INPUT RMS CURRENT vs LOAD
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
For board designs that allow through-hole components, the
Sanyo OS-CON® series offer low ESR and good
temperature performance. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX is surge current tested.
where,
I RMSx =
DC – DC
DC is duty cycle of the respective PWM.
Depending on the specifics of the input power and its
impedance, most (or all) of this current is supplied by the
input capacitor(s). Figure 22 shows the advantage of having
the PWM converters operating out-of-phase. If the
converters were operating in phase, the combined RMS
current would be the algebraic sum, which is a much larger
value as shown. The combined out-of-phase current is the
square root of the sum of the square of the individual
reflected currents and is significantly less than the combined
in-phase current.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN9197.3
May 26, 2009
ISL6441
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
4X 3.0
5.00
24X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
28
22
1
5.00
21
3 .10 ± 0 . 15
15
(4X)
7
0.15
8
14
TOP VIEW
0.10 M C A B
- 0.07
4 28X 0.25 + 0.05
28X 0.55 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 65 TYP )
( 24X 0 . 50)
(
SIDE VIEW
3. 10)
(28X 0 . 25 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 28X 0 . 75)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
18
FN9197.3
May 26, 2009