ISL6445 ® Data Sheet June 3, 2008 1.4MHz Dual, 180° Out-of-Phase, Step-Down PWM Controller FN9230.1 Features The ISL6445 is a high-performance, dual-output PWM controller optimized for converting wall adapter, battery or network intermediate bus DC input supplies into the system supply voltages required for a wide variety of applications. Each output is adjustable down to 0.8V. The two PWMs are synchronized 180o out-of-phase reducing the RMS input current and ripple voltage. The ISL6445 incorporates several protection features. An adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the lower MOSFET. Hiccup mode overcurrent operation protects the DC/DC components from damage during output overload/short circuit conditions. Each PWM has an independent logic-level shutdown input (SD1 and SD2). A single PGOOD signal is issued when soft-start is complete on both PWM controllers and their outputs are within 10% of the set point. Thermal shutdown circuitry turns off the device if the junction temperature exceeds +150°C. • Wide Input Supply Voltage Range - 5.6V to 24V - 4.5V to 5.6V • Two Independently Programmable Output Voltages • Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .1.4MHz • Out-of-Phase PWM Controller Operation - Reduces Required Input Capacitance and Power Supply Induced Loads • No External Current Sense Resistor - Uses Lower MOSFET’s rDS(ON) • Programmable Soft-Start • Extensive Circuit Protection Functions - PGOOD - UVLO - Overcurrent - Over-temperature - Independent Shutdown for Both PWMs • Excellent Dynamic Response - Voltage Feed-Forward with Current Mode Control Pinout ISL6445 (24 LD QSOP) TOP VIEW • Pb-Free (RoHS Compliant) LGATE2 1 24 LGATE1 Applications BOOT2 2 23 BOOT1 • Power Supplies with Two Outputs UGATE2 3 22 UGATE1 • xDSL Modems/Routers PHASE2 4 21 PHASE1 • DSP, ASIC, and FPGA Power Supplies ISEN2 5 20 ISEN1 PGOOD 6 19 PGND • Set-Top Boxes VCC5 7 18 SD1 SD2 8 17 SS1 • Dual Output Supplies for DSP, Memory, Logic, µP Core and I/O SS2 9 16 SGND • Telecom Systems 15 OCSET1 OCSET2 10 FB2 11 14 FB1 VIN 12 13 BIAS Ordering Information PART NUMBER (Note) PART MARKING ISL6445IAZ* ISL 6445IAZ TEMP. RANGE (°C) -40 to +85 PACKAGE (Pb-Free) PKG. DWG. # 24 Ld QSOP M24.15 *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6445 Typical Application Schematic VCC5 +12V C2 4.7µF VIN D1 BAT54HT1 SS1 C4 0.1µF C3 10µF BOOT1 C7 0.1µF VOUT1 L1 +1.8V, 2A 3.2µH C9 + 150µF R3 12.4k R1 7 9 23 2 UGATE1 22 3 PHASE1 21 4 ISEN1 20 5 Q1 FDS6912A PGND FB1 R4 10k SD1 ISL6445IA 24 C5 0.1µF C6 10µF BOOT2 UGATE2 C8 0.1µF PHASE2 R2 L2 1.4k 3.2µH ISEN2 1 LGATE2 19 11 D2 BAT54HT1 SS2 1.4K LGATE1 C1 56µF VCC5 12 17 + FB2 VOUT2 +3.3V, 2A + C10 150µF Q2 FDS6912A R5 31.6k OCSET1 14 15 R6 10k R7 121k 18 OCSET2 SD2 10 8 R8 121k 16 13 SGND BIAS 6 PGOOD PGOOD R9 10k VCC5 2 FN9230.1 June 3, 2008 Block Diagram BOOT1 PGOOD SD1 VIN SD2 SGND BOOT2 VCC UGATE2 UGATE1 PHASE2 PHASE1 ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING VCC_5V ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING VCC LGATE1 LGATE2 PGND 3 POR PGND ENABLE BIAS SUPPLIES REFERENCE FAULT LATCH FB3 SOFT-START UV PGOOD OC1 16kΩ OC2 16kΩ PWM1 - PWM2 - SOFT2 + + ERROR AMP 1 + 0.8V REF + + ERROR AMP 2 SS1 + DUTY CYCLE RAMP GENERATOR PWM CHANNEL PHASE CONTROL ISEN1 + 0.8V REF ISEN2 - CURRENT SAMPLE VSEN2 180kΩ - - CURRENT SAMPLE CURRENT SAMPLE CURRENT SAMPLE + OCSET2 OCSET1 + 0.8V REFERENCE 0.8V REFERENCE - OC1 OC2 + + VIN FN9230.1 June 3, 2008 SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT - VCC SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT + ISL6445 180kΩ 800kΩ 18.5pF 18.5pF 800kΩ FB1 UV PGOOD ISL6445 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Input Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V UGATE1, 2. . . . . . . . . . . . (PHASE1, 2 - 0.3V) to (BOOT1, 2 +0.3V) Thermal Resistance (Typical) θJA (°C/W) 24 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Package) -55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical Application Schematic” on page 2. VIN = 5.6V to 24V, or VCC5 = 5V ±10%, TA = -40°C to +85°C, Typical values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 5.6 12 24 V 4.5 5.0 5.6 V VIN SUPPLY Input Voltage Range VCC_5V SUPPLY (Note 2) Input Voltage Output Voltage VIN > 5.6V, IL = 20mA 4.5 5.0 5.5 V Maximum Output Current VIN = 12V 60 - - mA - 50 375 µA - 2.0 4.0 mA - 0.8 - V -1.0 - 1.0 % Rising VCC_5V Threshold 4.25 4.45 4.5 V Falling VCC_5V Threshold 3.95 4.2 4.4 V 1.25 1.4 1.55 MHz VIN = 12V - 1.6 - V VIN = 5V - 0.667 - V - 1.0 - V 2.0 - - V - - 0.8 V Output Voltage - 0.8 - V FB Pin Bias Current - - 150 nA PWM1, COUT = 1000p, TA = +25°C 71 - - % PWM2, COUT = 1000pF, TA = +25°C 73 - - % SUPPLY CURRENT Shutdown Current (Note 3) SD1 = SD2 = GND Operating Current (Note 4) REFERENCE SECTION Nominal Reference Voltage Reference Voltage Tolerance POWER-ON RESET OSCILLATOR Total Frequency Variation Peak-to-Peak Sawtooth Amplitude (Note 5) Ramp Offset (Note 6) SHUTDOWN1/SHUTDOWN2 HIGH Level (Converter Enabled) Internal Pull-up (3µA) LOW Level (Converter Disabled) PWM CONVERTERS Maximum Duty Cycle 4 FN9230.1 June 3, 2008 ISL6445 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical Application Schematic” on page 2. VIN = 5.6V to 24V, or VCC5 = 5V ±10%, TA = -40°C to +85°C, Typical values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 4 - % DC Gain (Note 6) 80 88 - dB Gain-Bandwidth Product (Note 6) 5.9 - - MHz - 2.0 - V/µs Maximum Output Voltage (Note 6) 0.9 - - V Minimum Output Voltage (Note 6) - - 3.6 V - 400 - mA Minimum Duty Cycle PWM CONTROLLER ERROR AMPLIFIERS Slew Rate (Note 6) PWM CONTROLLER GATE DRIVERS (Note 7) Sink/Source Current Upper Drive Pull-Up Resistance VCC5 = 4.5V - 8 - Ω Upper Drive Pull-Down Resistance VCC5 = 4.5V - 3.2 - Ω Lower Drive Pull-Up Resistance VCC5 = 4.5V - 8 - Ω Lower Drive Pull-Down Resistance VCC5 = 4.5V - 1.8 - Ω Rise Time COUT = 1000pF - 18 - ns Fall Time COUT = 1000pF - 18 - ns Pull-up = 100kΩ - 0.1 0.5 V - - ±1.0 µA POWER GOOD AND CONTROL FUNCTIONS PGOOD LOW Level Voltage PGOOD Leakage Current PGOOD Upper Threshold, PWM 1 and 2 Fraction of set point 105 - 120 % PGOOD Lower Threshold, PWM 1 and 2 Fraction of set point 80 - 95 % - 32 - µA - 64 - µA - 1.75 - V - 5 - µA Rising - 150 - °C Hysteresis - 20 - °C ISEN and CURRENT LIMIT Full Scale Input Current (Note 8) Overcurrent Threshold (Note 8) ROCSET = 110kΩ OCSET (Current Limit) Voltage SOFT-START Soft-Start Current PROTECTION Thermal Shutdown NOTES: 2. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min). When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the VCC_5V pin. (Refer to the “Pin Descriptions” on page 8 for more details.) 3. This is the total shutdown current with VIN = VCC_5V = PVCC = 5V. 4. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current. 5. The peak-to-peak sawtooth amplitude is production tested at 12V only; at 5V this parameter is guaranteed by design. 6. Limits should be considered typical and are not production tested. 7. Limits established by characterization and are not production tested. 8. Established by characterization. The full scale current of 32µA is recommended for optimum current sample and hold operation. See “Feedback Loop Compensation” on page 11. 5 FN9230.1 June 3, 2008 ISL6445 Oscilloscope plots are taken using the ISL6445EVAL Evaluation Board. 3.40 3.40 3.39 3.39 PWM2 OUTPUT VOLTAGE (V) PWM1 OUTPUT VOLTAGE (V) Typical Performance Curves 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 LOAD CURRENT (A) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOAD CURRENT (A) FIGURE 1. PWM1 LOAD REGULATION FIGURE 2. PWM2 LOAD REGULATION 0.85 PGOOD 5V/DIV REFERENCE VOLTAGE (V) 0.84 0.83 0.82 VOUT3 2V/DIV 0.81 0.80 0.79 VOUT2 2V/DIV 0.78 0.77 0.76 0.75 -40 -20 20 40 0 TEMPERATURE (°C) 60 80 FIGURE 3. REFERENCE VOLTAGE VARIATION OVER TEMPERATURE VOUT1 20mV/DIV, AC COUPLED VOUT1 2V/DIV FIGURE 4. SOFT-START WAVEFORMS WITH PGOOD VOUT2 20mV/DIV, AC COUPLED IL2 0.5A/DIV, AC COUPLED IL1 0.5A/DIV, AC COUPLED PHASE2 10V/DIV PHASE1 10V/DIV FIGURE 5. PWM1 WAVEFORMS 6 FIGURE 6. PWM2 WAVEFORMS FN9230.1 June 3, 2008 ISL6445 Typical Performance Curves Oscilloscope plots are taken using the ISL6445EVAL Evaluation Board. VOUT2 200mV/DIV AC COUPLED VOUT1 200mV/DIV AC COUPLED IOUT1 1A/DIV IOUT2 1A/DIV FIGURE 7. LOAD TRANSIENT RESPONSE VOUT1 (3.3V) FIGURE 8. LOAD TRANSIENT RESPONSE VOUT2 (1.2V) VOUT1 2V/DIV VCC_5V 1V/DIV IL1 2A/DIV SS1 2V/DIV VOUT1 1V/DIV FIGURE 9. PWM SOFT-START WAVEFORM FIGURE 10. OVERCURRENT HICCUP MODE OPERATION 100 PWM2 EFFICIENCY (%) PWM1 EFFICIENCY (%) 100 90 80 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LOAD CURRENT (A) FIGURE 11. PWM1 EFFICIENCY vs LOAD (3.3V), VIN = 5V 7 90 80 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LOAD CURRENT (A) FIGURE 12. PWM2 EFFICIENCY vs LOAD (3.3V), VIN = 5V FN9230.1 June 3, 2008 ISL6445 Pin Descriptions BOOT2, BOOT1 - These pins power the upper MOSFET drivers of each PWM converter. Connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the VCC_5V pin. UGATE2, UGATE1 - These pins provide the gate drive for the upper MOSFETs. PHASE2, PHASE1 - These pins are connected to the junction of the upper MOSFETs source, output filter inductor and lower MOSFETs drain. LGATE2, LGATE1 - These pins provide the gate drive for the lower MOSFETs. PGND - This pin provides the power ground connection for the lower gate drivers for both PWM1 and PWM2. This pin should be connected to the sources of the lower MOSFETs and the (-) terminals of the external input capacitors. FB2, FB1 - These pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. They set the output voltage of the converter. In addition, the PGOOD circuit uses these inputs to monitor the output voltage status. ISEN2, ISEN1 - These pins are used to monitor the voltage drop across the lower MOSFET for current loop feedback and overcurrent protection. PGOOD - This is an open drain logic output used to indicate the status of the output voltages. This pin is pulled low when either of the two PWM outputs is not within 10% of the respective nominal voltage. SGND - This is the small-signal ground, common to both controllers, and must be routed separately from the high current ground (PGND). All voltage levels are measured with respect to this pin. Connect the additional SGND pins to this pin. VIN - Use this pin to power the device with an external supply voltage with a range of 5.6V to 24V. For 5V ±10% operation, connect this pin to VCC5. VCC5 - This pin is the output of the internal +5V linear regulator. This output supplies the bias for the IC, the low side gate drivers, and the external boot circuitry for the high side gate drivers. The IC may be powered directly from a single 5V (±10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VCC5 pin must be always decoupled to power ground with a recommended minimum of 4.7µF ceramic capacitor, placed very close to the pin. BIAS - This pin must be connected directly to VCC5. SS1, SS2 - These pins provide a soft-start function for their respective PWM controllers. When the chip is enabled, the 8 regulated 5µA pull-up current source charges the capacitor connected from this pin to ground. The error amplifier reference voltage ramps from 0V to 0.8V while the voltage on the soft-start pin ramps from 0V to 0.8V. SD1, SD2 - These pins provide an enable/disable function for their respective PWM output. The output is enabled when this pin is floating or pulled HIGH, and disabled when the pin is pulled LOW. OCSET2, OCSET1 - A resistor from this pin to ground sets the overcurrent threshold for the respective PWM. Functional Description General Description The ISL6445 integrates control circuits for two synchronous buck converters. The two synchronous bucks operate 180 degrees out of phase to substantially reduce the input ripple and thus reduce the input filter requirements. The chip has four control lines (SS1, SD1, SS2, and SD2), which provide independent control for each of the synchronous buck outputs. The PWM controllers employ a free-running frequency of 1.4MHz. The current mode control scheme with an input voltage feed-forward ramp input to the modulator provides excellent rejection of input voltage variations and provides simplified loop compensation. Internal 5V Linear Regulator (VCC5) All ISL6445 functions are internally powered from an on-chip, low dropout, +5V regulator. The maximum regulator input voltage is 24V. Bypass the regulator’s output (VCC5) with a 4.7µF capacitor to ground. The dropout voltage for this LDO is typically 600mV, so when VIN is greater than 5.6V, VCC5 is +5V. The ISL6445 also employs an undervoltage lockout circuit that disables both regulators when VCC5 falls below 4.4V. The internal LDO can source over 60mA to supply the IC, power the low side gate drivers, charge the external boot capacitor and supply small external loads. When driving large FETs, little or no regulator current may be available for external loads. For example, a single large FET with 30nC total gate charge requires 30nC x 1.4MHz = 42mA. Thus four total FETs would require 36mA. With 3mA for the internal bias would leave approximately 20mA for an external +5V supply. Also, at higher input voltages with larger FETs, the power dissipation across the internal 5V will increase. Excessive dissipation across this regulator must be avoided to prevent junction temperature rise. Larger FETs can be used with 5V ±10% input applications. The thermal overload protection circuit will be triggered if the VCC5 output is short circuited. Connect VCC5 to VIN for 5V ±10% input applications. FN9230.1 June 3, 2008 ISL6445 Soft-Start Operation When soft-start is initiated, the voltage on the SS pin of the enabled PWM channels starts to ramp gradually, due to the 5µA current sourced into the external capacitor. The output voltage follows the soft-start voltage. VOUT2 1V/DIV When the SS pin voltage reaches 0.8V, the output voltage of the enabled PWM channel reaches the regulation point, and the soft-start pin voltage continues to rise. At this point the PGOOD and fault circuitry is enabled. This completes the soft-start sequence. Any further rise of SS pin voltage does not affect the output voltage. By varying the values of the soft-start capacitors, it is possible to provide sequencing of the main outputs at start-up. The soft-start time can be obtained from Equation 1: C SS T SOFT = 0.8V ⎛ -----------⎞ ⎝ 5μA⎠ (EQ. 1) VOUT1 1V/DIV FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING START-UP Output Voltage Programming A resistive divider from the output to ground sets the output voltage of either PWM channel. The center point of the divider shall be connected to FBx pin. The output voltage value is determined by Equation 2. VCC5 1V/DIV R1 + R2 V OUTx = 0.8V ⎛ ----------------------⎞ ⎝ R2 ⎠ VOUT1 1V/DIV (EQ. 2) where R1 is the top resistor of the feedback divider network and R2 is the resistor connected from FB1 or FB2 to ground. Out-of-Phase Operation SS1 1V/DIV FIGURE 13. SOFT-START OPERATION The soft-start capacitors can be chosen to provide startup tracking for the two PWM outputs. This can be achieved by choosing the soft-start capacitors such that the soft-start capacitor ration equals the respective PWM output voltage ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V then the soft-start capacitor ration should be, CSS1/CSS2 = 1.2/3.3 = 0.364. Figure 14 shows that soft-start waveform with CSS1 = 0.01µF and CSS2 = 0.027µF. The two PWM controllers in the ISL6445 operate 180° out-of-phase to reduce input ripple current. This reduces the input capacitor ripple current requirements, reduces power supply-induced noise, and improves EMI. This effectively helps to lower component cost, save board space and reduce EMI. Dual PWMs typically operate in-phase and turn on both upper FETs at the same time. The input capacitor must then support the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current. The higher RMS ripple current lowers the efficiency due to the power loss associated with the ESR of the input capacitor. This typically requires more low-ESR capacitors in parallel to minimize the input voltage ripple and ESR-related losses, or to meet the required ripple current rating. With dual synchronized out-of-phase operation, the high-side MOSFETs of the ISL6445 turn on 180° out-of-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple current rating, allowing fewer or less expensive capacitors, and reducing the shielding requirements for EMI. The typical operating curves show the synchronized 180° out-of-phase operation. 9 FN9230.1 June 3, 2008 ISL6445 Input Voltage Range The ISL6445 is designed to operate from input supplies ranging from 4.5V to 24V. However, the input voltage range can be effectively limited by the available maximum duty cycle (DMAX = 71%). V OUT + V d1 V IN ( min ) = ⎛ --------------------------------⎞ + V d2 – V d1 ⎝ ⎠ 0.71 VIN BOOT (EQ. 3) UGATE where, Vd1 = Sum of the parasitic voltage drops in the inductor discharge path, including the lower FET, inductor and PC board. Vd2 = Sum of the voltage drops in the charging path, including the upper FET, inductor and PC board resistances. The maximum input voltage and minimum output voltage is limited by the minimum on-time (tON(min)). V OUT V IN ( max ) ≤ ---------------------------------------------------t ON ( min ) × 1.4MHz VCC5 (EQ. 4) where, tON(min) = 30ns Gate Control Logic The gate control logic translates generated PWM signals into gate drive signals providing amplification, level shifting and shoot-through protection. The gate drivers have some circuitry that helps optimize the ICs performance over a wide range of operational conditions. As MOSFET switching times can vary dramatically from type to type and with input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower MOSFETs. Shoot-through control logic provides a 20ns deadtime to ensure that both the upper and lower MOSFETs will not turn on simultaneously and cause a shoot-through condition. Gate Drivers The low-side gate driver is supplied from VCC5 and provides a peak sink/source current of 400mA. The high-side gate driver is also capable of 400mA current. Gate-drive voltages for the upper N-Channel MOSFET are generated by the flying capacitor boot circuit. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high side MOSFET driver. To limit the peak current in the IC, an external resistor may be placed between the UGATE pin and the gate of the external MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s gate to drain capacitance. PHASE ISL6445 FIGURE 15. GATE DRIVER At start-up the low-side MOSFET turns on and forces PHASE to ground in order to charge the BOOT capacitor to 5V. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 5V regulator. Protection Circuits The converter output is monitored and protected against overload, short circuit and undervoltage conditions. A sustained overload on the output sets the PGOOD low and initiates hiccup mode. Both PWM controllers use the lower MOSFET’s ON-resistance, rDS(ON) , to monitor the current in the converter. The sensed voltage drop is compared with a threshold set by a resistor connected from the OCSETx pin to ground. ( 7 ) ( R CS ) R OCSET = ------------------------------------------( I OC ) ( r DS ( ON ) ) (EQ. 5) where, IOC is the desired overcurrent protection threshold, and RCS is a value of the current sense resistor connected to the ISENx pin. If the lower MOSFET current exceeds the overcurrent threshold, an overcurrent condition is detected. If overcurrent is detected for 2 consecutive clock cycles then the IC enters a hiccup mode by turning off the gate drivers and entering into soft-start. The IC will cycle 2x through soft-start before trying to restart. The IC will continue to cycle through soft-start until the overcurrent condition is removed. Because of the nature of this current sensing technique, and to accommodate a wide range of rDS(ON) variations, the value of the overcurrent threshold should represent an overload current about 150% to 180% of the maximum operating current. If more accurate current protection is desired place a current sense resistor in series with the lower MOSFET source. 10 FN9230.1 June 3, 2008 ISL6445 Over-Temperature Protection The IC incorporates an over-temperature protection circuit that shuts the IC down when a die temperature of +150°C is reached. Normal operation resumes when the die temperatures drops below +130°C through the initiation of a full soft-start cycle. C2 R2 C1 CONVERTER R1 EA TYPE 2 EA Feedback Loop Compensation GM = 17.5dB To reduce the number of external components and to simplify the process of determining compensation components, both PWM controllers have internally compensated error amplifiers. To make internal compensation possible several design measures were taken. First, the ramp signal applied to the PWM comparator is proportional to the input voltage provided via the VIN pin. This keeps the modulator gain constant with variation in the input voltage. Second, the load current proportional signal is derived from the voltage drop across the lower MOSFET during the PWM time interval and is subtracted from the amplified error signal on the comparator input. This creates an internal current control loop. The resistor connected to the ISEN pin sets the gain in the current feedback loop. Equation 6 estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the MOSFET’s rDS(ON). ( I MAX ) ( r DS ( ON ) ) R CS ≥ ----------------------------------------------32μA (EQ. 6) Choosing RCS to provide 32µA of current to the current sample and hold circuitry is recommended but values down to 2µA and up to 100µA can be used. Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency determined by the load. 1 F PO = --------------------------------2π ⋅ R O ⋅ C O (EQ. 7) where RO is load resistance and CO is load capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. Figure 16 shows a Type 2 amplifier and its response along with the responses of the current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies in between the zero and the pole. 1 F Z = ------------------------------- = 6kHz 2π ⋅ R 2 ⋅ C 1 (EQ. 8) 1 F P = ------------------------------- = 600kHz 2π ⋅ R 1 ⋅ C 2 (EQ. 9) 11 GEA = 18dB MODULATOR FZ FPO FP FC FIGURE 16. FEEDBACK LOOP COMPENSATION The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 1.2kHz to 30kHz range gives some additional phase ‘boost’. Some phase boost can also be achieved by connecting capacitor CZ in parallel with the upper resistor R1 of the divider that sets the output voltage value. Please refer to the “Output Inductor” and “Capacitor Selection” on page 13 for further details. Layout Guidelines Careful attention to layout requirements is necessary for successful implementation of a ISL6445 based DC/DC converter. The ISL6445 switches at a very high frequency and therefore the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also the peak gate drive current rises significantly in extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, increase device overvoltage stress and ringing. Careful component selection and proper PC board layout minimizes the magnitude of these voltage spikes. FN9230.1 June 3, 2008 ISL6445 There are two sets of critical components in a DC/DC converter using the ISL6445. The switching power components and the small signal components. The switching power components are the most critical from a layout point of view because they switch a large amount of energy so they tend to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multi-layer printed circuit board is recommended. Layout Considerations 1. The Input capacitors, Upper FET, Lower FET, Inductor and Output capacitor should be placed first. Isolate these power components on the topside of the board with their ground terminals adjacent to one another. Place the input high frequency decoupling ceramic capacitor very close to the MOSFETs. Making the gate traces as short and thick as possible will limit the parasitic inductance and reduce the level of dv/dt seen at the gate of the lower FETs when the upper FET turns on. 2. Use separate ground planes for power ground and small signal ground. Connect the SGND and PGND together close of the IC. Do not connect them together anywhere else. 3. The loop formed by Input capacitor, the top FET and the bottom FET must be kept as small as possible. 4. Insure the current paths from the input capacitor to the MOSFET; to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. 5. Place The PWM controller IC close to lower FET. The LGATE connection should be short and wide. The IC can be best placed over a quiet ground area. Avoid switching ground loop current in this area. 6. Place VCC5 bypass capacitor very close to VCC5 pin of the IC and connect its ground to the PGND plane. 7. Place the gate drive components BOOT diode and BOOT capacitors together near controller IC. 8. The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. Use copper filled polygons or wide but short trace to connect junction of upper FET. Lower FET and output inductor. Also keep the PHASE node connection to the IC short. Do not unnecessary oversize the copper islands for PHASE node. Since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. Route all high speed switching nodes away from the control circuitry. 11. Create separate small analog ground plane near the IC. Connect SGND pin to this plane. All small signal grounding paths including feedback resistors, current 12 limit setting resistors, SDx pull-down resistors should be connected to this SGND plane. 12. Ensure the feedback connection to output capacitor is short and direct. Component Selection Guidelines MOSFET Considerations The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. Two N-Channel MOSFETs are used in each of the synchronous-rectified buck converters for the PWM1 and PWM2 outputs. These MOSFETs should be selected based upon rDS(ON), gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see Equations 10 and 11). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. Equations 10 and 11 assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. 2 ( I O ) ( r DS ( ON ) ) ( V OUT ) ( I O ) ( V IN ) ( t SW ) ( F SW ) P UPPER = --------------------------------------------------------------- + -----------------------------------------------------------V IN 2 (EQ. 10) 2 ( I O ) ( r DS ( ON ) ) ( V IN – V OUT ) P LOWER = ------------------------------------------------------------------------------V IN (EQ. 11) A large gate-charge increases the switching time, tSW, which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. As the input voltage increases the power dissipation in the internal +5V regulator increases. To ensure that the ISL6445 does not overheat choose the external MOSFETs based on the total FET gate charge according the Figure 17. The plot shows the maximum recommended gate charge for different maximum ambient operating temperatures. The power dissipation across the internal LDO comes from the bias current for the chip as well as the current needed to supply the internal gate drivers that drive the external MOSFETs. The plot uses a recommended maximum operating junction temperature of +125°C and calculates the maximum gate charge based on the die temperature and the maximum drive current that the internal LDO can supply. FN9230.1 June 3, 2008 ISL6445 determined by the ESR (Equivalent Series Resistance) and voltage rating requirements as well as actual capacitance requirements. TOTAL GATE CHARGE (nC) 50 40 The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by Equation 13: TA = +50°C V RIPPLE = ΔI L ( ESR ) (EQ. 13) 30 where, IL is calculated in the “Output Inductor Selection” on page 13. TA = +70°C 20 TA = +60°C 10 6 9 15 12 18 INPUT VOLTAGE (V) 21 24 FIGURE 17. FET GATE CHARGE Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the output inductor, so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to it’s new level. The ISL6445 will provide either 0% or 71% duty cycle in response to a load transient. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications at 1.4MHz for the bulk capacitors. In most cases, multiple small-case electrolytic capacitors perform better than a single large-case capacitor. The stability requirement on the selection of the output capacitor is that the ‘ESR zero’, f Z, be between 1.2kHz and 30kHz. This range is set by an internal, single compensation zero at 6kHz. The ESR zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. Therefore, 1 C OUT = ------------------------------------2Π ( ESR ) ( f Z ) (EQ. 14) In conclusion, the output capacitors must meet three criteria: The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor. 1. They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient, The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is: The recommended output capacitor value for the ISL6445 is between 150µF to 680µF, to meet stability criteria with external compensation. Use of aluminum electrolytic, POSCAP, or tantalum type capacitors is recommended. Use of low ESR ceramic capacitors is possible but would take more rigorous loop analysis to ensure stability. 2 ( L O ) ( I TRAN ) C OUT = ----------------------------------------------------------2 ( V IN – V O ) ( DV OUT ) (EQ. 12) where, COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VO is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally 13 2. The ESR must be sufficiently low to meet the desired output voltage ripple due to the output inductor current, and 3. The ESR zero should be placed, in a rather large range, to provide additional phase margin. Output Inductor Selection The PWM converters require output inductors. The output inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) ESR. The ripple voltage FN9230.1 June 3, 2008 ISL6445 expression is given in the capacitor selection section and the ripple current is approximated by Equation 15: ( V IN – V OUT ) ( V OUT ) ΔI L = ---------------------------------------------------------( f S ) ( L ) ( V IN ) (EQ. 15) For the ISL6445, use Inductor values between 1µH to 3.3µH. Input Capacitor Selection The important parameters for the bulk input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25x greater than the maximum input voltage and 1.5x is a conservative guideline. The AC RMS Input current varies with the load. The total RMS current supplied by the input capacitance is as shown in Equation 16: I RMS = 2 2 Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For board designs that allow through-hole components, the Sanyo OS-CON® series offer low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX is surge current tested. (EQ. 16) I RMS1 + I RMS2 where, I RMSx = DC – DC 2 (EQ. 17) DC is duty cycle of the respective PWM. Depending on the specifics of the input power and its impedance, most (or all) of this current is supplied by the input capacitor(s). Figure 18 shows the advantage of having the PWM converters operating out of phase. If the converters were operating in phase, the combined RMS current would be the algebraic sum, which is a much larger value as shown. The combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is significantly less than the combined in-phase current. 5.0 4.5 INPUT RMS CURRENT 4.0 IN PHASE 3.5 3.0 2.5 OUT-OF-PHASE 2.0 1.5 5V 3.3V 1.0 0.5 0 0 1 2 3 3.3V AND 5V LOAD CURRENT 4 5 FIGURE 18. INPUT RMS CURRENT vs LOAD 14 FN9230.1 June 3, 2008 ISL6445 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) M24.15 N INDEX AREA H 0.25(0.010) M 24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) B M E 1 2 INCHES GAUGE PLANE -B- SYMBOL 3 L 0.25 0.010 SEATING PLANE -A- A D h x 45° -C- α e A2 A1 B C 0.10(0.004) 0.17(0.007) M C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MIN MAX MILLIMETERS MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - A2 - 0.061 - 1.54 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.337 0.344 8.55 8.74 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 N α 24 0° 24 8° 0° 7 8° 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. Rev. 2 6/04 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN9230.1 June 3, 2008