ISL6755 ¬ Data Sheet September 29, 2008 ZVS Full-Bridge PWM Controller with Average Current Limit FN6442.1 Features • Adjustable Resonant Delay for ZVS Operation The ISL6755 is a high-performance extension of the Intersil family of full-bridge ZVS controllers. Like the ISL6753, it achieves ZVS operation by driving the upper bridge FETs at a fixed 50% duty cycle while the lower bridge FETS are trailing-edge modulated with adjustable resonant switching delays. Adding to the ISL6753’s feature set is average current monitoring. The signal may be used for average current limiting, current sharing circuits and average current mode control. This advanced BiCMOS design features low operating current, adjustable oscillator frequency up to 2MHz, adjustable soft-start, precision deadtime and resonant delay control, and short propagation delays. Additionally, Multi-Pulse Suppression ensures alternating output pulses at low duty cycles where pulse skipping may occur. • Voltage- or Current-Mode Operation • 3% Current Limit Threshold • Adjustable Average Current Limit • 175µA Startup Current • Supply UVLO • Adjustable Deadtime Control • Adjustable Soft-Start • Adjustable Oscillator Frequency Up to 2MHz • Tight Tolerance Error Amplifier Reference Over Line, Load, and Temperature • 5MHz GBWP Error Amplifier • Adjustable Cycle-by-Cycle Peak Current Limit • Fast Current Sense to Output Delay Ordering Information PART NUMBER (Note) PART MARKING ISL6755AAZA* 6755 AAZ • 70ns Leading Edge Blanking TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # -40 to +105 20 Ld QSOP M20.15 *Add -T suffix to part number for tape and reel packaging NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Multi-Pulse Suppression • Buffered Oscillator Sawtooth Output • Internal Over-Temperature Protection • Pb-Free (RoHS Compliant) Applications • ZVS Full-Bridge Converters • Telecom and Datacom Power • Wireless Base Station Power Pinout ISL6755 (20 LD QSOP) TOP VIEW VERR 1 • File Server Power • Industrial Power Systems 20 VREF CTBUF 2 19 SS RTD 3 18 VDD RESDEL 4 17 OUTLL CT 5 16 OUTLR FB2 6 15 OUTUL FB1 7 14 OUTUR RAMP 8 13 N/C CS 9 12 GND IOUT 10 11 GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Functional Block Diagram VDD OUTUL 50% VDD OUTUR VREF PWM STEERING LOGIC UVLO OUTLL 2 OVERTEMPERATURE PROTECTION PWM OUTLR GND SAMPLE AND HOLD VREF - +70 nS LEADING EDGE BLANKING 1.00V OVER CURRENT COMPARATOR RESDEL ISL6755 IOUT CS + 4X RAMP CT OSCILLATOR VREF PWM COMPARATOR VREF RTD 80mV 1 mA + - SS VERR 0.33 CTBUF SOFTSTART CONTROL + - 0.6V FB1 + - FB2 FN6442.1 September 29, 2008 Typical Application - High Voltage Input ZVS Full-Bridge Converter VIN+ CR2 CR3 T3 Q2 Q8A R19 R20 Q8B Q5A C12 R12 Q5B Q1 C11 C9 + T1 C1 3 CR5 400 VDC RETURN L1 C16 C10 Q10A CR4 Q9A Q9B Q10B C16 C13 Q4 Q6A Q7A Q6B Q7B R13 + Vout Q3 R18 R17 U1 ISL6755 C8 R11 R16 T2 1 VERR CR1 VREF 20 2 CTBUF R19 R8 R7 R4 SS 19 4 RESDEL OUTLL 17 5 CT OUTLR 16 6 FB2 OUTUL 15 7 FB1 OUTUR 14 8 RAMP R10 R1 C14 VDD 18 3 RTD U2 N/C 13 9 CS GND 12 10 IOUT GND 11 C15 R2 R9 U3 VDD C3 C2 R5 R6 R15 C4 R14 R3 C5 C6 C7 ISL6755 VIN- BIAS + FN6442.1 September 29, 2008 ISL6755 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22.0V OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A Latchup (Note 3) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C Thermal Resistance (Typical) θJA (°C/W) 20 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . 88 Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range ISL6755AAxx . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Supply Voltage Range (Typical). . . . . . . . . . . . . . . 9VDC to 16VDC CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND. 3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a pulse limited to 50mA. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - - 20 - SUPPLY VOLTAGE Supply Voltage Start-Up Current, IDD VDD = 5.0V - 175 400 µA Operating Current, IDD RLOAD, COUT = 0 - 11.0 15.5 mA UVLO START Threshold 8.00 8.75 9.00 V UVLO STOP Threshold 6.50 7.00 7.50 V - 1.75 - V 4.850 5.000 5.150 V - 3 - mV -10 - - mA 5 - - mA VREF = 4.85V -15 - -100 mA Current Limit Threshold VERR = VREF 0.97 1.00 1.03 V CS to OUT Delay Excl. LEB - 35 - ns - 70 - ns Hysteresis REFERENCE VOLTAGE Overall Accuracy IVREF = 0mA to -10mA Long Term Stability TA = +125°C, 1000 hours (Note 4) Operational Current (source) Operational Current (sink) Current Limit CURRENT SENSE Leading Edge Blanking (LEB) Duration CS to OUT Delay + LEB TA = +25°C - - 150 ns CS Sink Current Device Impedance VCS = 1.1V - - 20 Ω Input Bias Current VCS = 0.3V -1.0 - 1.0 µA IOUT Sample and Hold Buffer Amplifier Gain TA = +25°C 3.85 4.00 4.15 V/V IOUT Sample and Hold VOH VCS = max, ILOAD = -300µA 3.9 - - V IOUT Sample and Hold VOL VCS = 0.00V, ILOAD = 10µA - - 0.3 V 4 FN6442.1 September 29, 2008 ISL6755 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - - 20 Ω 65 80 95 mV RAMP RAMP Sink Current Device Impedance VRAMP = 1.1V RAMP to PWM Comparator Offset TA = +25°C Bias Current VRAMP = 0.3V -5.0 - -2.0 µA Minimum Duty Cycle VERR < 0.6V - - 0 % Maximum Duty Cycle (per half-cycle) VERR = 4.20V, VRAMP = 0V, VCS = 0V (Note 5) - 94 - % RTD = 2.00kΩ, CT = 220pF - 97 - % RTD = 2.00kΩ, CT = 470pF - 99 - % 0.85 - 1.20 V 0.7 0.8 0.9 V 0.31 0.33 0.35 V/V (Note 4) 0 - VSS V Input Common Mode (CM) Range (Note 4) 0 - VREF V GBWP (Note 4) 5 - - MHz VERR VOL ILOAD = 2mA - - 0.4 V VERR VOH ILOAD = 0mA 4.20 - - V VERR Pull-Up Current Source VERR = 2.5V 0.8 1.0 1.3 mA EA Reference TA = 25°C 0.594 0.600 0.606 V 0.590 0.600 0.612 V 165 183 201 kHz -10 - +10 % PULSE WIDTH MODULATOR Zero Duty Cycle VERR Voltage VERR to PWM Comparator Input Offset TA = +25°C VERR to PWM Comparator Input Gain Common Mode (CM) Input Range ERROR AMPLIFIERS EA Reference + EA Input Offset Voltage OSCILLATOR Frequency Accuracy, Overall (Note 4) Frequency Variation with VDD TA = +25°C, (F20V- - F10V)/F10V - 0.3 1.7 % Temperature Stability VDD = 10V, |F-40°C - F0°C|/F0°C - 4.5 - % |F0°C - F105°C|/F25°C (Note 4) - 1.5 - % -193 -200 -207 µA 19 20 23 µA/µA TA = +25°C Charge Current Discharge Current Gain CT Valley Voltage Static Threshold 0.75 0.80 0.88 V CT Peak Voltage Static Threshold 2.75 2.80 2.88 V CT Pk-Pk Voltage Static Value 1.92 2.00 2.05 V 1.97 2.00 2.03 V 0 - 2 V 1.95 2.0 2.05 V/V RTD Voltage RESDEL Voltage Range CTBUF Gain (VCTBUFP-P/VCTP-P) 5 VCT = 0.8V, 2.6V FN6442.1 September 29, 2008 ISL6755 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.34 0.40 0.44 V CTBUF Offset from GND VCT = 0.8V CTBUF VOH ΔV(ILOAD = 0mA, ILOAD = -2mA), VCT = 2.6V - - 0.10 V CTBUF VOL ΔV(ILOAD = 2mA, ILOAD = 0mA), VCT = 0.8V - - 0.10 V -60 -70 -80 µA 4.410 4.500 4.590 V 10 - - mA 0.23 0.27 0.33 V SOFT-START Charging Current SS = 3V SS Clamp Voltage SS Discharge Current SS = 2V Reset Threshold Voltage TA = +25°C OUTPUTS High Level Output Voltage (VOH) IOUT = -10mA, VDD - VOH - 0.5 1.0 V Low Level Output Voltage (VOL) IOUT = 10mA, VOL - GND - 0.5 1.0 V Rise Time COUT = 220pF, VDD = 15V (Note 4) - 110 200 ns Fall Time COUT = 220pF, VDD = 15V (Note 4) - 90 150 ns UVLO Output Voltage Clamp VDD = 7V, ILOAD = 1mA (Note 6) - - 1.25 V Thermal Shutdown (Note 4) - 140 - °C Thermal Shutdown Clear (Note 4) - 125 - °C Hysteresis, Internal Protection (Note 4) - 15 - °C THERMAL PROTECTION NOTES: 4. Limits established by characterization and are not production tested. 5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using other values for these components. See Equations 1 through 5. 6. Adjust VDD below the UVLO stop threshold prior to setting at 7V. 6 FN6442.1 September 29, 2008 ISL6755 Typical Performance Curves 1.01 1 0.99 0.98 -40 25 CT DISCHARGE CURRENT GAIN NORMALIZED VREF 1.02 -25 -10 5 20 35 50 65 80 95 24 23 22 21 20 19 18 110 0 200 400 600 800 1000 RTD CURRENT (¬¨¬ TEMPERATURE (¬¨Ð FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT 1-103 1-104 CT = 1000pF FREQUENCY (kHz) DEADTIME TD (ns) CT = 680pF CT = 470pF 1-103 CT = 100pF CT = 220pF CT = 330pF 100 RTD = 10kΩ 100 RTD = 50kΩ RTD = 100kΩ 10 0 10 20 30 40 50 60 RTD (kΩ) 70 80 90 100 FIGURE 3. DEADTIME (DT) vs CAPACITANCE Pin Descriptions VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. Supply voltage under-voltage lock-out (UVLO) start and stop thresholds track each other resulting in relatively constant hysteresis. GND - Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. VREF - The 5.00V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a 0.1μF to 2.2μF low ESR capacitor. CT - The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200μA current source and discharged with a user adjustable current source controlled by RTD. RTD - This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this pin and GND determines the 7 10 0.1 1 CT (nF) 10 FIGURE 4. CAPACITANCE vs FREQUENCY magnitude of the current that discharges CT. The CT discharge current is nominally 20x the resistor current. The PWM deadtime is determined by the timing capacitor discharge duration. The voltage at RTD is nominally 2.00V. CS - This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1.00V nominal. The CS pin is shorted to GND at the termination of either PWM output. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. This delay may result in CS being discharged prior to the power switching device being turned off. RAMP - This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected to CS and the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate an appropriate signal, RAMP may be connected to the input voltage through a RC network for voltage feed forward control, or RAMP may be connected to VREF FN6442.1 September 29, 2008 ISL6755 through a RC network to produce the desired sawtooth waveform. nominal valley-to-peak gain of 2. It may be used for slope compensation. OUTUL and OUTUR - These outputs control the upper bridge FETs and operate at a fixed 50% duty cycle in alternate sequence. OUTUL controls the upper left FET and OUTUR controls the upper right FET. The left and right designation may be switched as long as they are switched in conjunction with the lower FET outputs, OUTLL and OUTLR. Functional Description RESDEL - Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower FETs. The voltage applied to RESDEL determines when the upper FETs switch relative to a lower FET turning on. Varying the control voltage from 0 to 2.00V increases the resonant delay duration from 0 to 100% of the deadtime. The control voltage divided by 2 represents the percent of the deadtime equal to the resonant delay. In practice the maximum resonant delay must be set lower than 2.00V to ensure that the lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs. OUTLL and OUTLR - These outputs control the lower bridge FETs, are pulse width modulated, and operate in alternate sequence. OUTLL controls the lower left FET and OUTLR controls the lower right FET. The left and right designation may be switched as long as they are switched in conjunction with the upper FET outputs, OUTUL and OUTUR. VERR - The control voltage input to the inverting input of the PWM comparator. The output of an external error amplifier (EA) is applied to this input for closed loop regulation. VERR has a nominal 1mA pull-up current source. When VERR is driven by an opto-coupler or other current source device, a pull-up resistor from VREF is required to linearize the gain. Generally, a pull-up resistor on the order of 5kΩ is acceptable. FB1,2 - FB1 and FB2 are the inverting inputs to the error amplifiers (EA). The amplifier may be used as the error amplifier for voltage feedback or used as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded. IOUT - Output of the 4X buffer amplifier of the sample and hold circuitry that captures and averages the CS signal. SS - Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor and the internal current source determine the rate of increase of the duty cycle during start-up. Features The ISL6755 PWM is an excellent choice for low cost ZVS full-bridge applications employing conventional output rectification. If synchronous rectification is required, please consider the ISL6752 or ISL6551 products. With the ISL6755’s many protection and control features, a highly flexible design with minimal external components is possible. Among its many features are support for both current- and voltage-mode control, a very accurate overcurrent limit threshold, thermal protection, a buffered sawtooth oscillator output suitable for slope compensation, voltage controlled resonant delay, and adjustable frequency with precise deadtime control. Oscillator The ISL6755 has an oscillator with a programmable frequency range to 2MHz, and can be programmed with an external resistor and capacitor. The switching period is the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and a fixed 200μA internal current source. The discharge duration is determined by RTD and CT. 3 T C ≈ 11.5 ⋅ 10 ⋅ CT S (EQ. 1) T D ≈ ( 0.06 ⋅ RTD ⋅ CT ) + 50 ⋅ 10 1 T SW = T C + T D = -----------F SW S –9 S (EQ. 2) (EQ. 3) where TC and TD are the charge and discharge times, respectively, TSW is the oscillator period, and FSW is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. This delay adds directly to the switching duration, but also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very small discharge currents are used, there will be increased error due to the input impedance at the CT pin. SS may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration. CTBUF - CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing 2mA. It is offset from ground by 0.40V and has a 8 FN6442.1 September 29, 2008 ISL6755 The maximum duty cycle, D, and percent deadtime, DT, can be calculated from: TC D = -----------T SW (EQ. 4) DT = 1 – D (EQ. 5) Soft-Start Operation The ISL6755 features a soft-start using an external capacitor in conjunction with an internal current source. Soft-start reduces component stresses and surge currents during start-up. Upon start-up, the soft-start circuitry limits the error voltage input (VERR) to a value equal to the soft-start voltage. The output pulse width increases as the soft-start capacitor voltage increases. This has the effect of increasing the duty cycle from zero to the regulation pulse width during the soft-start period. When the soft-start voltage exceeds the error voltage, soft-start is completed. Soft-start occurs during start-up and after recovery from a fault condition. The soft-start charging period may be calculated as follows: t = 64.3 ⋅ C (EQ. 6) ms where t is the charging period in ms and C is the value of the soft-start capacitor in μF. The second method is a slower, averaging method which produces constant or “brick-wall” current limit behavior. If voltage-mode control is used, the average overcurrent protection also maintains flux balance in the transformer by maintaining duty cycle symmetry between half-cycles. If voltage-mode control is used in a bridge topology, it should be noted that peak current limit results in inherently unstable operation. The DC blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. Average current limit will prevent the instability and allow continuous operation in current limit provided the control loop is designed with adequate bandwidth. The propagation delay from CS exceeding the current limit threshold to the termination of the output pulse is increased by the leading edge blanking (LEB) interval. The effective delay is the sum of the two delays and is nominally 105ns. The current sense signal applied to the CS pin connects to the peak current comparator and a sample and hold averaging circuit. After a 70ns leading edge blanking (LEB) delay, the current sense signal is actively sampled during the on time, the average current for the cycle is determined, and the result is amplified by 4x and output on the IOUT pin. If an RC filter is placed on the CS input, its time constant should not exceed ~50ns or significant error may be introduced on IOUT. The soft-start voltage is clamped to 4.50V with a tolerance of 2%. It is suitable for use as a “soft-started” reference provided the current draw is kept well below the 70μA charging current. The outputs may be inhibited by using the SS pin as a disable input. Pulling SS below 0.25V forces all outputs low. An open collector/drain configuration may be used to couple the disable signal into the SS pin. Gate Drive The ISL6755 outputs are capable of sourcing and sinking 10mA (at rated VOH, VOL) and are intended to be used in conjunction with integrated FET drivers or discrete bipolar totem pole drivers. The typical on resistance of the outputs is 50Ω. CHANNEL 1 (YELLOW): OUTLL CHANNEL 3 (BLUE): CS Overcurrent Operation Two overcurrent protection mechanisms are available to the power supply designer. The first method is cycle-by-cycle peak overcurrent protection which provides fast response. The cycle-by-cycle peak current limit results in pulse-by-pulse duty cycle reduction when the current feedback signal exceeds 1.0V. When the peak current exceeds the threshold, the active output pulse is immediately terminated. This results in a decrease in output voltage as the load current increases beyond the current limit threshold. The ISL6755 operates continuously in an overcurrent condition without shutdown. 9 CHANNEL 2 (RED): OUTLR CHANNEL 4 (GREEN): IOUT FIGURE 5. CS INPUT vs IOUT Figure 5 shows the relationship between the CS signal and IOUT under steady state conditions. IOUT is 4x the average of CS. Figure 6 shows the dynamic behavior of the current averaging circuitry when CS is modulated by an external sine wave. Notice IOUT is updated by the sample and hold circuitry at the termination of the active output pulse. FN6442.1 September 29, 2008 ISL6755 The EA available on the ISL6755 may also be used as the voltage EA for the voltage feedback control loop rather than the current EA as described above. An external op-amp may be used as either the current or voltage EA providing the circuit is not allowed to source current into VERR. The external EA must only sink current, which may be accomplished by adding a diode in series with its output. The 4x gain of the sample and hold buffer allows a range of 150mV to 1000mV peak on the CS signal, depending on the resistor divider placed on IOUT. The overall bandwidth of the average current loop is determined by the integrating current EA compensation and the divider on IOUT. CHANNEL 1 (YELLOW): OUTLL CHANNEL 3 (BLUE): CS CHANNEL 2 (RED): OUTLR CHANNEL 4 (GREEN): IOUT 1 VERR 20 VREF 2 19 SS 3 ISL6755 FIGURE 6. DYNAMIC BEHAVIOR OF CS vs IOUT The average current signal on IOUT remains accurate provided that the output inductor current is continuous (CCM operation). Once the inductor current becomes discontinuous (DCM operation), IOUT represents 1/2 the peak inductor current rather than the average current. This occurs because the sample and hold circuitry is active only during the on time of the switching cycle. It is unable to detect when the inductor current reaches zero during the off time. If average overcurrent limit is desired, IOUT may be used with either of the available error amplifiers of the ISL6755. Typically IOUT is divided down and filtered as required to achieve the desired amplitude. The resulting signal is input to the current error amplifier (IEA). The IEA is similar to the voltage EA found in most PWM controllers, except it cannot source current. Instead, VERR has a separate internal 1mA pull-up current source. Configure the IEA as an integrating (Type I) amplifier using the internal 0.6V reference. The voltage applied at FBx is integrated against the 0.6V reference. The resulting signal, VERR, is applied to the PWM comparator where it is compared to the sawtooth voltage on RAMP. If FBx is less than 0.6V, the IEA will be open loop (can’t source current), VERR will be at a level determined by the voltage loop, and the duty cycle is unaffected. As the output load increases, IOUT will increase, and the voltage applied to FB will increase until it reaches 0.6V. At this point the IEA will reduce VERR as required to maintain the output current at the level that corresponds to the 0.6V reference. When the output current again drops below the average current limit threshold, the IEA returns to an open loop condition, and the duty cycle is again controlled by the voltage loop. C10 150 - 1000 mV 4 17 OUTLL 5 16 OUTLR 6 15 OUTUL 7 FB1 0.6V + 8 14 OUTUR 9 CS 10 IOUT R6 18 VDD S&H 4x 13 N/C 12 GND 11 GND R5 R4 FIGURE 7. AVERAGE OVERCURRENT IMPLEMENTATION The current EA cross-over frequency, assuming R6 >> (R4||R5), is: 1 f CO = ----------------------------------2π ⋅ R6 ⋅ C10 Hz (EQ. 7) where fCO is the cross-over frequency. A capacitor in parallel with R4 may be used to provide a double-pole roll-off. The average current loop bandwidth is normally set to be much less than the switching frequency, typically less than 5kHz and often as slow as a few hundred hertz or less. This is especially useful if the application experiences large surges. The average current loop can be set to the steady state overcurrent threshold and have a time response that is longer than the required transient. The peak current limit can be set higher than the expected transient so that it does not interfere with the transient, but still protects for short-term larger faults. In essence a 2-stage overcurrent response is possible. The average current control loop behaves much the same as the voltage control loop found in typical power supplies except it regulates current rather than voltage. 10 FN6442.1 September 29, 2008 ISL6755 The peak overcurrent behavior is similar to most other PWM controllers. If the peak current exceeds 1.0V, the active output pulse is terminated immediately. If voltage-mode control is used in a bridge topology, it should be noted that peak current limit results in inherently unstable operation. DC blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. The average overcurrent circuitry prevents this behavior by maintaining symmetric duty cycles for each half-cycle. If the average current limit circuitry is not used, a latching overcurrent shutdown method using external components is recommended. The CS to output propagation delay is increased by the leading edge blanking (LEB) interval. The effective delay is the sum of the two delays and is 130ns maximum. selected so that the ramp amplitude reaches 1.0V at minimum input voltage within the duration of one half-cycle. VIN 1 20 2 19 3 18 4 R3 17 ISL6755 5 16 6 15 7 14 8 RAMP C7 13 9 GND 12 10 GND 11 Voltage Feed Forward Operation Voltage feed forward is a technique used to regulate the output voltage for changes in input voltage without the intervention of the control loop. Voltage feed forward is often implemented in voltage-mode control loops, but is redundant and unnecessary in peak current-mode control loops. Voltage feed forward operates by modulating the sawtooth ramp in direct proportion to the input voltage. Figure 8 demonstrates the concept. VIN ERROR VOLTAGE FIGURE 9. VOLTAGE FEED FORWARD CONTROL The charging time of the ramp capacitor is: V RAMP ( PEAK )⎞ ⎛ t = – R3 ⋅ C7 ⋅ ln ⎜ 1 – ----------------------------------------⎟ V IN ( MIN ) ⎠ ⎝ S (EQ. 8) For optimum performance, the maximum value of the capacitor should be limited to 10nF. The maximum DC current through the resistor should be limited to 2mA maximum. For example, if the oscillator frequency is 400kHz, the minimum input voltage is 300V, and a 4.7nF ramp capacitor is selected, the value of the resistor can be determined by rearranging Equation 9. –6 – 2.5 ⋅ 10 –t R3 = ------------------------------------------------------------------------- = -----------------------------------------------------------–9 1 V RAMP ( PEAK )⎞ ⎛ 4.7 ⋅ 10 ⋅ ln ⎛ 1 – ----------⎞ C7 ⋅ ln ⎜ 1 – ----------------------------------------⎟ ⎝ 300⎠ V ⎝ IN ( MIN ) ) ⎠ RAMP CT = 159 kΩ (EQ. 9) OUTLL, LR where t is equal to the oscillator period minus the deadtime. If the deadtime is short relative to the oscillator period, it can be ignored for this calculation. FIGURE 8. VOLTAGE FEED FORWARD BEHAVIOR Input voltage feed forward may be implemented using the RAMP input. An RC network connected between the input voltage and ground, as shown in Figure 9, generates a voltage ramp whose charging rate varies with the amplitude of the source voltage. At the termination of the active output pulse, RAMP is discharged to ground so that a repetitive sawtooth waveform is created. The RAMP waveform is compared to the VERR voltage to determine duty cycle. The selection of the RC components depends upon the desired input voltage operating range and the frequency of the oscillator. In typical applications, the RC components are 11 If feed forward operation is not desired, the RC network may be connected to VREF rather than the input voltage. Alternatively, a resistor divider from CTBUF may be used as the sawtooth signal. Regardless, a sawtooth waveform must be generated on RAMP as it is required for proper PWM operation. Slope Compensation Peak current-mode control requires slope compensation to improve noise immunity, particularly at lighter loads, and to prevent current loop instability, particularly for duty cycles greater than 50%. Slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the FN6442.1 September 29, 2008 ISL6755 voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation, is The inductor current, when reflected through the isolation transformer and the current sense transformer to obtain the current feedback signal at the sense resistor yields: N S ⋅ R CS ⎛ D ⋅ T SW ⎛ NS ⎞⎞ V CS = ------------------------ ⎜ I O + --------------------- ⎜ V IN ⋅ -------- – V O⎟ ⎟ N P ⋅ N CT ⎝ 2L O ⎝ NP ⎠⎠ V (EQ. 17) 1 Fm = -------------------SnTsw (EQ. 10) where VCS is the voltage across the current sense resistor and IO is the output current at current limit. where Sn is the slope of the sawtooth signal and Tsw is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes: 1 1 Fm = --------------------------------------- = ---------------------------( Sn + Se )Tsw m c SnTsw (EQ. 11) (EQ. 12) The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at half the oscillator frequency. The double-pole will be critically damped if the Q-factor is set to 1, and over-damped for Q > 1, and under-damped for Q < 1. An under-damped condition can result in current loop instability. 1 Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 ) (EQ. 13) where D is the percent of on time during a half cycle. Setting Q = 1 and solving for Se yields: 1 1 S e = S n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞ ⎠1–D ⎝⎝ π ⎠ V e + V CS = 1 (EQ. 18) Substituting Equations 16 and 17 into Equation 18 and solving for RCS yields: where Se is slope of the external ramp and: Se m c = 1 + ------Sn Since the peak current limit threshold is 1.00V, the total current feedback signal plus the external ramp voltage must sum to this value. (EQ. 14) N P ⋅ N CT 1 R CS = ------------------------ ⋅ -----------------------------------------------------NS VO 1 D I O + -------- T SW ⎛ --- + ----⎞ ⎝ π 2⎠ L Ω (EQ. 19) O For simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining the amount of external ramp to add. Magnetizing inductance provides a degree of slope compensation to the current feedback signal and reduces the amount of external ramp required. The magnetizing inductance adds primary current in excess of what is reflected from the inductor current in the secondary. V IN ⋅ DT SW ΔI P = ------------------------------Lm (EQ. 20) A where VIN is the input voltage that corresponds to the duty cycle D and Lm is the primary magnetizing inductance. The effect of the magnetizing current at the current sense resistor, RCS, is: Since Sn and Se are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by Ton to obtain the voltage change that occurs during Ton. ΔI P ⋅ R CS ΔV CS = -------------------------N CT 1 1 V e = V n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞ ⎠1–D ⎝⎝π ⎠ If ΔVCS is greater than or equal to Ve, then no additional slope compensation is needed and RCS becomes: (EQ. 15) where Vn is the change in the current feedback signal during the on time and Ve is the voltage that must be added by the external ramp. Vn can be solved for in terms of input voltage, current transducer components, and output inductance yielding: T SW ⋅ V ⋅ R CS N O S 1 V e = ------------------------------------------ ⋅ -------- ⎛ --- + D – 0.5⎞ ⎠ N CT ⋅ L O NP ⎝ π V (EQ. 16) where RCS is the current sense burden resistor, NCT is the current transformer turns ratio, LO is the output inductance, VO is the output voltage, and Ns and Np are the secondary and primary turns, respectively. 12 (EQ. 21) V N CT R CS = -------------------------------------------------------------------------------------------------------------------------------------NS ⎛ DT SW ⎛ NS ⎞ ⎞ V IN ⋅ DT SW -------- ⋅ ⎜ I O + ---------------- ⋅ ⎜ V ⋅ ------- – V O⎟ ⎟ + ------------------------------NP ⎝ 2L O ⎝ IN N P Lm ⎠⎠ (EQ. 22) If ΔVCS is less than Ve, then Equation 19 is still valid for the value of RCS, but the amount of slope compensation added by the external ramp must be reduced by ΔVCS. Adding slope compensation is accomplished in the ISL6755 using the CTBUF signal. CTBUF is an amplified representation of the sawtooth signal that appears on the CT pin. It is offset from ground by 0.4V and is 2x the peak-topeak amplitude of CT (0.4V to 4.4V). A typical application FN6442.1 September 29, 2008 ISL6755 sums this signal with the current sense feedback and applies the result to the CS pin as shown in Figure 10. 1 20 2 CTBUF 19 3 18 4 17 5 R9 6 R6 RCS 16 ISL6755 15 7 14 8 RAMP 13 9 CS GND 12 10 GND 11 Solve for the current sense resistor, RCS, using Equation 19. RCS = 15.1Ω. Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 16. Ve = 153mV Next, determine the effect of the magnetizing current from Equation 21. ΔVCS = 91mV Using Equation 24, solve for the summing resistor, R9, from CTBUF to CS. R9 = 30.1kΩ C4 Determine the new value of RCS, R’CS, using Equation 25. R’CS = 15.4Ω FIGURE 10. ADDING SLOPE COMPENSATION Assuming the designer has selected values for the RC filter placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition. ( D ( V CTBUF – 0.4 ) + 0.4 ) ⋅ R6 V e – ΔV CS = ------------------------------------------------------------------------------R6 + R9 (EQ. 23) V Rearranging to solve for R9 yields ( D ( V CTBUF – 0.4 ) – V e + ΔV CS + 0.4 ) ⋅ R6 R9 = ------------------------------------------------------------------------------------------------------------------V e – ΔV CS The above discussion determines the minimum external ramp that is required. Additional slope compensation may be considered for design margin. If the application requires deadtime less than about 500ns, the CTBUF signal may not perform adequately for slope compensation. CTBUF lags the CT sawtooth waveform by 300ns to 400ns. This behavior results in a non-zero value of CTBUF when the next half-cycle begins when the deadtime is short. Under these situations, slope compensation may be added by externally buffering the CT signal as shown below. Ω (EQ. 24) 1 3 R9 R6 + R9 R′ CS = ---------------------- ⋅ R CS R9 VREF 20 2 The value of RCS determined in Equation 19 or 22 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 17. The divider created by R6 and R9 makes this necessary. (EQ. 25) 19 ISL6755 17 5 CT 16 6 15 7 14 8 RAMP Example: R6 18 4 13 9 CS GND 12 10 GND 11 VIN = 280V VO = 12V RCS C4 CT LO = 2.0μH Np/Ns = 20 Lm = 2mH FIGURE 11. ADDING SLOPE COMPENSATION USING CT IO = 55A Oscillator Frequency, Fsw = 400kHz Duty Cycle, D = 85.7% NCT = 50 Using CT to provide slope compensation instead of CTBUF requires the same calculations, except that Equations 23 and 24 require modification. Equation 23 becomes: 2D ⋅ R6 V e – ΔV CS = ---------------------R6 + R9 R6 = 499Ω 13 V (EQ. 26) FN6442.1 September 29, 2008 ISL6755 and Equation 24 becomes: ( 2D – V e + ΔV CS ) ⋅ R6 R9 = ------------------------------------------------------------V e – ΔV CS Ω (EQ. 27) The buffer transistor used to create the external ramp from CT should have a sufficiently high gain so as to minimize the required base current. Whatever base current is required reduces the charging current into CT and will reduce the oscillator frequency. lumped together as switch capacitance, but represents all parasitic capacitance in the circuit including winding capacitance. Each switch is designated by its position, upper left (UL), upper right (UR), lower left (LL), and lower right (LR). The beginning of the cycle, shown in Figure 14, is arbitrarily set as having switches UL and LR on and UR and LL off. The direction of the primary and secondary currents are indicated by IP and IS, respectively. VIN+ UL UR D1 ZVS Full-Bridge Operation The ISL6755 is a full-bridge zero-voltage switching (ZVS) PWM controller that behaves much like a traditional hard-switched topology controller. Rather than drive the diagonal bridge switches simultaneously, the upper switches (OUTUL, OUTUR) are driven at a fixed 50% duty cycle and the lower switches (OUTLL, OUTLR) are pulse width modulated on the trailing edge. CT DEADTIME OUTLL PWM PWM PWM OUTLR PWM IS VOUT+ LL IP RTN LL LR D2 VIN- FIGURE 14. UL - LR POWER TRANSFER CYCLE The UL - LR power transfer period terminates when switch LR turns off as determined by the PWM. The current flowing in the primary cannot be interrupted instantaneously, so it must find an alternate path. The current flows into the parasitic switch capacitance of LR and UR which charges the node to VIN and then forward biases the body diode of upper switch UR. VIN+ OUTUR UL RESONANT DELAY UR D1 IS VOUT+ LL OUTUL IP RESDEL WINDOW RTN LL FIGURE 12. BRIDGE DRIVE SIGNAL TIMING LR D2 VIN- To understand how the ZVS method operates one must include the parasitic elements of the circuit and examine a full switching cycle. VIN+ UL UR D1 VOUT+ LL RTN LL FIGURE 15. UL - UR FREE-WHEELING PERIOD The primary leakage inductance, LL, maintains the current which now circulates around the path of switch UL, the transformer primary, and switch UR. When switch LR opens, the output inductor current free-wheels through both output diodes, D1 and D2. During the switch transition, the output inductor current assists the leakage inductance in charging the upper and lower bridge FET capacitance. LR D2 VIN- FIGURE 13. IDEALIZED FULL-BRIDGE In Figure 13, the power semiconductor switches have been replaced by ideal switch elements with parallel diodes and capacitance, the output rectifiers are ideal, and the transformer leakage inductance has been included as a discrete element. The parasitic capacitance has been 14 The current flow from the previous power transfer cycle tends to be maintained during the free-wheeling period because the transformer primary winding is essentially shorted. Diode D1 may conduct very little or none of the free-wheeling current, depending on circuit parasitics. This behavior is quite different than occurs in a conventional hard-switched full-bridge topology where the free-wheeling current splits nearly evenly between the output diodes, and flows not at all in the primary. FN6442.1 September 29, 2008 ISL6755 This condition persists through the remainder of the half-cycle. During the period when CT discharges, also referred to as the deadtime, the upper switches toggle. Switch UL turns off and switch UR turns on. The actual timing of the upper switch toggle is dependent on RESDEL which sets the resonant delay. The voltage applied to RESDEL determines how far in advance the toggle occurs prior to a lower switch turning on. The ZVS transition occurs after the upper switches toggle and before the diagonal lower switch turns on. The required resonant delay is 1/4 of the period of the LC resonant frequency of the circuit formed by the leakage inductance and the parasitic capacitance. The resonant transition may be estimated from Equation 28. π 1 τ = --- ----------------------------------2 2 R 1 --------------- – ---------2 LL CP 4L L (EQ. 28) where τ is the resonant transition time, LL is the leakage inductance, CP is the parasitic capacitance, and R is the equivalent resistance in series with LL and CP. The resonant delay is always less than or equal to the deadtime and may be calculated using Equation 29. V resdel τ resdel = -------------------- ⋅ DT 2 S (EQ. 29) where τresdel is the desired resonant delay, Vresdel is a voltage between 0 and 2V applied to the RESDEL pin, and DT is the deadtime (see Equations 1 through 5). The second power transfer period commences when switch LL closes. With switches UR and LL on, the primary and secondary currents flow as indicated in Figure 17. VIN+ UL UR D1 VOUT+ LL RTN LL LR D2 VIN- FIGURE 17. UR - LL POWER TRANSFER The UR - LL power transfer period terminates when switch LL turns off as determined by the PWM. The current flowing in the primary must find an alternate path. The current flows into the parasitic switch capacitance which charges the node to VIN and then forward biases the body diode of upper switch UL. As before, the output inductor current assists in this transition. The primary leakage inductance, LL, maintains the current, which now circulates around the path of switch UR, the transformer primary, and switch UL. When switch LL opens, the output inductor current free-wheels predominantly through diode D1. Diode D2 may actually conduct very little or none of the free-wheeling current, depending on circuit parasitics. This condition persists through the remainder of the half-cycle. VIN+ UL UR D1 IS VOUT+ LL When the upper switches toggle, the primary current that was flowing through UL must find an alternate path. It charges/discharges the parasitic capacitance of switches UL and LL until the body diode of LL is forward biased. If RESDEL is set properly, switch LL will be turned on at this time.The output inductor does not assist this transition. It is purely a resonant transition driven by the leakage inductance. VIN+ UL UR D1 IS VOUT+ LL IP RTN LL IP RTN LL LR D2 VIN- FIGURE 18. UR - UL FREE-WHEELING PERIOD When the upper switches toggle, the primary current that was flowing through UR must find an alternate path. It charges/discharges the parasitic capacitance of switches UR and LR until the body diode of LR is forward biased. If RESDEL is set properly, switch LR will be turned on at this time. LR D2 VIN- FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT TRANSITION 15 FN6442.1 September 29, 2008 ISL6755 Fault Conditions VIN+ UL UR D1 IS VOUT+ LL IP RTN LL LR D2 VIN- FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT TRANSITION The first power transfer period commences when switch LR closes and the cycle repeats. The ZVS transition requires that the leakage inductance has sufficient energy stored to fully charge the parasitic capacitances. Since the energy stored is proportional to the square of the current (1/2 LLIP2), the ZVS resonant transition is load dependent. If the leakage inductance is not able to store sufficient energy for ZVS, a discrete inductor may be added in series with the transformer primary. A fault condition occurs if VREF or VDD fall below their undervoltage lockout (UVLO) thresholds or if the thermal protection is triggered. When a fault is detected, the softstart capacitor is quickly discharged, and the outputs are disabled low. When the fault condition clears and the softstart voltage is below the reset threshold, a soft-start cycle begins. An overcurrent condition is not considered a fault and does not result in a shutdown. Thermal Protection Internal die over-temperature protection is provided. An integrated temperature sensor protects the device should the junction temperature exceed +140°C. There is approximately +15°C of hysteresis. Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD and VREF should be bypassed directly to GND with good high frequency capacitance. References [1] Ridley, R., “A New Continuous-Time Model for Current Mode Control”, IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991. 16 FN6442.1 September 29, 2008 ISL6755 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA H 0.25(0.010) M M20.15 B M 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) E GAUGE PLANE -B1 2 INCHES SYMBOL 3 L 0.25 0.010 SEATING PLANE -A- A D h x 45¬ -C- α e A2 A1 B C 0.10(0.004) 0.17(0.007) M C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. MIN MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - A2 - 0.061 - 1.54 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.337 0.344 8.56 8.74 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 N α 20 0° 20 8° 0° 7 8° Rev. 1 6/04 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6442.1 September 29, 2008