CD4089BMS CMOS Binary Rate Multiplier December 1992 Features conjunction with an up/down counter and control logic used to perform arithmetic operations (adds, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigometric functions, A/D and D/A conversions, and frequency division. • High Voltage Type (20V Rating) • Cascadable in Multiples of 4 Bits • Set to “15” Input and “15” Detect Output • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” For words of more than 4 bits, CD4089BMS devices may be cascaded in two different modes: an Add mode and a Multiply mode (see Figures 3 and 4). In the Add mode some of the gaps left by the more significant unit at the count of 15 are filled in by the less significant units. For example, when two units are cascaded in the Add mode and programmed to 11 and 13, respectively, the more significant unit will have 11 output pulses for every 16 input pulses and the other unit will have 13 output pulses for every 256 input pulses for a total of 11 16 + 13 189 = 256 256 In the Multiply mode the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second multiplier. Thus the output rate will be 11 16 Applications x 13 16 = 143 256 The CD4089BMS has an internal synchronous 4 bit counter which, together with one of the four binary input bits, produces pulse trains as shown in Figure 6. • Numerical Control • Instrumentation • Digital Filtering If more than one binary input bit is high, the resulting pulse train is a combination of the separate pulse trains as shown in Figure 6. • Frequency Synthesis Description The CD4089BMS is supplied in these 16-lead outline packages: CD4089BMS is a low power 4 bit digital rate multiplier that provides an output pulse rate that is the clock-input-pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, there will be 13 output pulses for every 16 input pulses. This device may be used in Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H2R H6P Functional Diagram Pinout CD4089BMS TOP VIEW BINARY RATE SELECT INPUTS CLOCK 9 “15” OUT 1 16 VDD C 2 15 B D 3 14 A SET TO “15” 4 OUT 5 12 CASCADE OUT 6 11 INHIBIT IN (CARRY) INHIBIT OUT (CARRY) 7 VSS 8 INHIBIT (CARRY) IN RATE SELECT LOGIC 11 SET TO “15” 13 CLEAR 4 4 BIT BINARY COUNTER 1 7 VDD = 16 VSS = 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1064 6 OUT OUT RATE OUTPUTS 13 9 CLOCK STROBE CASCADE 12 5 CLEAR 10 STROBE 10 A B C D 14 15 2 3 “15” OUT INHIBIT (CARRY) OUT File Number 3329 Specifications CD4089BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 - 10 µA +125oC - 1000 µA 3 -55oC - 10 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 1 -55oC VDD = 18V MAX 2 oC 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1065 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4089BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Output SYMBOL TPHL1 TPLH1 CONDITIONS (NOTES 1, 2) VDD = 5V, VIN = VDD or GND Propagation Delay Clear to Out TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Cascade to Out TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Transition Time Maximum Clock Input Frequency TTHL TTLH GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND LIMITS MIN MAX UNITS 9 +25oC - 300 ns 10, 11 +125oC, -55oC - 405 ns 9 +25oC - 760 ns 10, 11 +125oC, -55oC - 1026 ns 9 +25oC - 180 ns 10, 11 +125oC, -55oC - 243 ns 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns 9 +25oC 1.2 - MHz 10, 11 +125oC, -55oC .89 - MHz MAX UNITS NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 1, 2 TEMPERATURE MIN -55 C, +25 C - 5 µA +125oC - 150 µA o o -55 C, +25 C - 10 µA +125oC - 300 µA o o -55 C, +25 C - 10 µA +125oC - 600 µA o o o o Output Voltage VOL5 VDD = 5V, No Load 1, 2 +25 C, +125 C, -55oC - 50 mV Output Voltage VOL10 VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH5 VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH10 VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA Output Current (Sink) IOL5 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA 4.2 - mA -55 Output Current (Sink) Output Current (Sink) IOL10 IOL15 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V 1, 2 1, 2 -55 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 oC oC oC - -0.36 mA - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125 -55oC Output Current (Source) Output Current (Source) IOH5B IOH10 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 oC +125 -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 7-1066 1, 2 - -0.9 mA - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Specifications CD4089BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE o o MIN MAX UNITS Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25 C, +125 C, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V Propagation Delay Clock to Out TPHL4 TPLH4 VDD = 5V 1, 2, 3 +25oC - 220 ns VDD = 10V 1, 2, 3 +25oC - 110 ns o - 90 ns o VDD = 15V Propagation Delay Clock to Out Propagation Delay Clock to Inhibit Out Propagation Delay Clock to Inhibit Out TPHL1 TPLH1 TPHL5 TPLH5 1, 2, 3 +25 C VDD = 10V 1, 2, 3 +25 C - 150 ns VDD = 15V 1, 2, 3 +25oC - 120 ns o VDD = 5V 1, 2, 3 +25 C - 720 ns VDD = 10V 1, 2, 3 +25oC - 320 ns o VDD = 15V 1, 2, 3 +25 C - 220 ns VDD = 5V 1, 2, 3 +25oC - 500 ns 1, 2, 3 +25oC - 200 ns VDD = 10V o VDD = 15V 1, 2, 3 +25 C - 150 ns Propagation Delay Clear to Out TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 350 ns VDD = 15V 1, 2, 3 +25 C - 260 ns Propagation Delay Cascade to Out TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC - 90 ns VDD = 15V 1, 2, 3 +25 C - 70 ns Propagation Delay Clock to “9” or “15” Out TPHL6 TPLH6 VDD = 5V 1, 2, 3 +25oC - 600 ns VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns 1, 2, 3 o +25 C - 320 ns VDD = 10V 1, 2, 3 +25 oC - 150 ns VDD = 15V 1, 2, 3 +25oC - 110 ns VDD = 5V 1, 2, 3 +25 oC - 660 ns VDD = 10V 1, 2, 3 +25oC - 300 ns VDD = 15V 1, 2, 3 +25 oC - 220 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25 oC - 80 ns oC 2.5 - MHz 3.5 - MHz Propagation Delay Inhibit In to Inhibit Out Propagation Delay Set to Out Transition Time Maximum Clock Input Frequency Minimum Inhibit-In Setup Time Minimum Inhibit-In Removal Time Minimum Clock Pulse Width Maximum Clock Rise and Fall Time TPHL7 TPLH7 TPHL8 TPLH8 TTHL TTLH FCL TSU TREM TW TRCL TFCL VDD = 5V VDD = 15V o o VDD = 10V 1, 2, 3 +25 VDD = 15V 1, 2, 3 +25oC VDD = 5V 1, 2, 3 +25 oC - 100 ns VDD = 10V 1, 2, 3 +25oC - 40 ns VDD = 15V 1, 2, 3 +25 oC - 20 ns VDD = 5V 1, 2, 3 +25oC - 240 ns VDD = 10V 1, 2, 3 +25oC - 130 ns VDD = 15V 1, 2, 3 +25oC - 110 ns 1, 2, 3 +25 oC - 330 ns oC VDD = 5V VDD = 10V 1, 2, 3 +25 - 170 ns VDD = 15V 1, 2, 3 +25oC - 100 ns oC VDD = 5V 1, 2, 3, 4 +25 - 15 µs VDD = 10V 1, 2, 3, 4 +25oC - 15 µs 1, 2, 3, 4 oC - 15 µs VDD = 15V 7-1067 +25 Specifications CD4089BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Minimum Set Removal Time TREM Minimum Clear Removal Time Minimum Set or Clear Pulse Width Input Capacitance TREM CONDITIONS NOTES CIN o MIN MAX UNITS VDD = 5V 1, 2, 3 +25 C - 150 ns VDD = 10V 1, 2, 3 +25oC - 80 ns o VDD = 15V 1, 2, 3 +25 C - 50 ns VDD = 5V 1, 2, 3 +25oC - 60 ns 1, 2, 3 o +25 C - 40 ns VDD = 15V 1, 2, 3 +25 oC - 30 ns VDD = 5V 1, 2, 3 +25oC - 160 ns VDD = 10V 1, 2, 3 +25oC - 90 ns VDD = 15V 1, 2, 3 +25oC - 60 ns oC - 7.5 pF VDD = 10V TW TEMPERATURE Any Input 1, 2 +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 20V, VIN = VDD or GND TEMPERATURE MIN MAX UNITS o - 25 µA o +25 C 1, 4 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25 C -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP Functional F VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND 1, 4 +25 C - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns o VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 4. Read and Record 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 7-1068 READ AND RECORD IDD, IOL5, IOH5A Specifications CD4089BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B IDD, IOL5, IOH5A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 1, 5-7 2-4, 8-15 16 Static Burn-In 2 (Note 1) 1, 5-7 8 2-4, 9-16 Dynamic BurnIn (Note 1) - 2, 4, 8, 10, 12-15 3, 16 1, 5-7 8 2-4, 9-16 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 1, 5-7 9 11 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1069 CD4089BMS Logic Diagram A *14 B *15 C *2 *10 *12 STROBE CASCADE Qd Qc Qb Qa D *3 CLOCK *9 Qa Qa CLEAR SYNCHRONOUS 4 BIT BINARY COUNTER *13 SET TO “15” *4 OUT 6 Qc Qb Qa OUT 5 Qb Qb Qc Qb Qa Qc Qd Qa Qd INHIBIT IN *11 Qa Qb Qc Qd Qa “15” 1 INHIBIT OUT 7 Qb Qc Qd VDD *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 1. LOGIC DIAGRAM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD4089BMS TRUTH TABLE INPUTS OUTPUTS NUMBER OF PULSES OR INPUT LOGIC LEVEL (0 = Low; 1 = High; X = Don’t Care) NUMBER OF PULSES OR OUTPUT LOGIC LEVEL (L = Low; H = High) D C B A CLK INH IN STR CAS CLR SET OUT OUT INH OUT “15” OUT 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 16 16 16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L 1 2 3 H 1 2 3 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 16 16 16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 6 7 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 16 16 16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 10 11 8 9 10 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 16 16 16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 13 14 15 12 13 14 15 1 1 1 1 1 1 1 1 X X X X X X X X X X X X 16 16 16 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 ** L H ** H * H 1 1 ** 1 1 1 0 X X X X X X X X X X 16 16 16 0 0 0 0 0 0 0 0 0 1 1 X 0 0 1 16 L L 16 H H H H L L L H * Output same as the first 16 lines of this truth table (depending on values A, B, C, D) ** Depends on internal state of counter MOST SIGNIFICANT DIGIT 1 A 1 B 0 C 1 D DRM CLOCK 1 LEAST SIGNIFICANT DIGIT 1 A OUT 0 B OUT 1 C 1 D INH OUT CASC DRM CLOCK 2 MOST SIGNIFICANT DIGIT 1 A OUT 1 B OUT 0 C 1 D INH OUT DRM CLOCK CASC 1 LEAST SIGNIFICANT DIGIT 1 A OUT 0 B OUT 1 C 1 D INH OUT CASC DRM CLOCK 2 OUT OUT INH OUT CASC INH IN “15” INH IN “15” INH IN “15” INH IN “15” ST CLEAR S ST CLEAR S ST CLEAR S ST CLEAR S CLOCK CLOCK FIGURE 2. TWO CD4089BMS’s CASCADED IN THE “ADD” MODE WITH A PRESET NUMBER OF 189 FIGURE 3. TWO CD4089BMS’s CASCADED IN THE “MULTIPLY” MODE WITH A PRESET NUMBER 11 13 189 + = 16 256 256 OF 143 7-1071 11 13 143 + = 16 16 256 CD4089BMS CLOCK COUNTER STATE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 * (LSB) INPUT A = H INPUT B = H OUTPUT WAVE TRAINS (TERM 6) INPUT C = H (MSB) INPUT D = H * AN OUTPUT BIT MAY BE FILLED IN THIS COUNTER STATE BY A LESS SIGNIFICANT CD4089 CASCADED IN THE ADD MODE FIGURE 4. TIMING DIAGRAM 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC 0 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics FIGURE 8. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-1072 CD4089BMS 200 (Continued) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics 150 SUPPLY VOLTAGE (VDD) = 15V 10V 100 5V 50 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) POWER DISSIPATION PER (PD) (µW) SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 0 0 100 FIGURE 9. TYP. PROPAGATION DELAY TIMES AS FUNCTION OF LOAD CAPACITANCE (CLOCK OR STROBE TO OUT) 105 8 200 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 10. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 104 8 10V 6 4 10V 2 103 5V 8 6 4 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 2 4 68 1 2 4 68 2 4 68 2 4 68 103 10 102 INPUT FREQUENCY (fIN) (kHz) 2 4 68 104 FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1073