Ultra Low Noise, Precision Voltage Reference ISL21090 Features The ISL21090 is a ultra low noise, high DC accuracy precision voltage reference with wide input voltage range from 4.7V to 36V. The ISL21090 uses the new Intersil Advanced Bipolar technology to achieve sub 2µVP-P 0.1Hz noise with an initial voltage accuracy of 0.02%. • Reference Output Voltage Option - 2.5V (Released) - 1.25V, 3.3V, 4.096V, 5V, 7V and 10V (Coming Soon) • Initial Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±0.02% The ISL21090 offers a 2.5V output voltage option with 7ppm/°C temperature coefficient and also provides excellent line and load regulation. The device is offered in an 8 Ld SOIC package. • Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930µA (Typ) The ISL21090 is ideal for high-end instrumentation, data acquisition and processing applications requiring high DC precision where low noise performance is critical. • Output Voltage Noise . . . . . . . . . . . 1.9µVP-P Typ (0.1Hz to 10Hz) (2.5V Option) • Tempco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7ppm/°C Max (3ppm/°C Coming Soon) • Output Current Capability . . . . . . . . . . . . . . . . . . . . . . . . 20mA • Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/V • Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5ppm/mA • Operating Temperature Range. . . . . . . . . . .-40°C to +125°C Applications • High-End Instrumentation • Precision Voltage Sources for Data Acquisition System, Industrial Control, Communication Infrastructure • Process Control and Instrumentations 1 VIN 2 10µF 0.1µF 3 4 DNC DNC VIN DNC COMP GND VOUT TRIM 8 7 VREF 2.5010 6 5 TYPICAL TEMPERATURE 2.5005 COEFFICIENT CURVE FOR 10 UNITS 0.1µF VDD SERIAL CLOCK CHIP SELECT SERIAL DATA I/O VREF SCLK OUTxS CSb OUTxF SDIO VOUT (V) 2.5000 DACOUTx 2.4980 -55 GND -35 -15 5 25 45 65 85 105 125 145 TEMPERATURE (°C) FIGURE 1. ISL21090 TYPICAL APPLICATION DIAGRAM 1 2.4990 2.4985 DAC June 8, 2011 FN6993.0 2.4995 FIGURE 2. VOUT vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL21090 Pin Configuration ISL21090 (8 LD SOIC) TOP VIEW 1 DNC DNC VIN DNC 7 2 3 4 8 COMP GND VOUT TRIM 6 5 Pin Descriptions PIN NUMBER PIN NAME 1 DNC Do Not Connect 2 VIN Input Voltage Connection 3 COMP 4 GND Ground Connection 5 TRIM Voltage Reference Trim input 6 VOUT Voltage Reference Output 7 DNC Do Not Connect 8 DNC Do Not Connect 2 DESCRIPTION Compensation and Noise Reduction Capacitor FN6993.0 June 8, 2011 ISL21090 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL21090BFB825Z-TK PART MARKING 21090 BFZ25 VOUT OPTION (V) GRADE (%) TEMPCO (ppm/°C) TEMP RANGE (°C) 2.5 0.02 7 -40 to +125 PACKAGE TAPE & REEL (Pb-Free) 8 Ld SOIC PKG. DWG. # M8.15E NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL21090. For more information on MSL please see Tech Brief TB363. 3 FN6993.0 June 8, 2011 ISL21090 Absolute Maximum Ratings Thermal Information Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +40V VOUT to GND (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VOUT + 0.5V Voltage on any Pin to Ground . . . . . . . . . . . . . . . . . . . -0.5V to +VOUT + 0.5V Voltage on DNC pins . . . . . . . . . . . . . . . No connections permitted to these pins Input Voltage Slew Rate (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1V/µs ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . 115 58 Continuous Power Dissipation (TA = +125°C) . . . . . . . . . . . . . . . . .217mW Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile (Note 6). . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. 6. Post-reflow drift for the ISL21090 devices can exceed 100µV to 1.0mV based on experimental results with devices on FR4 double sided boards. The engineer must take this into account when considering the reference voltage after assembly. Electrical Specifications temperature range,-40°C to +125°C. PARAMETER VIN = 5V (2.5V option), IOUT = 0, unless otherwise specified. Boldface limits apply over the operating DESCRIPTION CONDITIONS VOUT Output Voltage VIN = 5V VOA VOUT Accuracy @ TA = +25°C All VOUT options TC VOUT Output Voltage Temperature Coefficient ISL21090 B grade VIN Input Voltage Range (Note 9) VOUT = 2.5V IIN Supply Current ΔVOUT /ΔVIN Line Regulation ΔVOUT/ΔIOUT Load Regulation MIN (Note 7) TYP MAX (Note 7) 2.5 V +0.02 % 7 ppm/°C 36 V 0.930 1.28 mA VIN = 4.7V to 36V, VOUT = 2.5V 8 18 ppm/V Sourcing: 0mA ≤ IOUT ≤ 20mA 2.5 17 ppm/mA Sinking: -10mA ≤ IOUT ≤ 0mA 2.5 17 ppm/mA Dropout Voltage (Note 8) VOUT = 2.5V @ 10mA 1.1 1.7 V ISC+ Short Circuit Current TA = +25°C, VOUT tied to GND 55 mA ISC- Short Circuit Current TA = +25°C, VOUT tied to VIN -61 mA tR Turn-on Settling Time 90% of final value, CL = 1.0µF, CC = open 150 µs Ripple Rejection f = 120Hz 90 dB eN Output Voltage Noise 0.1Hz ≤ f ≤ 10Hz, VOUT = 2.5V 1.9 µVP-P VN Broadband Voltage Noise 10Hz ≤ f ≤ 1kHz, VOUT = 2.5V 1.6 µVRMS Noise Density f = 1kHz, VOUT = 2.5V 50 nV/√Hz Long Term Stability TA = +25°C 20 ppm VD ΔVOUT/Δt -0.02 UNIT 4.7 NOTES: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. VIN-VOUT measured at the point where VOUT drops 1mV from the nominal measured value. 9. Coming soon: VIN (MIN) = 3.7V 4 FN6993.0 June 8, 2011 ISL21090 Typical Performance Curves (ISL21090-2.5) 1300 1000 1200 980 UNIT 3 1100 IIN (µA) IIN (µA) 960 940 UNIT 1 920 900 800 900 UNIT 2 700 19 600 4 880 4 9 14 24 VIN (V) 29 34 39 FIGURE 3. IIN vs VIN, THREE UNITS 2.500290 9 14 19 34 39 2.499800 VOUT (V) 2.499990 UNIT 2 UNIT 3 2.499890 2.499600 +125°C 2.499400 -40°C 2.499200 2.499000 2.499790 6 9 12 15 18 21 24 27 30 33 36 39 2.498800 4 9 14 19 VIN (V) FIGURE 5. LINE REGULATION, THREE UNITS 30 30 20 20 10 CL = 1nF 0 24 VIN (V) 29 34 39 FIGURE 6. LINE REGULATION, THREE TEMPERATURES AMPLITUDE (mV) AMPLITUDE (mV) 29 +25°C 2.500000 2.500090 -10 10 CL = 100nF 0 -10 -20 -20 -30 24 VIN (V) 2.500200 UNIT 1 2.500190 2.499690 3 -40°C FIGURE 4. IIN vs VIN, THREE TEMPERATURES 2.500390 VOUT (V) +125°C +25°C 1000 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 7. LINE TRANSIENT WITH 1nF LOAD (ΔVIN = ±500mV) 5 -30 0 10 20 30 40 50 60 70 80 90 100 TIME (µs) FIGURE 8. LINE TRANSIENT WITH 100nF LOAD (ΔVIN = ±500mV) FN6993.0 June 8, 2011 ISL21090 Typical Performance Curves (ISL21090-2.5) (Continued) 6 30 20 4 AMPLITUDE (mV) +25°C VOUT (µV) 10 0 -40°C -10 -20 +125°C 0 -2 CL = 100nF -20 -15 -10 -5 0 5 ILOAD (mA) (SOURCING) 10 15 -6 20 0 5 5 3 2 CL = 0.1µF 1 0 350 VIN CL = 1µF 1 -1 0 300 400 50 100 150 TIME (µs) 250 300 350 400 FIGURE 12. TURN-ON TIME WITH 1µF 1000.0 0 CL = NO LOAD 100.0 -20 CL = 100nF -40 PSRR (dB) 10.0 ZOUT (Ω) 200 TIME (µs) FIGURE 11. TURN-ON TIME WITH 0.1µF CL = 10nF 1.0 0.1 CL = 10nF -60 CL = 1nF -80 -100 0.01 0.001 10 120 2 -1 250 100 3 0 200 80 4 VIN VOUT (V) VOUT (V) 4 150 60 FIGURE 10. LOAD TRANSIENT (ΔVIN = ±1mA) 6 100 40 TIME (µs) 6 50 20 (SINKING) FIGURE 9. LOAD REGULATION, THREE TEMPERATURES 0 CL = 1µF -4 -30 -40 -25 CL = NO LOAD 2 100 -120 CL = 100nF CL = 1nF 1k 10k 100k FREQUENCY (Hz) FIGURE 13. ZOUT vs FREQUENCY 6 1M 10M -140 10 CL = NO LOAD 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 14. RIPPLE REJECTION AT DIFFERENT CAPACITIVE LOADS FN6993.0 June 8, 2011 ISL21090 Typical Performance Curves (ISL21090-2.5) (Continued) 2.5010 90 TYPICAL TEMPERATURE 2.5005 COEFFICIENT CURVE FOR 10 UNITS -40°C CURRENT (mA) 80 VOUT (V) 2.5000 2.4995 2.4990 2.4985 70 60 +25°C 50 40 2.4980 -55 -35 -15 5 25 45 65 85 105 125 145 30 +125°C 3 8 TEMPERATURE (°C) 13 18 23 28 33 38 VIN (V) FIGURE 15. VOUT vs TEMPERATURE, 10 UNITS FIGURE 16. SHORT-CIRCUIT TO VIN X = 10s/DIV Y = 1µV/DIV -30 CURRENT (mA) -35 -40 +125°C -45 +25°C -50 -55 -40°C -60 -65 3 8 13 18 23 VIN (V) 28 FIGURE 17. SHORT-CIRCUIT TO GND 7 33 38 FIGURE 18. VOUT vs NOISE, 0.1Hz to 10Hz FN6993.0 June 8, 2011 ISL21090 Device Operation Bandgap Precision References The ISL21090 uses a bandgap architecture and special trimming circuitry to produce a temperature compensated, precision voltage reference with high input voltage capability and moderate output current drive. Applications Information Board Mounting Considerations For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package, which subjects the die to mild stresses when the printed circuit (PC) board is heated and cooled, which slightly changes the shape. Because of these die stresses, placing the device in areas subject to slight twisting can cause degradation of reference voltage accuracy. It is normally best to place the device near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. Mounting the device in a cutout also minimizes flex. Obviously, mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy. Board Assembly Considerations Some PC board assembly precautions are necessary. Normal output voltage shifts of 100µV to 500µV can be expected with Pb-free reflow profiles or wave solder on multi-layer FR4 PC boards. Precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures. Noise Performance and Reduction The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 1.9µVP-P (VOUT = 2.5V). The noise measurement is made with a bandpass filter. The filter is made of a 1-pole high-pass filter, with a corner frequency at 0.1Hz, and a 2-pole low-pass filter, with a corner frequency (3dB) at 9.9Hz, to create a filter with a 9.9Hz bandwidth. Noise in the 10Hz to 1kHz bandwidth is approximately 1.6µVRMS (VOUT = 2.5V), with 0.1µF capacitance on the output. This noise measurement is made with a 2 decade bandpass filter. The filter is made of a 1-pole high-pass filter with a corner frequency at 10Hz of the center frequency, and 1-pole low-pass 8 filter with a corner frequency at 1kHz. Load capacitance up to 10µF can be added but will result in only marginal improvements in output noise and transient response. Turn-On Time Normal turn-on time is typically 150µs, as shown in Figure 12. The circuit designer must take this into account when looking at power-up delays or sequencing. Temperature Coefficient The limits stated for temperature coefficient (Tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH – VLOW), and divide by the temperature extremes of measurement (THIGH – TLOW). The result is divided by the nominal reference voltage (at T = +25°C) and multiplied by 106 to yield ppm/°C. This is the “Box” method for specifying temperature coefficient. Output Voltage Adjustment The output voltage can be adjusted above and below the factory-calibrated value via the trim terminal. The trim terminal is the negative feedback divider point of the output op amp. The positive input of the amplifier is about 1.216V, and in feedback, so will be the trim voltage. The trim terminal has a 5000Ω resistor to ground internally, and in the case of the 2.5V output version, there is a feedback resistor of approximately 5000Ω from VOUT to trim. The suggested method to adjust the output is to connect a very high value external resistor directly to the trim terminal and connect the other end to the wiper of a potentiometer that has a much lower total resistance and whose outer terminals connect to VOUT and ground. If a 1MΩ resistor is connected to trim, the output adjust range will be ±6.3mV. It is important to minimize the capacitance on the trim terminal to preserve output amplifier stability. It is also best to connect the series resistor directly to the trim terminal, to minimize that capacitance and also to minimize noise injection. Small trim adjustments will not disturb the factory-set temperature coefficient of the reference, but trimming near the extreme values can. FN6993.0 June 8, 2011 ISL21090 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION June 8, 2011 FN6993.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL21090 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN6993.0 June 8, 2011 ISL21090 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 10 FN6993.0 June 8, 2011