Radiation Hardened Ultra Low Noise, Precision Voltage Reference ISL71090SEH75 Features The ISL71090SEH75 is an ultra low noise, high DC accuracy precision voltage reference with a wide input voltage range from 9.2V to 30V. The ISL71090SEH75 uses the Intersil Advanced Bipolar technology to achieve sub 1.0µVP-P noise at 0.1Hz with an accuracy over temperature of 0.15%. • Reference output voltage . . . . . . . . . . . . . . . . . . 7.5V ±0.05% • Accuracy over temperature . . . . . . . . . . . . . . . . . . . . . .±0.15% The ISL71090SEH75 offers a 7.5V output voltage with 10ppm/°C temperature coefficient and also provides excellent line and load regulation. The device is offered in an 8 Ld Flatpack package. The ISL71090SEH75 is ideal for high-end instrumentation, data acquisition and applications requiring high DC precision where low noise performance is critical. Applications • RH voltage regulators precision outputs • Precision voltage sources for data acquisition system for space applications • Strain and pressure gauge for space applications • Output voltage noise . . . . . . . . .1.0µVP-P Typ (0.1Hz to 10Hz) • Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930µA (Typ) • Tempco (box method) . . . . . . . . . . . . . . . . . . . 10ppm/°C Max • Output current capability . . . . . . . . . . . . . . . . . . . . . . . . 20mA • Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/V • Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10ppm/mA • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation environment - High dose rate (50-300rad(Si)/s) . . . . . . . . . . . 100krad(Si) - Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 100krad(Si)* - SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm2/mg *Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer by wafer basis to 50krad(Si) at low dose rate • Electrically screened to SMD 5962-13211 Related Literature • AN1847, “ISL71090SEHxx User’s Guide” • AN1848, “Single Event Effects (SEE) Testing of the ISL71090SEH Precision Voltage Reference” • AN1849, “Total Dose Testing of the ISL71090SEH Precision Voltage Reference” ISL71090SEH75 2 VIN 0.1µF 3 1nF 4 DNC DNC VIN DNC COMP VOUT GND TRIM 8 7 7.510 VREF 7.506 5 1µF C REFIN DACOUT VDD VDD D12 VEE VEE D0 BIPOFF NOTE: Select C to minimize settling time. 1.1k GND 7.502 7.500 UNIT 2 UNIT 5 UNIT 3 UNIT 1 UNIT 4 7.498 7.494 7.492 7.490 -80 HS-565BRH 1 7.504 7.496 7.5V - 0.1% -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 1. ISL71090SEH75 TYPICAL APPLICATION DIAGRAM December 2, 2013 FN8591.2 7.5V + 0.1% 7.508 6 VOUT (V) 1 FIGURE 2. VOUT vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL71090SEH75 Ordering Information ORDERING NUMBER (Notes 1, 2) PART NUMBER VOUT OPTION (V) TEMP RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962R1321104VXC ISL71090SEHVF75 7.5 -55 to +125 8 Ld Flatpack K8.A ISL71090SEHF75/PROTO ISL71090SEHF75/PROTO 7.5 -55 to +125 8 Ld Flatpack K8.A 5962R1321104V9A ISL71090SEHVX75 7.5 -55 to +125 DIE ISL71090SEHX75SAMPLE ISL71090SEHX75SAMPLE 7.5 -55 to +125 DIE ISL71090SEHF75EVAL1Z Evaluation Board NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in this “Ordering Information” table must be used when ordering. Pin Configuration ISL71090SEH75 (8 LD FLATPACK) TOP VIEW DNC 1 8 DNC DNC VIN 2 7 COMP 3 6 VOUT GND 4 5 TRIM NOTE: The ESD triangular mark is indicative of pin #1. It is a part of the device marking and is placed on the lid in the quadrant where pin #1 is located. Pin Descriptions PIN NUMBER PIN NAME ESD CIRCUIT DESCRIPTION 1, 7, 8 DNC 3 Do not Connect. Internally terminated. 2 VIN 1 Input Voltage Connection 3 COMP 2 Compensation and Noise Reduction Capacitor 4 GND 1 Ground Connection. Also connected to the lid. 5 TRIM 2 Voltage Reference Trim input 6 VOUT 2 Voltage Reference Output VDD VDD CAPACITIVELY TRIGGERED CLAMP VDD PIN DNC GND GND ESD CIRCUIT 1 2 ESD CIRCUIT 2 ESD CIRCUIT 3 FN8591.2 December 2, 2013 ISL71090SEH75 Functional Block Diagram VIN BIAS REGULATOR DNC BAND GAP REFERENCE DNC 3.7V DNC 1.2V Gm VOUT GND COMP TRIM 1.2V 3 FN8591.2 December 2, 2013 ISL71090SEH75 Absolute Maximum Ratings Thermal Information Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +40V VIN to GND at an LET = 86MeV•cm2/mg . . . . . . . . . . . . . . -0.5V to +36V VOUT to GND (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VOUT + 0.5V Voltage on any Pin to Ground . . . . . . . . . . . . . . . . . -0.5V to +VOUT + 0.5V Voltage on DNC Pins . . . . . . . . . . . . No connections permitted to these pins ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld Flatpack Package (Notes 3, 4). . . . . . 140 15 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile (Note 5). . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2V to +30V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For θJC, the "case temp" location is the center of the ceramic on the package underside. 5. Post-reflow drift for the ISL71090SEH75 devices can be 100µV typical based on experimental results with devices on FR4 double sided boards. The engineer must take this into account when considering the reference voltage after assembly. 6. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate. 7. The output capacitance used for SEE testing is CIN = 0.1µF and COUT = 1µF. Electrical Specifications For Flatpack VIN = 15V, IOUT = 0mA, CL = 0.1µF and CC = 1nF unless otherwise specified. Boldface limits apply over the operating temperature range, -55°C to +125°C. PARAMETER DESCRIPTION CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNIT % VOUT Output Voltage VOA VOUT Accuracy @ TA = +25°C ) VOUT = 7.5V -0.05 +0.05 VOA VOUT Accuracy @ TA = -55°C to +125°C VOUT = 7.5V -0.15 +0.15 % VOA VOUT Accuracy, Post Rad -0.3 +0.3 % 10 ppm/°C TC VOUT 7.5 VOUT = 7.5V Output Voltage Temperature Coefficient (Note 9) V VIN Input Voltage Range IIN Supply Current ΔVOUT /ΔVIN Line Regulation VIN = 9.2V to 30V 8 20 ppm/V ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA ≤ IOUT ≤ 20mA 10 20 ppm/mA 21 40 ppm/mA 1.5 1.7 V 9.2 0.930 Sinking: -10mA ≤ IOUT ≤ 0mA VD Dropout Voltage (Note 10) 30 V 1.5 mA ISC+ Short Circuit Current TA = +25°C, VOUT tied to GND 53 mA ISC- Short Circuit Current TA = +25°C, VOUT tied to VIN -63 mA tR Turn-on Settling Time 90% of final value, CL = 1.0µF, CC = open 250 µs PSRR Ripple Rejection f = 120Hz 90 dB eN Output Voltage Noise 0.1Hz ≤ f ≤ 10Hz 1.0 µVP-P VN Broadband Voltage Noise 10Hz ≤ f ≤ 1kHz 1.2 µVRMS Noise Density f = 1kHz, VIN = 9.5V 38 nV/√Hz Long Term Drift TA = +125°C, 1000hrs 15 ppm ΔVOUT/Δt 4 FN8591.2 December 2, 2013 ISL71090SEH75 Electrical Specifications For Die VIN = 15V, IOUT = 0mA, CL = 0.1µF and CC = 1nF unless otherwise specified. Boldface limits apply over the operating temperature range, -55°C to +125°C. PARAMETER DESCRIPTION VOUT Output Voltage CONDITIONS MIN (Note 8) TYP MAX (Note 8) 7.5 UNIT V VOA VOUT Accuracy @ TA = +25°C (Note 11) VOUT = 7.5V (Note 11) -0.05 +0.05 % VOA VOUT Accuracy @ TA = -55°C to +125°C VOUT = 7.5V (Note 11) (Note 11) -0.15 +0.15 % VOA VOUT Accuracy, Post Rad -0.3 +0.3 % 10 ppm/°C TC VOUT VOUT = 7.5V Output Voltage Temperature Coefficient (Note 9) VIN Input Voltage Range IIN Supply Current 9.2 0.930 30 V 1.5 mA ΔVOUT /ΔVIN Line Regulation VIN = 9.2V to 30V 8 20 ppm/V ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA ≤ IOUT ≤ 20mA 10 20 ppm/mA 21 40 ppm/mA VD Dropout Voltage (Note 10) 1.5 1.7 V Sinking: -10mA ≤ IOUT ≤ 0mA NOTES: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 9. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT(max) - VOUT(min) is divided by the temperature range; in this case, -55°C to +125°C = +180°C. 10. Dropout Voltage is the minimum VIN - VOUT differential voltage measured at the point where VOUT drops 1mV from VIN = nominal at TA = +25°C 11. The VOUT accuracy is based on die mount with Silver Glass die attach material such as "QMI 2569" or equivalent in a package with an Alumina ceramic substrate 5 FN8591.2 December 2, 2013 ISL71090SEH75 Typical Performance Curves V OUT = 7.5V, TA = +25°C, COUT = 1µF, COMP = 1nF, unless otherwise specified. 3.5 7.510 LINE REGULATION (ppm/V) 7.5V + 0.1% 7.508 7.506 VOUT (V) 7.504 7.502 VOUT (V) 0mA, +25°C 7.500 7.498 VOUT (V) 0mA, +125°C 7.496 7.494 VOUT (V) 0mA, -55°C 7.492 7.490 7.5V - 0.1% 0 5 10 15 20 VIN (V) 25 30 3.0 LINE REG ppm/V M-55°C 2.0 1.5 1.0 0.5 0.0 0 35 LINE REG ppm/V +125°C 2.5 LINE REG ppm/V +25°C 5 10 15 20 25 30 35 VIN (V) FIGURE 3. VOUT ACCURACY OVER TEMPERATURE FIGURE 4. LINE REGULATION OVER TEMPERATURE AT VIN = 5V (ppm/mA) 7.510 7.508 7.5V -0.1% 7.5V +0.1% VOUT (V) 0mA +25°C VOUT (V) 20mA +25°C VOUT (V) -10mA +25°C VOUT (V) 0mA +125°C VOUT (V) 20mA +125°C VOUT (V) -10mA +125°C VOUT (V) 0mA -55°C VOUT (V) 20mA -55°C VOUT (V) -10mA -55°C 7.506 VOUT (V) 7.504 7.502 7.500 7.498 7.496 7.494 7.492 7.490 0 5 10 15 20 VIN (V) 25 30 35 FIGURE 5. VOUT vs VIN at 0mA, 20mA AND -10mA 20 7.510 7.508 7.506 VOUT (V), +25°C 7.504 VOUT (V) LOAD REGULATION (ppm/mA) 7.5V + 0.1% 7.502 7.500 7.498 7.496 VOUT (V), +125°C VOUT (V), -55°C 7.494 7.492 7.490 -10 7.5V - 0.1% -5 0 5 10 IOUT (mA) 15 20 25 FIGURE 6. LOAD REGULATION OVER TEMPERATURE AT VIN = 9.2V 6 LOAD REG ppm/mA (VIN = 5V, +125°C) 15 10 LOAD REG ppm/mA (VIN = 5V, -55°C) 5 0 -5 -10 -15 -10 LOAD REG ppm/mA (VIN = 5V, +25°C) -5 0 5 10 15 20 25 IOUT (mA) FIGURE 7. LOAD REGULATION OVER TEMPERATURE AT VIN = 9.2V (ppm/mA) FN8591.2 December 2, 2013 ISL71090SEH75 Typical Performance Curves V OUT = 7.5V, TA = +25°C, COUT = 1µF, COMP = 1nF, unless otherwise specified. 1.6 1.4 +25°C DROPOUT (V) 1.2 1.0 0.8 VOUT +125°C 20mV/Div VIN = 9V VOUT = 7.5V VOUT 0mA TO 1mA SLEW RATE: 2mA/µs COUT = 1µF COMP = 1000pF 0.6 0.4 +150°C 0.2 0.0 0.0 0.005 0.010 0.015 IOUT (A) 0.020 0.025 100µs/Div FIGURE 8. DROPOUT VOLTAGE FOR 7.5V FIGURE 9. LOAD TRANSIENT 0 TO 1mA 7.510 1.E-05 f = 1kHz En = 37.5nV/√Hz VIN = 9.5V VOUT = 7.5V RI = OPEN 7.506 VOUT (V) 7.504 1.E-07 7.502 7.500 UNIT 2 UNIT 5 UNIT 3 UNIT 4 7.498 7.494 7.492 1.E-09 0.1 UNIT 1 7.496 1.E-08 1 10 100 1k 10k 100k 7.490 -80 7.5V - 0.1% -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 10. NOISE DENSITY vs FREQUENCY (VIN = 9.5V, VOUT = 7.5V, IOUT = 0mA FIGURE 11. VOUT vs TEMPERATURE 0 -10 -20 -30 PSRR (dB) NOISE (V/√Hz) 1.E-06 7.5V + 0.1% 7.508 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 12. PSRR (+25°C, VIN = 9.5V, VOUT = 7.5V, IOUT = 0mA, CIN = 0.1µF, COUT = 1.0µF, COMP = 1nF, VSIG = 300mVP-P) 7 FN8591.2 December 2, 2013 ISL71090SEH75 Device Operation Output Voltage Adjustment Bandgap Precision Reference The output voltage can be adjusted above and below the factory-calibrated value via the trim terminal. The trim terminal is the negative feedback divider point of the output op amp. The positive input of the amplifier is about 1.216V, and in feedback, so will be the trim voltage. The suggested method to adjust the output is to connect a 1MΩ external resistor directly to the trim terminal and connect the other end to the wiper of a potentiometer that has a 100kΩ resistance and whose outer terminals connect to VOUT and ground. If a 1MΩ resistor is connected to trim, the output adjust range will be ±6.3mV. The TRIM pin should not have any capacitor tied to its output, also it is important to minimize the capacitance on the trim terminal during layout to preserve output amplifier stability. It is also best to connect the series resistor directly to the trim terminal to minimize that capacitance and also to minimize noise injection. Small trim adjustments will not disturb the factory-set temperature coefficient of the reference, but trimming near the extreme values can. The ISL71090SEH75 uses a bandgap architecture and special trimming circuitry to produce a temperature compensated, precision voltage reference with high input voltage capability and moderate output current drive. Applications Information Board Mounting Considerations For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a ceramic flatpack package. Generally, mild stresses to the die when the printed circuit (PC) board is heated and cooled, can slightly change the shape. Because of these die stresses, placing the device in areas subject to slight twisting can cause degradation of reference voltage accuracy. It is normally best to place the device near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. Mounting the device in a cutout also minimizes flex. Obviously, mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy. Board Assembly Considerations Some PC board assembly precautions are necessary. Normal output voltage shifts of typically 100µV can be expected with Pb-free reflow profiles or wave solder on multi-layer FR4 PC boards. Precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures. Output Stage The output stage of the device has a push pull configuration with an high side PNP and a low side NPN. This helps the device to act as a source and sink. The device can source 20mA. Use of COMP Cap The reference can be compensated for the COUT capacitors used by adding a capacitor from COMP pin to GND. See Table 1 for recommended values. of the COMP capacitor. TABLE 1. Noise Performance and Reduction The output noise voltage over the 0.1Hz to 10Hz bandwidth is typically 1.0µVP-P (VOUT = 7.5V). The noise measurement is made with a 9.9Hz bandpass filter. Noise in the 10Hz to 1kHz bandwidth is approximately 1.2µVRMS, with 1µF capacitance on the output. This noise measurement is made with a band pass filter of 990Hz. Load capacitance up to 10µF (with COMP capacitor listed in Table 1) can be added but will result in only marginal improvements in output noise and transient response. Turn-On Time Normal turn-on time is typically 250µs, the circuit designer must take this into account when looking at power-up delays or sequencing. Temperature Coefficient The limits stated for temperature coefficient (Tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures which provide for the maximum voltage deviation and take the total variation, (VHIGH - VLOW), this is then divided by the temperature extremes of measurement (THIGH – TLOW). The result is divided by the nominal reference voltage (at T = +25°C) and multiplied by 106 to yield ppm/°C. This is the “Box” method for specifying temperature coefficient. 8 COUT (µF) CCOMP (nF) 0.1 1 1 1 10 10 SEE Testing The SET result is based on the ISL71090SEH25. The ISL71090SEH25 and ISL71090SEH75 share the same active circuitry consisting of a precision bandgap ckt and a trimmable amplifier to set the output reference with only a resistor change to scale the output. The SET test was done under an ion beam having an LET of 86MeV•cm2/mg. The device did not latch up or burn out to a VDD of 36V and at +125°C. Single Event transients were observed and are summarized in the Table 2: TABLE 2. VIN (V) IOUT (mA) COUT (µF) SET (% VOUT) 4 5 1 -4.6 30 5 1 -4.4 30 5 10 -1.0 DNC Pins These pins are for trimming purpose and for factory use only. Do not connect these to the circuit in any way. It will adversely effect the performance of the reference. FN8591.2 December 2, 2013 ISL71090SEH75 Package Characteristics TOP METALLIZATION Type: AlCu (99.5%/0.5%) Thickness: 30kÅ Weight of Packaged Device 0. 31 Grams (Typical) BACKSIDE FINISH Lid Characteristics Silicon Finish: Gold Potential: Connected to lead #4 (GND) Case Isolation to Any Lead: 20 x 109 Ω (min) ASSEMBLY RELATED INFORMATION SUBSTRATE POTENTIAL Floating Die Characteristics ADDITIONAL INFORMATION Die Dimensions 1464µm x 1744µm (58mils x 69mils) Thickness: 483µm ± 25µm (19mils ± 1 mil) WORST CASE CURRENT DENSITY <2 x 105 A/cm2 Interface Materials PROCESS Dielectrically Isolated Advanced Bipolar Technology- PR40 SOI GLASSIVATION Type: Nitrox Thickness: 15kÅ Metallization Mask Layout DNC DNC DNC VS COMP VOUT SENSE GND POWR VOUT FORCE GND QUIET 9 (see Note 12, Table 3) TRIM FN8591.2 December 2, 2013 ISL71090SEH75 TABLE 3. DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) BOND WIRES PER PAD GND PWR 2 -104 0 1 GND QUIET 1 0 0 1 COMP 3 -108 589 1 VS 4 -125 1350 1 DNC 5 -108 1452 1 DNC 6 1089 1452 1 DNC 7 1089 1350 1 VOUT SENSE 8 1072 598 1 VOUT FORCE 9 1088 1 1 TRIM 10 985 -25 1 NOTES: 12. Origin of coordinates is the centroid of GND QUIET. 13. Bond wire size is 1.0 mil. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE December 2, 2013 FN8591.2 Electrical spec table on page 4 (Flatpack) and page 5 (Die): VOUT Accuracy Post Rad section, changed the value for Min from -0.25% to -0.3% and Max from +0.25% to +0.3%. October 4, 2013 FN8591.1 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN8591.2 December 2, 2013 ISL71090SEH75 Package Outline Drawing K8.A 8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 3, 3/13 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 0.050 (1.27 BSC) 0.005 (0.13) MIN 4 PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.110 (2.79) 0.087 (2.21) 0.265 (6.73) 0.245 (6.22) TOP VIEW 0.036 (0.92) 0.026 (0.66) 0.009 (0.23) 0.004 (0.10) 6 0.265 (6.75) 0.245 (6.22) -D- -H- -C- 0.180 (4.57) 0.170 (4.32) SEATING AND BASE PLANE 0.370 (9.40) 0.325 (8.26) 0.03 (0.76) MIN SIDE VIEW 0.007 (0.18) 0.004 (0.10) NOTES: LEAD FINISH 0.009 (0.23) BASE METAL 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 2. If a pin one identification mark is used in addition to a tab, the limits of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 4. Measure dimension at all four corners. 3 SECTION A-A 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. 5. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 6. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 8. Controlling dimension: INCH. 11 FN8591.2 December 2, 2013