High Speed Quad SPST CMOS Analog Switch HI-201HS/883 Features The HI-201HS/883 is a monolithic CMOS analog switch featuring very fast switching speeds and low ON resistance. This integrated circuit consists of four independently selectable SPST switches and is pin compatible with the industry standard HI-201 switch. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Fabricated using silicon-gate technology and the Intersil dielectric isolation process, this TTL compatible device offers improved performance over previously available CMOS analog switches while eliminating the problem of latch-up associated with other fabrication processes. Featuring maximum switching times of 50ns, low ON resistance of 50Ω maximum, and a wide analog signal range, the HI-201HS/883 is designed for any military application where improved switching performance, particularly switching speed, is required. (A more detailed discussion on the design and application of the HI-201HS/883 can be found in Application Note AN543.) The HI-201HS/883 is available in a 16 Ld CerDIP package and is specified over the temperature range of -55°C to +125°C. • Low “On” Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Ω Max • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns • Analog Current Range (Continuous) . . . . . . . . . . . . . . . 25mA • TTL/CMOS Compatible • No Latch-Up • Pin Compatible with Standard HI-201 Applications • High Speed Multiplexing • High Frequency Analog Switching • Sample and Hold Circuits • Digital Filters • Op Amp Gain Switching Networks • Integrator Reset Circuits Functional Diagram Pin Configuration V+ HI1-0201HS/883 (16 LD CERDIP) TOP VIEW SOURCE A1 1 16 A2 OUT1 2 15 OUT2 IN1 3 14 IN2 V- 4 13 V+ GND 5 12 NC IN4 6 11 IN3 OUT4 7 10 OUT3 A4 8 TTL LOGIC INPUT SWITCH CELL DRAIN V- Ordering Information 9 A3 PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HI1-0201HS/883 HI1-201HS/883 -55 to +125 16 Ld CerDIP F16.3 TRUTH TABLE LOGIC SWITCH 0 1 ON OFF 1 GATE INPUT GATE OUTPUT PART NUMBER April 9, 2012 FN8265.0 LEVEL SHIFTER AND DRIVER CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HI-201HS/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V ±VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V Analog Input Voltage, (+VS ). . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +2V Analog Input Voltage, (-VS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V Digital Input Voltage, (+VA) . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V Digital Input Voltage, (-VA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V Peak Current (S or D) (Pulse at 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 50mA Continuous Current Any Terminal (Except S or D) . . . . . . . . . . . . . . . 25mA Thermal Resistance θJA (°C/W) θJC (°C/W) CerDIP Package . . . . . . . . . . . . . . . . . . . . . . 75 16 Package Power Dissipation at +75°C CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Package Power Dissipation Derating Factor above +75°C CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.36mW/°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .≤275°C Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Operating Supply Voltage Range (±VSUPPLY) . . . . . . . . . . . . . . . . . . . .±15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0V to +VSUPPLY CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V, unless otherwise specified. D.C. PARAMETERS Switch “ON” Resistance SYMBOL rDS CONDITIONS VA = 0.8V, VS = 10V, ID = -1mA All Unused Channels VAL = 0.8V VA = 0.8V, VS = -10V, ID = 1mA All Unused Channels VAL = 0.8V Source “OFF” Leakage Current IS(OFF) VS = +14V, VD = -14V, VAH = 3.0V All Unused Channels VAH = 3.0V, VD = +14V, VS = -14V VS = -14V, VD = +14V, VAH = 3.0V All Unused Channels VAH = 3.0V, VD = -14V, VS = +14V Drain “OFF” Leakage Current ID(OFF) VD = -14V, VS = +14V, VAH = 3.0V All Unused Channels VAH = 3.0V, VD = +14V, VS = -14V VD = +14V, VS = -14V, VAH = 3.0V All Unused Channels VAH = 3.0V, VD = -14V, VS = +14V Channel “ON” Leakage Current ID(ON) VD = VS = +14V, VAL = 0.8V, All Unused Channels VAL = 0.8V, VD = VS = -14V VD = VS = -14V, VAL = 0.8V, All Unused Channels VAL = 0.8V, VD = VS = +14V GROUP A SUBGROUPS TEMPERATURE (°C) MIN MAX UNITS 1 +25 - 50 Ω 2, 3 -55 to +125 - 75 Ω 1 +25 - 50 Ω 2, 3 -55 to +125 - 75 Ω 1 +25 -10 10 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -10 10 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -10 10 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -10 10 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -10 10 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -10 10 nA 2, 3 -55 to +125 -100 100 nA 1 +25 - 500 µA 2, 3 Low Level Input Current IAL VAL = 0.8V All Unused Channels VAH = 4.0V -55 to +125 - 500 µA High Level Input Current IAH VAH = 4.0V All Unused Channels VAL = 0.8V 1 +25 - 40 µA 2, 3 -55 to +125 - 40 µA All Channels VAL = 0.8V 1, 2 +25, +125 - 10 mA 3 -55 - 10 mA All Channels VAH = 3.0V 1, 2 +25, +125 - 10 mA 3 -55 - 10 mA Supply Current +ICC 2 FN8265.0 April 9, 2012 HI-201HS/883 TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V, unless otherwise specified. D.C. PARAMETERS SYMBOL Supply Current -ICC CONDITIONS GROUP A SUBGROUPS TEMPERATURE (°C) MIN MAX UNITS 1, 2 +25, +125 - 6 mA 3 -55 - 6 mA 1, 2 +25, +125 - 6 mA 3 -55 - 6 mA All Channels VAL = 0.8V All Channels VAH = 3.0V TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V, unless otherwise specified. PARAMETERS SYMBOL Turn “ON” Time t(ON) Turn “OFF” Time t(OFF) CONDITIONS GROUP A SUBGROUPS TEMPERATURE (°C) MIN MAX UNITS CL = 35pF, RL = 1kΩ VAH = 3.0V, VAL - 0.8V 9 +25 - 50 ns 10, 11 -55, +125 - 100 ns CL = 35pF, RL = 1kΩ VAH = 3.0V, VAL - 0.8V 9 +25 - 50 ns 10, 11 -55, +125 - 100 ns TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1) Device Characterized at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V PARAMETERS SYMBOL Address Capacitance CA NOTE TEMPERATURE (°C) MIN MAX UNITS f = 1MHz, VAL = 0V 1 +25 - 35 pF CONDITIONS Switch Input Capacitance CS (OFF) f = 1MHz, VAH = 5V, Measure Input to GND 1 +25 - 20 pF Switch Output Capacitance CD (OFF) f = 1MHz, VAH = 5V, Measure Output to Ground 1 +25 - 20 pF CD (ON) f = 1MHz, VAL = 0V, Measure Output to Ground 1 +25 - 50 pF Drain to Source Capacitance CDS f = 1MHz, VAH = 5V 1 +25 - 2.0 pF Off Isolation VISO f = 100kHz, VA = 3.0, RL = 1k, VGEN = 1VP-P, CL = 10pF 1 +25 50 - dB Cross Talk VCT f = 100kHz, VA = 3.0, RL = 1k, VGEN = 1VP-P, CL = 10pF 1 +25 50 - dB Charge Transfer Error VCTE RL = 1k, CL = 0.01µF 1 +25 - 10 mV NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters SUBGROUPS (Tables 1 and 2) 1 1 (Note 2), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C & D Endpoints 1 NOTE: 2. PDA applies to Subgroup 1 only. 3 FN8265.0 April 9, 2012 HI-201HS/883 Test Circuits +VCC +VCC S D VS D S VD ID VIN IIN VIN -VCC GND -VCC GND FIGURE 1. INPUT LEAKAGE CURRENT FIGURE 2. ID(OFF) +VCC +VCC D VS IS S VD D ID(ON) VIN VIN V -VCC GND -VCC GND FIGURE 4. ID(ON) FIGURE 3. IS(OFF) +VCC I1 D S STEP GENERATOR (See Note) TEST POINT 0.01µF VIN 15V IN1 V+ IN3 S1 S3 D1 D3 IN2 IN4 S2 GND I2 TEST POINT 0.01µF D2 V- STEP GENERATOR (See Note) TEST POINT 0.01µF S4 D4 GND TEST POINT 0.01µF -15V GND -VCC NOTE: The pulse generator has the following characteristics: VGEN = 0V to 3V, rise time ≤ 20ns, fall time ≤ 20ns, PRR = 100kHz. FIGURE 5. SUPPLY CURRENTS 4 FIGURE 6. CHARGE TRANSFER ERROR FN8265.0 April 9, 2012 HI-201HS/883 Test Circuits (Continued) 15V SINE WAVE GENERATOR (See Note) +VCC S 2.4V TEST POINT D VIN TEST POINT VD 1kΩ 3.0V 1kΩ A1 V+ S1 S3 D1 D3 A2 A4 S2 D2 V- SINE WAVE GENERATOR (See Note) A3 S4 D4 GND 1kΩ 3.0V 1kΩ TEST POINT TEST POINT -15V GND GND -VCC NOTE: The pulse generator has the following characteristics: VGEN = 1VP-P, Frequency = 100kHz. FIGURE 8. OFF CHANNEL ISOLATION FIGURE 7. RDS 15V 3.0V 0.8V TEST POINT 1kΩ TEST POINT 1kΩ 3.0V 0.8V 1kΩ A1 V+ A3 S1 S3 D1 D3 A2 A4 S2 D2 V- 3.0V 0.8V TEST POINT 3.0V 0.8V 1kΩ TEST POINT S4 D4 GND -15V GND SINE WAVE GENERATOR (See Note) 1kΩ NOTE: The pulse generator has the following characteristics: VGEN = 1VP-P, Frequency = 100kHz. FIGURE 9. CROSSTALK BETWEEN CHANNELS 5 FN8265.0 April 9, 2012 HI-201HS/883 Switching Waveforms (See Note 3) +3V RL = 1kΩ ±5% CL = 35pF ±5% Includes wiring and probe capacitance NOTES: 3. The pulse generator has the following characteristics: VGEN = 3.0V, tTHL ≤ 20ns 4. See Table 2 for complete terminal conditions RISE TIME FALL TIME DIGITAL INPUT tON CONDITION A SWITCH OUTPUT 0V VIH = 3.0V 90% 50% 10% 50% VGEN VIL = 0.0V tOFF 90% 90% 90% 90% 0V CONDITION B NOTE: Rise time and fall time ≤20ns. 6 FN8265.0 April 9, 2012 HI-201HS/883 Burn-In Circuit HI-201HS/883 CERDIP NOTE: R = 10kΩ, 5%, 1/4W or 1/2W. C1 = C2 = 0.01µF (per socket) or 0.1µF (per row). D1 = D2 = IN4002 or equivalent (one per board). |(V+) - (V-)| = 30V. Schematic Diagrams SWITCH CELL A Q MN31 ANALOG IN ANALOG OUT MP33 MP32 MN32 MN33 MP31 Q B 7 FN8265.0 April 9, 2012 HI-201HS/883 Schematic Diagrams (Continued) REFERENCE/LEVEL SHIFTER V+ MP42 MP43 P41 MP44 MP45 QN41 QN43 QN42 R42 D41 5V R41 C48 QN45 QP44 QN44 VR1 C49 DZ42 5.6V QP41 QP42 MN42 MN44 MN45 VEE MN46 A MP51 MP52 QN6 IX4 IX3 IQ MP4 QN8 QN9 QN7 MP3 MP7 VR1 IX2 IX1 MP8 MP5 MP6 MP9 MP10 MP11 MP12 QN1 IQ C1 VA MN11 R1 QN4 QP1 QP4 QP5 QN5 QN2 R3 R2 VCC C2 Q MP13 MP14 QP2 IX3 CFF QP7 IX2 Q VEE R POLY VR1 IX1 MN12 MN5 IX4 QP9 QP6 MN3 MN4 MN9 MN6 MN10 MN13 MN7 MN14 MN8 QP8 MN51 MN52 B REPEAT FOR EACH LEVEL SHIFTER 8 FN8265.0 April 9, 2012 HI-201HS/883 Die Characteristics GLASSIVATION: Type: Nitride Nitride Thickness: 7kÅ ±0.7kÅ DIE DIMENSIONS: 92mils x 111mils x 19mils WORST CASE CURRENT DENSITY: METALLIZATION: 4.5 x 105A/cm2 at 25mA Type: Aluminum Thickness: 16kÅ ±2kÅ This device meets Glassivation Integrity Test requirement per Mil-Std-883 Method 2021 and Mil-M-38510 paragraph 3.5.5.4. Metallization Mask Layout HI-201HS/883 A1 A2 OUT2 OUT1 IN1 IN2 V- V+ GND IN4 IN3 OUT4 OUT3 A4 9 A3 FN8265.0 April 9, 2012 HI-201HS/883 The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves TA = +25°C, VSUPPLY = ±15V, VAH = 3.0V, VAL = 0.8V 80 80 TA = +25°C 70 70 60 60 ON RESISTANCE (Ω) ON RESISTANCE (Ω) V+ = +15V, V- = -15V 50 +125°C 40 +25°C 30 -55°C 20 10 50 40 30 20 -10 -5 0 5 10 0 -15 15 FIGURE 10. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND TEMPERATURE -10 -5 0 5 10 15 FIGURE 11. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER SUPPLY VOLTAGE 100.0 100.0 LEAKAGE CURRENT (nA) LEAKAGE CURRENT (nA) V+ = +15V, V- = -15V ANALOG INPUT (V) ANALOG INPUT (V) 10.0 1.0 0.10 25 75 V+ = +15V, V- = -15V LEAKAGE CURRENT (pA) 6 5 I+ 4 I3 2 1 -15 5 25 45 65 85 105 TEMPERATURE (°C) FIGURE 14. SUPPLY CURRENT vs TEMPERATURE 10 0.10 75 125 FIGURE 13. ID(ON) vs TEMPERATURE 7 -35 1.0 TEMPERATURE (°C) FIGURE 12. IS(OFF) OR ID(OFF) vs TEMPERATURE 0 -55 10.0 0.01 25 125 TEMPERATURE (°C) SUPPLY CURRENT (mA) V+ = +12V, V- = -12V 10 0 -15 0.01 V+ = +8V, V- = -8V V+ = +10V, V- = -10V 125 100 80 V+ = +15V, V- = -15V 60 IS(OFF) → VD = 0V 40 ID(OFF) → VS = 0V 20 ID(ON) 0 -20 -40 -60 IS(OFF) /ID(OFF) -80 -100 -120 -140 -160 -180 -200 -14 -12 -10 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 12 14 FIGURE 15. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE FN8265.0 April 9, 2012 HI-201HS/883 The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. 60 40 VAL = 0V, VAH2 = 3V, VAH1 = 5V 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 -240 -260 -280 35 25 45 55 65 75 85 TA = +25°C, VSUPPLY = ±15V, VAH = 3.0V, VAL = 0.8V (Continued) IAH1 LEAKAGE CURRENT (nA) LEAKAGE CURRENT (µA) Typical Performance Curves IAH2 IAL 95 105 115 125 10 9 V+ = +15V, V- = -15V, TA = +25°C 8 I S(OFF) → VD = 0V 7 6 ID(OFF) → VS = 0V 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -16.0 -15.5 -15.0 -14.5 -14.0 14.0 TEMPERATURE (°C) 14.5 15.0 15.5 16.0 ANALOG INPUT (V) FIGURE 16. DIGITAL INPUT LEAKAGE CURRENT vs TEMPERATURE FIGURE 17. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE 180 350 RL = 1kΩ, CL = 35pF, TA = +25°C tOFF2 160 300 120 SWITCHING TIME (ns) SWITCHING TIME (ns) 140 V+ = +15V V- = -15V RL = 1kΩ CL = 35pF 100 80 60 tOFF1 40 0 -55 -35 tOFF2 200 150 100 -15 5 25 45 65 85 105 0 125 5 TEMPERATURE (°C) tOFF2 150 100 tOFF1 50 0 6 7 8 9 10 11 12 13 14 POSITIVE SUPPLY (V) FIGURE 20. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE 11 9 10 11 12 13 14 15 250 200 tOFF2 150 100 tOFF1 tON 50 tON 5 8 V+ = +15V, RL = 1kΩ CL = 35pF, TA = +25°C 300 SWITCHING TIME (ns) SWITCHING TIME (ns) 350 250 200 7 FIGURE 19. SWITCHING TIME vs POSITIVE AND NEGATIVE SUPPLY VOLTAGE V- = -15V, RL = 1kΩ CL = 35pF, TA = +25°C 300 6 POSITIVE AND NEGATIVE SUPPLY VOLTAGE (±V) FIGURE 18. SWITCHING TIME vs TEMPERATURE 350 tOFF1 tON 50 tON 20 250 15 0 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 NEGATIVE SUPPLY (V) FIGURE 21. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE FN8265.0 April 9, 2012 HI-201HS/883 The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves TA = +25°C, VSUPPLY = ±15V, VAH = 3.0V, VAL = 0.8V (Continued) 3.0 350 V + = +15V, V- = -15V, RL = 1kΩ SWITCHING TIME (ns) INPUT LOGIC THRESHOLD (V) CL = 35pF, VAL = 0V, TA = +25°C 300 250 200 tOFF2 150 100 tOFF1 50 0 2.5 2.0 1.8 1.5 1.0 0.5 tON 0 0 1 2 3 4 DIGITAL INPUT AMPLITUDE (V) 5 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (±V) FIGURE 22. SWITCHING TIME vs INPUT LOGIC AMPLITUDE FIGURE 23. INPUT SWITCHING THRESHOLD vs POSITIVE AND NEGATIVE SUPPLY VOLTAGE 40 ΔVO OUT IN CHARGE INJECTION (pC) 40 30 20 30 CL VA 10 0 CD(ON) 35 CAPACITANCE (pF) 50 QOUT ΔQO = CL x ΔVO -10 -20 25 20 15 CD(OFF) OR CS(OFF) 10 -30 V+ = +15V, V- = -15V CL = 1nF, RIN = 0Ω -40 -50 -10 -5 0 ANALOG INPUT (V) 5 5 CDS(OFF) 0 -15 10 -10 FIGURE 24. CHARGE INJECTION vs ANALOG INPUT 140 140 V+ = +15V, V- = -15V VIN = 3VRMS , VA = 3V 80 RL = 100Ω IN VIN 40 20 OUT VO RL = 1kΩ OFF ISOLATION = 20 Log 0 10k 100k RL = 1kΩ VIN FIGURE 26. OFF ISOLATION vs FREQUENCY 12 100 IN 80 60 VIN 40 OUT VO1 RL = 1kΩ VO2 RL = 1kΩ CROSSTALK = 20 Log FREQUENCY (Hz) 15 VIN = 3VRMS , VA = 3V 20 VO 1M 10 V+ = +15V, V- = -15V 120 100 60 0 5 ANALOG INPUT (V) FIGURE 25. CAPACITANCE vs ANALOG INPUT CROSSTALK (dB) OFF ISOLATION (dB) 120 -5 10M 0 10k VO2 VO1 100k 1M FREQUENCY (Hz) 10M FIGURE 27. CROSSTALK vs FREQUENCY FN8265.0 April 9, 2012 HI-201HS/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE METAL E M -Bbbb S C A-B S (c) Q -C- SEATING PLANE S1 b2 b C A-B S eA/2 NOTES - 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 c aaa M C A - B S D S D S MAX 0.014 eA e MIN b α A A MILLIMETERS MAX A A L MIN M (b) SECTION A-A D S INCHES SYMBOL b1 D BASE PLANE ccc M F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 16 5. This dimension allows for off-center lid, meniscus, and glass overrun. 16 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN8265.0 April 9, 2012