IRFP048R, SiHFP048R Datasheet

IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Dynamic dV/dt rating
60
RDS(on) ()
VGS = 10 V
• Isolated central mounting hole
0.018
Qg max. (nC)
110
• 175 °C operating temperature
Qgs (nC)
29
• Ease of paralleling
Qgd (nC)
38
• Simple drive requirements
Configuration
Single
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D
DESCRIPTION
TO-247AC
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness. 
The
TO-247AC
package
is
preferred
for
commercial-industrial applications where higher power
levels preclude the use of TO-220AB devices. The
TO-247AC is similar but superior to the earlier TO-218
package because its isolated mounting hole. It also provides
greater creepage distances between pins to meet the
requirements of most safety specifications.
G
S
D
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247AC
Lead (Pb)-free
IRFP048RPbF
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
± 20
Continuous Drain Current e
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dt c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature) d
Mounting Torque
for 10 s
6-32 or M3 screw
V
70
52
A
IDM
290
1.3
W/°C
EAS
200
mJ
PD
190
W
dV/dt
4.5
V/ns
TJ, Tstg
-55 to +175
Linear Derating Factor
Single Pulse Avalanche Energy b
UNIT
300
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 43 μH, Rg = 25 , IAS = 73 A (see fig. 12).
c. ISD  72 A, dI/dt  200 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. Current limited by the package (die current = 73 A)
S16-0015-Rev. C, 18-Jan-16
Document Number: 91199
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.80
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 μA
60
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.060
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 150 °C
-
-
250
μA
-
-
0.018

gfs
VDS = 25 V, ID = 44 A b
20
-
-
S
Input Capacitance
Ciss
2400
-
Coss
-
1300
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
Output Capacitance
-
190
-
-
-
110
-
-
29
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
ID = 44 A b
VGS = 10 V
Dynamic
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
38
Turn-On Delay Time
td(on)
-
8.1
-
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VGS = 10 V
ID = 72 A, VDS = 48 V
see fig. 6 and 13 b
VDD = 30 V, ID = 72 A,
Rg = 9.1 , RD = 0.34, see fig. 10 b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
-
250
-
-
210
-
-
250
-
-
5.0
-
-
13
-
-
-
70c
-
-
290
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current a
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the 
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 73 A, VGS = 0 V
S
b
TJ = 25 °C, IF = 72 A, dI/dt = 100 A/μs b
-
-
2.0
V
-
120
180
ns
-
0.50
0.80
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. Current limited by the package (die current = 73 A).
S16-0015-Rev. C, 18-Jan-16
Document Number: 91199
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 175 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
S16-0015-Rev. C, 18-Jan-16
Document Number: 91199
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
S16-0015-Rev. C, 18-Jan-16
Document Number: 91199
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
IAS
V DD
A
VDS
10 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
S16-0015-Rev. C, 18-Jan-16
IAS
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91199
5
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S16-0015-Rev. C, 18-Jan-16
Fig. 13b - Gate Charge Test Circuit
Document Number: 91199
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFP048R, SiHFP048R
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel










Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91199.
S16-0015-Rev. C, 18-Jan-16
Document Number: 91199
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-247AC (High Voltage)
A
A
4
E
B
3 R/2
E/2
7 ØP
Ø k M DBM
A2
S
(Datum B)
ØP1
A
D2
Q
4
4
2xR
(2)
D1
D
1
2
4
D
3
Thermal pad
5 L1
C
L
A
See view B
2 x b2
3xb
0.10 M C A M
4
E1
0.01 M D B M
View A - A
C
2x e
A1
b4
Planting
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D DE
(b1, b3, b5)
Base metal
E
C
(c)
C
c1
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS
DIM.
MIN.
MAX.
A
4.58
5.31
A1
2.21
2.59
A2
1.17
2.49
b
0.99
1.40
b1
0.99
1.35
b2
1.53
2.39
b3
1.65
2.37
b4
2.42
3.43
b5
2.59
3.38
c
0.38
0.86
c1
0.38
0.76
D
19.71
20.82
D1
13.08
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
INCHES
MIN.
MAX.
0.180
0.209
0.087
0.102
0.046
0.098
0.039
0.055
0.039
0.053
0.060
0.094
0.065
0.093
0.095
0.135
0.102
0.133
0.015
0.034
0.015
0.030
0.776
0.820
0.515
-
DIM.
D2
E
E1
e
Øk
L
L1
N
ØP
Ø P1
Q
R
S
MILLIMETERS
MIN.
MAX.
0.51
1.30
15.29
15.87
13.72
5.46 BSC
0.254
14.20
16.25
3.71
4.29
7.62 BSC
3.51
3.66
7.39
5.31
5.69
4.52
5.49
5.51 BSC
INCHES
MIN.
MAX.
0.020
0.051
0.602
0.625
0.540
0.215 BSC
0.010
0.559
0.640
0.146
0.169
0.300 BSC
0.138
0.144
0.291
0.209
0.224
0.178
0.216
0.217 BSC
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
1
Document Number: 91000