Si1480DH Datasheet

Si1480DH
Vishay Siliconix
N-Channel 100 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
100
RDS(on) () Max.
ID (A)
0.200 at VGS = 10 V
2.6a
0.320 at VGS = 4.5 V
2.2
• TrenchFET® Power MOSFET
• 100 % Rg and UIS Tested
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
Qg (Typ.)
1.8
APPLICATIONS
•
•
•
•
Load Switches
DC/DC Converters
Power Management
LED Backlighting
SOT-363
SC-70 (6-LEADS)
D
1
D
6
D
D
5
2
AU
D
XX
YY
Marking Code
G
Lot Traceability
and Date Code
G
3
4
S
Part # Code
S
Top View
N-Channel MOSFET
Ordering Information: Si1480DH-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
± 20
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)a
TC = 70 °C
TA = 25 °C
2.6
2.1b,c
IDM
7
Avalanche Current
IAS
2.4
EAS
0.29
Continuous Source-Drain Diode Current
Maximum Power Dissipationa
TC = 25 °C
TA = 25 °C
IS
A
1.3b,c
2.8
TC = 70 °C
1.8
PD
W
1.5b,c
TA = 70 °C
Operating Junction and Storage Temperature Range
mJ
2.3
TC = 25 °C
TA = 25 °C
A
1.7b,c
Pulsed Drain Current (t = 300 µs)
L = 0.1 mH
V
a
2.2
ID
TA = 70 °C
Repetitive Avalanche Energy
Unit
1
TJ, Tstg
b,c
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
t 5 s
Steady State
Maximum Junction-to-Ambientb,d
Maximum Junction-to-Foot (Drain)
Symbol
Typical
Maximum
Unit
RthJA
RthJF
60
34
80
45
°C/W
Notes:
a. Package Limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 125 °C/W.
Document Number: 67327
S12-2727-Rev. A, 12-Nov-12
For technical questions, contact: [email protected]
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1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1480DH
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
100
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS/TJ
VDS Temperature Coefficient
ID = 250 µA
VGS(th) Temperature Coefficient
VGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 µA
IGSS
Gate-Source Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
RDS(on)
Forward Transconductance
gfs
V
54
mV/°C
- 4.1
3
V
VDS = 0 V, VGS = ± 20 V
± 100
nA
VDS = 100 V, VGS = 0 V
1
VDS = 100 V, VGS = 0 V, TJ = 55 °C
10
VDS =  5 V, VGS = 10 V
1.6
6
µA
A
VGS = 10 V, ID = 1.9 A
0.161
0.200
VGS = 4.5 V, ID = 1.5 A
0.230
0.320
VDS = 10 V, ID = 1.9 A
3.7

S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
130
VDS = 50 V, VGS = 0 V, f = 1 MHz
tr
Turn-Off DelayTime
td(off)
Fall Time
3.3
5
1.8
2.7
VDS = 50 V, VGS = 4.5 V, ID = 2.7 A
0.7
Turn-On Delay Time
VDD = 50 V, RL = 23 
ID  2.2 A, VGEN = 4.5 V, Rg = 1 
td(on)
tr
Turn-Off DelayTime
td(off)
Fall Time
nC
1
f = 1 MHz
tf
Rise Time
pF
VDS = 50 V, VGS = 10 V, ID = 2.7 A
td(on)
Rise Time
54
10
VDD = 50 V, RL = 23 
ID  2.2 A, VGEN = 10 V, Rg = 1 
tf
1.3
6.5
13
15
30
45
90
11
20
13
25
5
10
11
20
10
20
10
20

ns
ns
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current
IS
Pulse Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Charge
Qrr
Body Diode Reverse Recovery Time
trr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
TC = 25 °C
2.3
7
IS = 2.2 A, VGS = 0 V
IF = 2.2 A, dI/dt = 100 A/µs,
TJ = 25 °C
A
0.9
1.2
V
20
40
nC
25
50
18
ns
7
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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For technical questions, contact: [email protected]
Document Number: 67327
S12-2727-Rev. A, 12-Nov-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1480DH
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
7
2.0
VGS = 10 V thru 6 V
VGS = 5 V
6
ID - Drain Current (A)
ID - Drain Current (A)
1.6
5
4
3
VGS = 4 V
2
1.2
TC = 25 °C
0.8
TC = 125 °C
0.4
1
TC = - 55 °C
VGS = 3 V
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
3.0
1.0
VDS - Drain-to-Source Voltage (V)
3.0
4.0
5.0
Transfer Characteristics Curves vs. Temperature
0.500
200
0.400
160
Ciss
0.300
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
Output Characteristics
VGS = 4.5 V
0.200
VGS = 10 V
120
Coss
80
0.100
40
0.000
Crss
0
0
1
2
3
4
5
6
0
4
8
12
16
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
20
1.8
10
RDS(on) - On-Resistance (Normalized)
VDS = 50 V
VGS - Gate-to-Source Voltage (V)
2.0
VGS - Gate-to-Source Voltage (V)
ID = 2.7 A
8
VDS = 25 V
6
VDS = 80 V
4
2
VGS = 10 V
1.6
ID = 1.9 A
1.4
VGS = 4.5 V
1.2
1.0
0.8
0.6
0
0
1
2
3
4
- 50
- 25
0
25
50
75
100
125
150
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 67327
S12-2727-Rev. A, 12-Nov-12
For technical questions, contact: [email protected]
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1480DH
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
100
0.60
10
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
0.50
TJ = 150 °C
TJ = 25 °C
1
ID = 1.9 A
0.40
0.30
TJ = 125 °C
0.20
TJ = 25 °C
0.10
0.1
0.00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
2
VSD - Source-to-Drain Voltage (V)
4
6
8
10
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
RDS(on) vs. VGS vs. Temperature
30
2.8
25
2.6
Power (W)
VGS(th) (V)
20
2.4
ID = 250 μA
2.2
15
10
2.0
5
1.8
- 50
- 25
0
25
50
75
100
125
0
0.001
150
1
Time (s)
Threshold Voltage
Single Pulse Power
10
100
600
Limited by RDS(on)*
10
100 us
1
ID - Drain Current (A)
0.01
0.1
TJ - Temperature (°C)
1 ms
0.1
10 ms
100 ms
1s
10 s
DC
TA = 25 °C
0.01
BVDSS Limited
0.001
0.1
1
10
100
1000
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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For technical questions, contact: [email protected]
Document Number: 67327
S12-2727-Rev. A, 12-Nov-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1480DH
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
3.0
3.0
2.5
2.5
2.0
2.0
Power (W)
ID - Drain Current (A)
Package Limited
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
0
25
50
75
100
TF - Foot Temperature (°C)
Current Derating*
125
150
25
50
75
100
125
150
TC - Foot Temperature (°C)
Power Derating
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 67327
S12-2727-Rev. A, 12-Nov-12
For technical questions, contact: [email protected]
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1480DH
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
t1
0.05
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = R thJA = 125 °C/W
3. T JM - TA = PDMZthJA(t)
4. Surface Mounted
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67327.
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For technical questions, contact: [email protected]
Document Number: 67327
S12-2727-Rev. A, 12-Nov-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SCĆ70:
6ĆLEADS
MILLIMETERS
6
5
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
4
E1 E
1
2
3
-B-
e
b
e1
D
-Ac
A2 A
L
A1
Document Number: 71154
06-Jul-01
INCHES
Min
Nom
Max
Min
Nom
Max
0.90
–
1.10
0.035
–
0.043
–
–
0.10
–
–
0.004
0.80
–
1.00
0.031
–
0.039
0.15
–
0.30
0.006
–
0.012
0.10
–
0.25
0.004
–
0.010
1.80
2.00
2.20
0.071
0.079
0.087
1.80
2.10
2.40
0.071
0.083
0.094
1.15
1.25
1.35
0.045
0.049
0.053
0.65BSC
0.026BSC
1.20
1.30
1.40
0.047
0.051
0.055
0.10
0.20
0.30
0.004
0.008
0.012
7_Nom
7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
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1
AN815
Vishay Siliconix
Single-Channel LITTLE FOOTR SC-70 6-Pin MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
EVALUATION BOARDS SINGLE SC70-6
The new single 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the single-channel version.
The evaluation board (EVB) measures 0.6 inches by
0.5 inches. The copper pad traces are the same as in Figure 2.
The board allows examination from the outer pins to 6-pin DIP
connections, permitting test sockets to be used in evaluation
testing. See Figure 3.
52 (mil)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the basic
pad layout and dimensions. These pad patterns are sufficient
for the low to medium power applications for which this
package is intended. Increasing the drain pad pattern yields a
reduction in thermal resistance and is a preferred footprint.
The availability of four drain leads rather than the traditional
single drain lead allows a better thermal path from the package
to the PCB and external environment.
96 (mil)
6
5
4
1
2
3
71 (mil)
26 (mil)
13 (mil)
0, 0 (mil)
18 (mil)
26 (mil)
PIN-OUT
16 (mil)
Figure 1 shows the pin-out description and Pin 1
identification.The pin-out of this device allows the use of four
pins as drain leads, which helps to reduce on-resistance and
junction-to-ambient thermal resistance.
SOT-363
SC-70 (6-LEADS)
D
1
6
D
D
2
5
D
G
3
4
S
FIGURE 2.
SC-70 (6 leads) Single
The thermal performance of the single 6-pin SC-70 has been
measured on the EVB, comparing both the copper and
Alloy 42 leadframes. This test was first conducted on the
traditional Alloy 42 leadframe and was then repeated using the
1-inch2 PCB with dual-side copper coating.
Top View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
Document Number: 71334
12-Dec-03
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1
AN815
Vishay Siliconix
Front of Board SC70-6
Back of Board SC70-6
vishay.com
FIGURE 3.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(Package Performance)
COOPER LEADFRAME
Room Ambient 25 _C
The junction to foot thermal resistance is a useful method of
comparing different packages thermal performance.
A helpful way of presenting the thermal performance of the
6-Pin SC-70 copper leadframe device is to compare it to the
traditional Alloy 42 version.
Thermal performance for the 6-pin SC-70 measured as
junction-to-foot thermal resistance, where the “foot” is the
drain lead of the device at the bottom where it meets the PCB.
The junction-to-foot thermal resistance is typically 40_C/W in
the copper leadframe and 163_C/W in the Alloy 42 leadframe
— a four-fold improvement. This improved performance is
obtained by the enhanced thermal conductivity of copper over
Alloy 42.
The typical RqJA for the single 6-pin SC-70 with copper
leadframe is 103_C/W steady-state, compared with 212_C/W
for the Alloy 42 version. The figures are based on the 1-inch2
FR4 test board. The following example shows how the thermal
resistance impacts power dissipation for the two different
leadframes at varying ambient temperatures.
ALLOY 42 LEADFRAME
PD +
Rq JA
Elevated Ambient 60 _C
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
212 CńW
o
o
P D + 150 Co* 25 C
212 CńW
P D + 590 mW
P D + 425 mW
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2
T J(max) * T A
T J(max) * T A
Rq JA
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
124 CńW
o
o
P D + 150 Co* 60 C
124 CńW
P D + 1.01 W
P D + 726 mW
As can be seen from the calculations above, the compact 6-pin
SC-70 copper leadframe LITTLE FOOT power MOSFET can
handle up to 1 W under the stated conditions.
Testing
To further aid comparison of copper and Alloy 42 leadframes,
Figure 5 illustrates single-channel 6-pin SC-70 thermal
performance on two different board sizes and two different pad
patterns. The measured steady-state values of RqJA for the
two leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Power Dissipation
Room Ambient 25 _C
PD +
Elevated Ambient 60 _C
1) Minimum recommended pad pattern on
the EVB board V (see Figure 3.
1-inch2
2) Industry standard
PCB with
maximum copper both sides.
Alloy 42
Copper
329.7_C/W
208.5_C/W
211.8_C/W
103.5_C/W
The results indicate that designers can reduce thermal
resistance (RqJA) by 36% simply by using the copper
leadframe device rather than the Alloy 42 version. In this
example, a 121_C/W reduction was achieved without an
increase in board area. If increasing in board size is feasible,
a further 105_C/W reduction could be obtained by utilizing a
1-inch2 square PCB area.
The copper leadframe versions have the following suffix:
Single:
Si14xxEDH
Dual:
Si19xxEDH
Complementary: Si15xxEDH
Document Number: 71334
12-Dec-03
AN815
400
250
320
200
240
Thermal Resistance (C/W)
Thermal Resistance (C/W)
Vishay Siliconix
Alloy
42
160
Copper
80
150
Alloy
42
100
50
Copper
0
0
10-5
10-4
10-3
10-2
10-1
1
10
100
1000
10-5
Leadframe Comparison on EVB
Document Number: 71334
12-Dec-03
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
Time (Secs)
FIGURE 4.
10-4
FIGURE 5.
Leadframe Comparison on Alloy 42 1-inch2 PCB
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3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.067
0.026
(0.648)
0.045
(1.143)
0.096
(2.438)
(1.702)
0.016
0.026
0.010
(0.406)
(0.648)
(0.241)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72602
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000