Si1302DL Datasheet

Si1302DL
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
PRODUCT SUMMARY
VDS (V)
30
FEATURES
RDS(on) ()
ID (A)
0.480 at VGS = 10 V
0.64
0.700 at VGS = 4.5 V
0.53
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Compliant to RoHS Directive 2002/95/EC
SC-70 (3-LEADS)
1
Marking Code
3
S
D
2
KA
XX
YY
G
Lot Traceability
and Date Code
Part # Code
Top View
Ordering Information: Si1302DL-T1-E3 (Lead (Pb)-free)
Si1302DL-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)a
Symbol
VDS
VGS
TA = 25 °C
TA = 70 °C
ID
IDM
IS
Pulsed Drain Current
Continuous Diode Current (Diode Conduction)a
Maximum Power Dissipationa
TA = 25 °C
TA = 70 °C
PD
5s
0.64
0.51
0.26
0.31
0.20
TJ, Tstg
Operating Junction and Storage Temperature Range
Steady State
30
± 20
0.60
0.48
1.5
0.23
0.28
0.18
- 55 to 150
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
Symbol
t 5 s
Steady State
Steady State
RthJA
RthJF
Typical
355
380
285
Maximum
400
450
340
Unit
°C/W
Notes:
a. Surface mounted on 1" x 1" FR4 board.
Document Number: 71249
S10-2140-Rev. F, 20-Sep-10
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Si1302DL
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
1
Typ
Max.
Unit
Static
VGS(th)
VDS = VGS, ID = 250 µA
3
V
Gate-Body Leakage
IGSS
VDS = 0 V, VGS = ± 20 V
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V
1
5
On-State Drain Currenta
ID(on)
VDS = 30 V, VGS = 0 V, TJ = 70 °C
VDS = 5 V, VGS = 10 V
Gate Threshold Voltage
Drain-Source On-State Resistancea
Forward Transconductancea
Diode Forward
Voltagea
1.5
A
VGS = 10 V, ID = 0.6 A
0.410
0.480
VGS = 4.5 V, ID = 0.2 A
0.600
0.700
gfs
VGS = 15 V, ID = 0.6 A
0.75
VSD
IS = 0.23 A, VGS = 0 V
0.8
1.2
0.86
1.4
RDS(on)
µA

S
V
Dynamicb
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
0.08
Turn-On Delay Time
td(on)
5
10
8
15
Rise Time
VDS = 15 V, VGS = 10 V, ID = 0.6 A
VDD = 15 V, RL = 30 
ID  0.5 A, VGEN = 10 V, Rg = 6 
tr
Turn-Off DelayTime
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
0.24
IF = 0.23 A, dI/dt = 100 A/µs
nC
8
15
7
15
15
30
ns
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1.0
1.0
VGS = 10 V thru 4 V
0.8
I D - Drain Current (A)
I D - Drain Current (A)
0.8
0.6
0.4
3V
0.2
0.6
0.4
TC = 125 °C
0.2
25 °C
0.0
0.0
0.5
1.0
1.5
2.0
2.5
VDS - Drain-to-Source Voltage (V)
Output Characteristics
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2
3.0
0.0
0.0
0.5
1.0
1.5
2.0
- 55 °C
2.5
3.0
3.5
4.0
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
Document Number: 71249
S10-2140-Rev. F, 20-Sep-10
Si1302DL
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1.6
60
1.4
Ciss
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
50
1.2
1.0
0.8
VGS = 4.5 V
0.6
VGS = 10 V
40
30
Coss
20
0.4
0.0
0.0
Crss
10
0.2
0
0.2
0.4
0.6
0.8
1.0
0
4
8
1.8
VDS = 15 V
ID = 0.6 A
VGS = 10 V
ID = 0.6 A
1.6
8
6
4
1.4
(Normalized)
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
20
Capacitance
10
2
1.2
1.0
0.8
0.2
0.4
0.6
0.8
0.6
- 50
1.0
- 25
0
Qg - Total Gate Charge (nC)
25
50
75
100
125
150
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
1.8
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
1
TJ = 150 °C
1.5
1.2
ID = 0.6 A
0.9
0.6
0.3
TJ = 25 °C
0.1
0.0
16
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
On-Resistance vs. Drain Current
0
0.0
12
0.0
0.2
0.4
0.6
0.8
1.0
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
Document Number: 71249
S10-2140-Rev. F, 20-Sep-10
1.2
0
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
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Si1302DL
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.4
5
4
0.2
0.0
Power (W)
VGS(th) Variance (V)
ID = 250 µA
- 0.2
- 0.4
3
TA = 25 °C
2
1
- 0.6
- 50
0
- 25
0
25
50
75
100
125
150
10-2
10-1
1
10
100
600
Time (s)
TJ - Temperature (°C)
Threshold Voltage
Single Pulse Power
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 360 °C/W
3. TJM – TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
100
10
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71249.
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Document Number: 71249
S10-2140-Rev. F, 20-Sep-10
Package Information
Vishay Siliconix
SCĆ70:
3ĆLEADS
MILLIMETERS
3
E1 E
1
2
e
b
e1
D
c
A2
A
L
0.08
c
A1
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
INCHES
Min
Nom
Max
Min
Nom
Max
0.90
–
1.10
0.035
–
0.043
–
–
0.10
–
–
0.004
0.80
–
1.00
0.031
–
0.039
0.25
–
0.40
0.010
–
0.016
0.10
–
0.25
0.004
–
0.010
1.80
2.00
2.20
0.071
0.079
0.087
1.80
2.10
2.40
0.071
0.083
0.094
1.15
1.25
1.35
0.045
0.049
0.053
0.65BSC
0.026BSC
1.20
1.30
1.40
0.047
0.051
0.055
0.10
0.20
0.30
0.004
0.008
0.012
7_Nom
7_Nom
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5549
Document Number: 71153
06-Jul-01
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AN813
Vishay Siliconix
Single-Channel LITTLE FOOTR SC-70 3-Pin and 6-Pin MOSFET
Recommended Pad Pattern and Thermal Peformance
INTRODUCTION
BASIC PAD PATTERNS
This technical note discusses pin-outs, package outlines, pad
patterns, evaluation board layout, and thermal performance
for single-channel LITTLE FOOT power MOSFETs in the
SC-70 package. These new Vishay Siliconix devices are
intended for small-signal applications where a miniaturized
package is needed and low levels of current (around 350 mA)
need to be switched, either directly or by using a level shift
configuration. Vishay provides these single devices with a
range of on-resistance specifications and in both traditional
3-pin and new 6-pin versions. The new 6-pin SC-70 package
enables improved on-resistance values and enhanced
thermal performance compared to the 3-pin package.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the basic
pad layout and dimensions for the 3-pin SC-70 and the 6-pin
SC-70. These pad patterns are sufficient for the low-power
applications for which this package is intended. Increasing the
pad pattern has little effect on thermal resistance for the 3-pin
device, reducing it by only 10% to 15%. But for the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 35% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB). The availability of four drain leads rather than the
traditional single drain lead allows a better thermal path from
the package to the PCB and external environment.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the single-channel SC-70 device in both 3-pin and 6-pin
configurations. The pin-out of the 6-pin device allows the use
of four pins as drain leads, which helps to reduce on-resistance
and junction-to-ambient thermal resistance.
SOT-323
SC-70 (3-LEADS)
SOT-363
SC-70 (6-LEADS)
Top View
G
Top View
1
3
S
D
2
D
1
6
D
2
5
G
3
4
EVALUATION BOARDS FOR THE SINGLE
SC70-3 AND SC70-6
Figure 2 shows the 3-pin and 6-pin SC-70 evaluation boards
(EVB). Both measure 0.6 inches by 0.5 inches. Their copper
pad traces are the same as described in the previous section,
Basic Pad Patterns. Both boards allow interrogation from the
outer pins to 6-pin DIP connections, permitting test sockets to
be used in evaluation testing.
The thermal performance of the single SC-70 has been
measured on the EVB for both the 3-pin and 6-pin devices, the
results shown in Figures 3 and 4. The minimum recommended
footprint on the evaluation board was compared with the
industry standard of 1-inch square FR4 PCB with copper on
both sides of the board.
FIGURE 1.
For package dimensions see outline drawings:
SC-70 (3-Leads) (http://www.vishay.com/doc?71153)
SC-70 (6-Leads) (http://www.vishay.com/doc?71154)
Front of Board SC70-3
Back of Board, SC70-3 and SC70-6
Front of Board SC70-6
ChipFETr
ChipFETr
vishay.com
FIGURE 2.
Document Number: 71236
12-Dec-03
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AN813
Vishay Siliconix
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
SC-70 (6-PIN)
Thermal performance for the 3-pin SC-70 measured as
junction-to-foot thermal resistance is 285_C/W typical,
340_C/W maximum. Junction-to-foot thermal resistance for
the 6-pin SC70-6 is 105_C/W typical, 130_C/W maximum —
a nearly two-thirds reduction compared with the 3-pin device.
The “foot” is the drain lead of the device as it connects with the
body. This improved performance is obtained by the increase
in drain leads from one to four on the 6-pin SC-70. Note that
these numbers are somewhat higher than other LITTLE FOOT
devices due to the limited thermal performance of the Alloy 42
lead-frame compared with a standard copper lead-frame.
The typical RθJAfor the single 3-pin SC-70 is 360_C/W steady
state, compared with 180_C/W for the 6-pin SC-70. Maximum
ratings are 430_C/W for the 3-pin device versus 220_C/W for
the 6-pin device. All figures are based on the 1-inch square
FR4 test board.The following table shows how the thermal
resistance impacts power dissipation for the two different
pin-outs at two different ambient temperatures.
TJ(max) * TA
PD +
Rq JA
o
o
PD + 150 Co* 25 C
180 CńW
Room Ambient 25 _C
Elevated Ambient 60 _C
TJ(max) * TA
PD +
Rq JA
TJ(max) * TA
Rq JA
o
o
PD + 150 Co* 25 C
360 CńW
o
o
PD + 150 Co* 60 C
360 CńW
PD + 347 mW
PD + 250 mW
PD + 694 mW
PD + 500 mW
To aid comparison further, Figures 3 and 4 illustrate
single-channel SC-70 thermal performance on two different
board sizes and two different pad patterns. The results display
the thermal performance out to steady state and produce a
graphic account of the thermal performance variation between
the two packages. The measured steady state values of RθJA
for the single 3-pin and 6-pin SC-70 are as follows:
LITTLE FOOT SC-70
Thermal Resistance (C/W)
320
3-pin
6-pin
160
80
329.7_C/W
360_C/W
211.8_C/W
3-pin
6-pin
160
80
1” Square FR4 PCB
0
10-3
10-2
10-1
1
10
100
1000
10-5 10-4
Comparison of SC70-3 and SC70-6 on EVB
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
Time (Secs)
2
410.31_C/W
240
0.5 in x 0.6 in EVB
0
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6-Pin
The results show that designers can reduce thermal
resistance RθJA on the order of 20% simply by using the 6-pin
device rather than the 3-pin device. In this example, a 80_C/W
reduction was achieved without an increase in board area. If
increasing board size is an option, a further 118_C/W reduction
could be obtained by utilizing a 1-inch square PCB area.
320
240
3-Pin
2) Industry standard 1” square PCB with
maximum copper both sides.
400
FIGURE 3.
Rq JA
NOTE: Although they are intended for low-power applications,
devices in the 6-pin SC-70 will handle power dissipation in
excess of 0.5 W.
400
10-5 10-4
TJ(max) * TA
o
o
PD + 150 Co* 60 C
180 CńW
1) Minimum recommended pad pattern
(see Figure 4) on the EVB.
SC-70 (3-PIN)
Thermal Resistance (C/W)
PD +
Elevated Ambient 60 _C
Testing
Junction-to-Ambient Thermal Resistance
(dependent on PCB size)
PD +
Room Ambient 25 _C
FIGURE 4.
Comparison of SC70-3 and SC70-6 on 1”
Square FR4 PCB
Document Number: 71236
12-Dec-03
Application Note 826
Vishay Siliconix
0.045
(1.143)
(0.648)
0.022
(0.559)
0.026
0.025
(0.622)
(2.438)
0.096
RECOMMENDED MINIMUM PADS FOR SC-70: 3-Lead
0.027
(0.686)
0.071
(1.803)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72601
Revision: 21-Jan-08
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Revision: 02-Oct-12
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Document Number: 91000