CA3420, CA3420A TM Data Sheet April 2000 File Number 1320.6 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifiers Features The CA3420A and CA3420 are integrated circuit operational amplifiers that combine PMOS transistors and bipolar transistors on a single monolithic chip. The CA3420A and CA3420 BiMOS operational amplifiers feature gate protected PMOS transistors in the input circuit to provide very high input impedance, very low input currents (less than 1pA). The internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leakage current for every 10oC increase in temperature. The CA3420 series operates at total supply voltages from 2V to 20V either single or dual supply. These operational amplifiers are internally phase compensated to achieve stable operation in the unity gain follower configuration. Additionally, they have access terminals for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common mode input voltage capability down to 0.45V below the negative supply terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that can swing essentially from rail-to-rail. The output driving current of 1.5mA (Min) is provided by using nonlinear current mirrors. • 1pA Input Current (Typ) (Essentially Constant to 85oC) • 2V Supply at 300µA Supply Current • Rail-to-Rail Output Swing (Drive ±2mA into 1kΩ Load) • Pin Compatible with 741 Operational Amplifiers Applications • pH Probe Amplifiers • Picoammeters • Electrometer (High Z) Instruments • Portable Equipment • Inaccessible Field Equipment • Battery-Dependent Equipment (Medical and Military) Functional Diagram X1 MOS BIPOLAR Ordering Information TEMP. RANGE (oC) PART NUMBER PACKAGE PKG. NO. CA3420AT -55 to 125 8 Pin Metal Can T8.C CA3420E -55 to 125 8 Ld PDIP E8.3 + MOS BIPOLAR HIGH GAIN (50K) OTA BUFFER (X2) X1 BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK Pinouts CA3420 (PDIP) TOP VIEW CA3420 (METAL CAN) TOP VIEW TAB OFFSET NULL 1 INV. INPUT 2 NON-INV. INPUT 3 V- 4 8 STROBE 7 V+ + 6 OUTPUT 5 OFFSET NULL OFFSET NULL STROBE 8 7 V+ 1 INV. 2 INPUT NON-INV. 3 INPUT - 6 OUTPUT + 4 5 OFFSET NULL V- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 CA3420, CA3420A Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 105 N/A Metal Can Package . . . . . . . . . . . . . . . 165 80 Maximum Junction Temperature (Metal Can Package). . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Typical Values Intended Only for Design Guidance, VSUPPLY = ±10V, TA = 25oC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS CA3420A CA3420 UNITS Input Resistance RI 150 150 TΩ Input Capacitance CI 4.9 4.9 pF Output Resistance RO 300 300 Ω Equivalent Input Noise Voltage eN 62 62 nV/√Hz 38 38 nV/√Hz mA f = 1kHz RS = 100Ω f = 10kHz Short-Circuit Current Source IOM+ 2.6 2.6 To Opposite Supply Sink IOM- 2.4 2.4 mA fT 0.5 0.5 MHz Gain Bandwidth Product Slew Rate SR Transient Response Current from Terminal 8 0.5 0.5 V/µs 0.7 0.7 µs OS 15 15 % To V- I8+ 20 20 µA To V+ I8- 2 2 mA Rise Time tR Overshoot RL = 2kΩ, CL = 100pF For Equipment Design, At VSUPPLY = ±1V, TA = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL Input Offset Voltage Input Offset Current (Note 3) Input Current (Note 3) TEST CONDITIONS CA3420A TYP MAX MIN TYP MAX UNITS |VIO| - 5 10 - 2 5 mV |IIO| - 0.01 4 - 0.01 4 pA |II| Large Signal Voltage Gain CA3420 MIN AOL RL = 10kΩ - 1 5 - 0.02 5 pA 10 100 - 20 100 - kV/V 80 100 - 86 100 - dB Common Mode Rejection Ratio CMRR - 560 1800 - 560 1000 µV/V 55 65 - 60 65 - dB Common Mode Input Voltage Range VlCR+ 0.2 0.5 - 0.2 0.5 - V VlCR- - -1.3 - -1 -1.3 - V 100 1000 - 32 320 µV/V Power Supply Rejection Ratio PSRR ∆VIO/∆V 60 80 - 70 90 - dB Max Output Voltage VOM+ RL = ∞ 0.90 0.95 - 0.90 0.95 - V VOM- -0.85 -0.91 - -0.85 -0.91 - V I+ - 350 650 - 350 650 µA PD - 0.7 1.1 - 0.7 1.1 mW ∆VlO/∆T - 4 - - 4 - µV/oC Supply Current Device Dissipation Input Offset Voltage Temperature Drift NOTE: 3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. 2 CA3420, CA3420A For Equipment Design, at VSUPPLY = ±10V, TA = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS CA3420 MIN CA3420A TYP MAX MIN TYP MAX UNITS mV |VIO| - 5 10 - 2 5 Input Offset Current (Note 4) |IIO| - 0.03 4 - 0.03 4 pA Input Current (Note 4) |II| - 0.05 5 - 0.05 5 pA 10 100 - 20 100 - kV/V 80 100 - 86 100 - dB 100 320 - 100 320 µV/V dB Input Offset Voltage Large Signal Voltage Gain AOL RL = 10kΩ Common Mode Rejection Ratio CMRR 70 80 - 70 80 - Common Mode Input Voltage Range VlCR+ 8.5 9.3 - 9.0 9.3 - V VlCR- -10 -10.3 - -10 -10.3 - V - 32 320 - 32 320 µV/V 70 90 - 70 90 - dB V Power Supply Rejection Ratio PSRR VOM+ Max Output Voltage Supply Current Device Dissipation Input Offset Voltage Temperature Drift ∆VIO/∆V RL = ∞ 9.7 9.9 - 9.7 9.9 - VOM- -9.7 -9.85 - -9.7 -9.85 - V I+ - 450 1000 - 450 1000 µA PD - 9 14 - 9 14 mW ∆VlO/∆T - 4 - - 4 - µV/oC NOTE: 4. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. Typical Applications 10GΩ 10pF +1.5V Picoammeter Circuit The exceptionally low input current (typically 0.2pA) makes the CA3420 highly suited for use in a picoammeter circuit. With only a single 10GΩ resistor, this circuit covers the range from ±1.5pA. Higher current ranges are possible with suitable switching techniques and current scaling resistors. Input transient protection is provided by the 1MΩ resistor in series with the input. Higher current ranges require that this resistor be reduced. The 10MΩ resistor connected to pin 2 of the CA3420 decouples the potentially high input capacitance often associated with lower current circuits and reduces the tendency for the circuit to oscillate under these conditions. 2 1MΩ The meter is placed in series with the gain network, thus eliminating the meter temperature coefficient error term. Supply current in the standby position with the meter undeflected is 300µA. At full-scale deflection this current rises to 800µA. Carbon-zinc battery life should be in excess of 1,000 hours. 500-0-500 µA 7 - 6 CA3420 3 + M ±50pA 4 5 BATTERY RETURNS 1 1.5kΩ ±15pA 1.5kΩ, 1% ±5pA 430Ω, 1% ±1.5pA 150Ω, 1% 11kΩ 68Ω 1% 1kΩ 10kΩ -1.5V High Input Resistance Voltmeter Advantage is taken of the high input impedance of the CA3420 in a high input resistance DC voltmeter. Only two 1.5V “AA” type penlite batteries power this exceedingly high-input resistance (>1,000,000MΩ) DC voltmeter. Full-scale deflection is ±500mV, ±150mV, and ±15mV. Higher voltage ranges are easily added with external input voltage attenuator networks. 10MΩ FIGURE 1. PICOAMMETER CIRCUIT +1.5V 3 22MΩ 10MΩ 6 CA3420 100pF 2 - M ±500mV 4 5 1 500-0-500 µA 7 + BATTERY RETURNS 10kΩ ±150mV 1.5kΩ 1.5kΩ, 1% 1kΩ ±50mV 430Ω, 1% -1.5V ±15mV 1.1kΩ 150Ω, 1% 68Ω 1% FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER 3 CA3420, CA3420A 1.0 OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q19 (mV) INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V) Typical Performance Curves TA = 25oC RL = 100kΩ 0.8 0.6 0.4 0.2 VO- 0 -0.2 VO+ -0.4 VICR- -0.6 VICR+ -0.8 1 5 10 TA = 25oC V- = 0V V+ = 2V V+ = 5V V+ = 10V V+ = 20V 100 1000 0.01 -1.0 0 10 15 0.1 SUPPLY VOLTAGE (V) OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q17 (mV) TA = 25oC V+ = 0V V- = -20V V- = -10V V- = -5V V- = -2V 100 10 0.01 0.1 1 10 1000 100 10 1 101 102 103 105 TA = 25oC VS = ±5V RL = 10kΩ CL = 0pF 0 -45 80 -90 60 -135 -180 40 OPEN LOOP PHASE (DEGREES) FIGURE 6. INPUT NOISE VOLTAGE vs FREQUENCY 100 OPEN LOOP VOLTAGE GAIN (dB) 104 FREQUENCY (Hz) FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT 20 0 101 102 103 104 105 106 FREQUENCY (Hz) FIGURE 7. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE 4 TA = 25oC VS = ±10V VS = ±5V VS = ±1V LOAD (SINKING) CURRENT (mA) 1 10 FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE 1000 1 LOAD (SOURCING) CURRENT (mA) 106 CA3420, CA3420A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 5 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 8 10.92 7 3.81 4 9 Rev. 0 12/93 CA3420, CA3420A Metal Can Packages (Can) T8.C MIL-STD-1835 MACY1-X8 (A1) REFERENCE PLANE A 8 LEAD METAL CAN PACKAGE e1 L L2 L1 INCHES ØD2 4.19 4.70 - 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 N Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - α ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - k C L e BASE AND SEATING PLANE Q BASE METAL Øb1 NOTES 0.185 1 F MAX 0.016 k1 β MIN 0.165 Øe Øb1 Øb MAX A A 2 MIN Øb A ØD ØD1 MILLIMETERS SYMBOL LEAD FINISH Øb2 SECTION A-A NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 0.200 BSC 5.08 BSC - e1 0.100 BSC F - 0.040 - 2.54 BSC 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 12.70 19.05 1 1.27 1 L 0.500 0.750 L1 - 0.050 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - α - β 45o BSC 45o BSC 45o BSC 45o BSC N 8 8 2. Measured from maximum diameter of the product. 3 3 4 Rev. 0 5/18/94 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. 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