IRFD210, SiHFD210 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 200 RDS(on) () VGS = 10 V 1.5 Qg (Max.) (nC) 8.2 Qgs (nC) 1.8 Qgd (nC) 4.5 Configuration Single D Dynamic dV/dt Rating Repetitive Avalanche Rated For Automatic Insertion End Stackable Fast Switching Ease of Paralleling Simple Drive Requirements Compliant to RoHS Directive 2002/95/EC Available RoHS* COMPLIANT HVMDIP DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The 4 pin DIP package is a low cost machine-insertable case style which can be stacked in multiple combinations on standard 0.1" pin centers. The dual drain serves as a thermal link to the mounting surface for power dissipation levels up to 1 W. G S G S D N-Channel MOSFET ORDERING INFORMATION Package HVMDIP IRFD210PbF SiHFD210-E3 IRFD210 SiHFD210 Lead (Pb)-free SnPb ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 200 Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at 10 V TA = 25 °C TA = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor UNIT V 0.60 0.38 A 4.8 0.0083 W/°C EAS 79 mJ Currenta IAR 0.60 A Repetitive Avalanche Energya EAR 0.10 mJ Single Pulse Avalanche Energyb Repetitive Avalanche Maximum Power Dissipation TA = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s PD 1.0 W dV/dt 5.0 V/ns TJ, Tstg - 55 to + 150 300d °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 82 mH, Rg = 25 , IAS = 1.2 A (see fig. 12). c. ISD 3.3 A, dI/dt 70 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 www.vishay.com 1 IRFD210, SiHFD210 Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient SYMBOL TYP. MAX. UNIT RthJA - 120 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 200 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.30 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance IGSS IDSS RDS(on) gfs VGS = ± 20 V - - ± 100 VDS = 200 V, VGS = 0 V - - 25 VDS = 160 V, VGS = 0 V, TJ = 125 °C - - 250 - - 1.5 0.10 - - S - 140 - ID = 0.36 Ab VGS = 10 V VDS = 50 V, ID = 0.36 Ab μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg VGS = 0 V VDS = 25 V f = 1.0 MHz, see fig. 5 VGS = 10 V ID = 3.3 A, VDS = 160 V see fig. 6 and 13b - 53 - - 15 - - - 8.2 - - 1.8 Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 4.5 Turn-On Delay Time td(on) - 8.2 - Rise Time Turn-Off Delay Time Fall Time tr td(off) LD Internal Source Inductance LS nC - 17 - - 14 - - 8.9 - - 4.0 - - 6.0 - - - 0.60 S - - 4.8 TJ = 25 °C, IS = 0.60 A, VGS = 0 Vb - - 2.0 - 150 310 ns - 0.60 1.4 μC VDD = 100 V, ID = 3.3 A Rg = 24 , RD = 30 , see fig. 10b tf Internal Drain Inductance pF Between lead, 6 mm (0.25") from package and center of die contact D ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/μsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width 300 μs; duty cycle 2 % www.vishay.com 2 Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 IRFD210, SiHFD210 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) TA = 25 °C Fig. 1 - Typical Output Characteristics, TA = 25 °C Fig. 3 - Typical Transfer Characteristics TA = 150 °C Fig. 2 - Typical Output Characteristics, TA = 150 °C Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRFD210, SiHFD210 Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage TA = 25 °C TJ = 150 °C SINGLE PULSE Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 8 - Maximum Safe Operating Area Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 IRFD210, SiHFD210 Vishay Siliconix RD VDS VGS D.U.T. ID, Drain Current (A) Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % TA, Ambient Temperature (°C) 10 % VGS td(on) td(off) tf Fig. 10b - Switching Time Waveforms Thermal Response (ZthJA) Fig. 9 - Maximum Drain Current vs. Ambient Temperature tr t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 www.vishay.com 5 IRFD210, SiHFD210 Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T. Rg + - IAS V DD VDS 10 V 0.01 W tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 IRFD210, SiHFD210 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91129. Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 www.vishay.com 7 Package Information Vishay Siliconix HVM DIP (High voltage) 0.248 [6.29] 0.240 [6.10] 0.043 [1.09] 0.035 [0.89] 0.197 [5.00] 0.189 [4.80] 0.133 [3.37] 0.125 [3.18] 0.180 [4.57] 0.160 [4.06] 0.094 [2.38] 0.086 [2.18] A L 0.160 [4.06] 0.140 [3.56] 0° to 15° 2x 0.017 [0.43] 0.013 [0.33] 0.045 [1.14] 2 x 0.035 [0.89] E min. 0.024 [0.60] 4x 0.020 [0.51] 0.100 [2.54] typ. E max. INCHES MILLIMETERS DIM. MIN. MAX. MIN. A 0.310 0.330 7.87 MAX. 8.38 E 0.300 0.425 7.62 10.79 L 0.270 0.290 6.86 7.36 ECN: X10-0386-Rev. B, 06-Sep-10 DWG: 5974 Note 1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions. Document Number: 91361 Revision: 06-Sep-10 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000