HCS161MS TM Radiation Hardened Synchronous Counter September 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s >1010 MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 • Cosmic Ray Upset Immunity 2 x 10-9 Error/Bit Day (Typ) P2 5 12 Q2 • Latch-Up Free Under Any Conditions P3 6 11 Q3 • Military Temperature Range: -55oC to +125 oC PE 7 10 TE GND 8 • Dose Rate Upset RAD (Si)/s 20ns Pulse • Significant Power Reduction Compared to LSTTL ICs 9 SPEN • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16 TOP VIEW • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCS161MS is a Radiation Hardened 4-Input Binary; synchronous counter featuring asynchronous reset and lookahead carry logic. The HCS161 has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (p0 - p3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCS161MS has two count output, IC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count. MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE GND 8 9 SPE The HCS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS161MS is supplied in a 16 lead Ceramic flatpack (K suf fix) or a SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS161DMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCS161KMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack +25oC Sample 16 Lead SBDIP HCS161K/Sample +25oC Sample 16 Lead Ceramic Flatpack HCS161HMSR +25oC Die Die DB NA HCS161D/Sample 518755 FN2469.2 Spec Number 193 HCS161MS Functional Diagram 3 5 4 P0 VCC 6 P2 P1 7 P3 PE 10 TE 16 GND 8 SPE 9 T FF0 R SPE T FF1 R SPE T FF2 R SPE T FF3 R SPE D D D D Q CL CP Q CL Q Q CL CL 2 MR R 1 Q0 Q1 14 Q2 13 Q3 12 TC 11 15 TRUTH TABLE INPUTS OPERATING MODE OUTPUTS MR CP PE TE SPE Pn Qn TC Reset (Clear) L X X X X X L L Parallel Load H X X I I L L H X X I h H (a) Count H h h h (c) X Count (a) Inhibit H X I (b) X h (c) X qn (a) H X X I (b) h (c) X qn L H = High Level, L = Low Level, X = Immaterial, = Transition from low to high Spec Number 194 518755 Specifications HCS161MS Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . . ±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. Operating Conditions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . . 100ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Quiescent Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Noise Immunity Functional Test TEMPERATURE MIN MAX UNITS 1 +25oC - 40 µA 2, 3 +125oC, -55oC - 750 µA 1 +25oC 4.8 - mA 2, 3 +125oC, -55oC 4.0 - mA 1 +25oC -4.8 - mA 2, 3 +125oC, -55oC -4.0 - mA VCC = 4.5V, VIH = 3.15V, IOL = 50µA, VIL = 1.35V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 5.5V, VIH = 3.85V, IOL = 50µA, VIL = 1.65V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 3.15V, IOH = -50µA, VIL = 1.35V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIH = 3.85V, IOH = -50µA, VIL = 1.65V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIN = VCC or GND 1 +25oC - ±0.5 µA 2, 3 +125oC, -55oC - ±5.0 µA 7, 8A, 8B +25oC, +125oC, -55oC - - - SYMBOL ICC IOL IOH VOL VOH IIN FN LIMITS GROUP A SUBGROUPS (NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC) NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. Spec Number 195 518755 Specifications HCS161MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER CP to Qn CP to TC TE to TC MR to Qn MR to TC (NOTES 1, 2) CONDITIONS SYMBOL TPHL TPLH TEMPERATURE MIN MAX UNITS 9 +25oC 2 34 ns 10, 11 +125oC, -55oC 2 39 ns 9 +25oC 2 37 ns 10, 11 +125oC, -55oC 2 42 ns 9 +25oC 2 23 ns 10, 11 +125oC, -55oC 2 26 ns 9 +25oC 2 41 ns 10, 11 +125oC, -55oC 2 45 ns 9 +25oC 2 46 ns 10, 11 +125oC, -55oC 2 51 ns VCC = 4.5V TPHL TPLH VCC = 4.5V TPHL TPLH VCC = 4.5V TPHL VCC = 4.5V TPHL LIMITS GROUP A SUBGROUPS VCC = 4.5V NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Capacitance Power Dissipation CPD Input Capacitance Output Transition Time CIN TTHL TTLH CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1 +25oC - 54 pF 1 +125oC, -55oC - 84 pF 1 +25oC - 10 pF 1 +125oC - 10 pF 1 +25oC - 15 ns 1 +125oC - 22 ns VCC = 5.0V, f = 1MHz VCC = 5.0V, f = 1MHz VCC = 4.5V NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Quiescent Current SYMBOL ICC (NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND 200K RAD LIMITS TEMPERATURE +25 oC o MIN MAX UNITS - 0.75 mA Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V +25 C 4.0 - mA Output Current (Source) IOH VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V +25oC -4.0 - mA Spec Number 196 518755 Specifications HCS161MS TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER 200K RAD LIMITS (NOTES 1, 2) CONDITIONS SYMBOL TEMPERATURE MIN MAX UNITS - 0.1 V Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50µA +25oC Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOH = -50µA +25oC VCC -0.1 - V VCC = 5.5V, VIN = VCC or GND +25oC - ±5 µA Input Leakage Current IIN Noise Immunity Functional Test FN o VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) +25 C - - - TPHL VCC = 4.5V +25oC 2 39 ns TPLH VCC = 4.5V +25oC 2 39 ns TPHL VCC = 4.5V +25oC 2 43 ns TPLH VCC = 4.5V +25oC 2 43 ns TPHL VCC = 4.5V +25oC 2 27 ns TPLH VCC = 4.5V +25oC 2 27 ns MR to Qn TPHL VCC = 4.5V +25oC 2 45 ns MR to TC TPHL VCC = 4.5V +25oC 2 51 ns CP to Qn CP to TC TE to TC NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V. 3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP DELTA LIMIT ICC 5 12µA IOL/IOH 5 -15% of 0 Hour PARAMETER TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test III (Postburn-In) 100%/5004 1, 7, 9 PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Group D READ AND RECORD ICC, IOL/H Subgroups 1, 2, 3, 9, 10, 11 NOTE: 1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised. Spec Number 197 518755 Specifications HCS161MS TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1) NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V 50kHz 25kHz - 16 - - - 1 - 7, 9, 10, 16 - - 11 - 15 1, 3, 5, 7, 9, 10, 16 2 - STATIC BURN-IN I TEST CONDITIONS (Note 1) 11 - 15 1 - 10 STATIC BURN-IN II TEST CONNECTIONS (Note 1) 11 - 15 8 DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2) - 4, 6, 8 NOTES: 1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in. 2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in. TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V ± 0.5V 11 - 15 8 1 - 7, 9, 10, 16 NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Spec Number 198 518755 HCS161MS Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Delta Calculation (T0-T1) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Interim Electrical Test 3 (T3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% PIND, Method 2020, Condition A 100% Final Electrical Test 100% External Visual 100% Fine/Gross Leak, Method 1014 100% Serialization 100% Radiographic, Method 2012 (Note 3) 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 199 518755 HCS161MS AC Timing Diagrams AC Load Circuit DUT TEST POINT VIH INPUT VS CL VIL RL TPLH TPHL VOH CL = 50pF VS OUTPUT RL = 500Ω VOL TTLH VOH TTHL 80% 20% VOL 80% 20% OUTPUT AC VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. William Graisse, 3 1006 Lausanne Switzerland TEL: +41 21 6140560 FAX: +41 21 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 Spec Number 200 518755 HCS161MS Die Characteristics DIE DIMENSIONS: 104 x 86 mils 2650 x 2190mm METALLIZATION: Type: AlSi Metal Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100µm x 100µm 4 x 4 mils Metallization Mask Layout HCS161MS CP (2) MR (1) VCC (16) (15) TC P0 (3) (14) Q0 P1 (4) (13) Q1 P2 (5) (12) Q2 P3 (6) (11) Q3 PE (7) (8) GND (9) SPE (10) TE NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS161 is TA14346A. Spec Number 201 518755