3 phase BLDC Controller IC SI-6633C Application Note July, 2013 Ver.1.1 MCD division low voltage motor group Sanken Electric Co., Ltd. This application note is applied to SI-6633C, which is controller for 3-phase brushless motor. About the latest information, please refer to our charge section. (Index) 1. General description ............................................................................. 3 2. Features ............................................................................................. 3 3. Package information, recommended foot print ...................................... 4 4. Block diagram and application circuit .................................................. 5 5. Pin assignment ................................................................................... 6 6. Absolute maximum rating ................................................................... 7 7. Recommended operating range ............................................................ 7 8. Power dissipation ............................................................................... 7 9. Electrical characteristics ...................................................................... 8 10. Truth table, timing chart .................................................................... 10 10.1. 10.2. 10.3. 10.4. 10.5. 10.6. 10.7. 10.8. 10.9. Excitation control input (Hall and Logic input).......................... 10 FL output (flag output) ............................................................... 10 FG signal .................................................................................... 11 Internal PWM control ................................................................. 11 PWM control input (PWM and Decay) ...................................... 12 Disable function for synchronous rectification (Fast Decay only)12 OCP control ................................................................................ 13 Motor lock .................................................................................. 13 Enable and Break ........................................................................ 14 Sanken Electric Co., Ltd. 1 / 21 SI-6633C Application Note Ver. 1.1 11. Functional description; individual block ............................................. 15 11.1. UVLO ......................................................................................... 15 11.2. TSD ............................................................................................ 15 11.3. OVP ............................................................................................ 15 11.4. Charge Pump .............................................................................. 15 11.5. Gate Drive and OCP ................................................................... 16 11.6. Hall Amp .................................................................................... 16 11.7. FG Gen ....................................................................................... 16 11.8. Commutation and Control Logic ................................................ 16 11.9. Internal PWM ............................................................................. 16 11.10. OSC ............................................................................................ 17 11.11. Lock Detect ................................................................................ 17 12. Pin diagram...................................................................................... 18 13. Operation waveform ......................................................................... 19 14. Evaluation board circuit diagram ....................................................... 20 15. Pattern layout for evaluation board..................................................... 21 Sanken Electric Co., Ltd. 2 / 21 SI-6633C Application Note Ver. 1.1 1. General description This is a pre-driver IC for a 3-phase brushless DC motor. This device can be combined with a wide variety of N channel power MOSFETs, and is ready for motor power voltage of up to 30V. Phase is switched by hall elements arranged at an interval of 120°. This is provided with functions of PWM electric current control to limit inrush electric current, and of overheat shutdown and synchronous rectification, etc. The synchronous rectification function rectifies by MOSFET of low temperature resistance instead of body diode and can reduce power loss at the time of regeneration. This product has enable, direction, and brake inputs, and can control electric current by internal PWM. In addition, rotation of the motor can be detected by logic output FG. 2. Features N channel MOSFET of 6 elements is driven. Ready for hall input Various protection functions are built in. Overvoltage protection Low voltage protection Overcurrent protection (ready for supply fault, load short-circuit) Thermal protection Lock detection Through-current prevention function Alarm output function at time of error Synchronous rectification to reduce power loss PWM current limit FG output Standby mode Sanken Electric Co., Ltd. 3 / 21 SI-6633C Application Note Ver. 1.1 3. Package information, recommended foot print Unit: mm QFN36Pin package with thermal pad Recommended foot print (red line area) Sanken Electric Co., Ltd. 4 / 21 SI-6633C Application Note Ver. 1.1 4. Block diagram and application circuit VBB=10～30V VDD=3～5.5V V D D V B B HU+ Hall HU- UVLO CPL OVP HV+ Hall Amp Hall CPH Charge Pump Drv.Reg Int.Reg V C P HallU HV- GHU HallV HW+ Hall SU TSD HallW HW- GLU GHV Gate Drive & OCP FL SV GLV FG FG Gen Comm & Control Lock Detect Logic GHW OSC コ ン ト ロ ー ラ SW GLW Dir Enable Sen Brake ÷10 PWM Decay C L D C O S C G N D Sanken Electric Co., Ltd. R e f 5 / 21 SI-6633C Application Note Ver. 1.1 Pin assignment FL FG VDD COSC 35 34 33 32 31 30 GND Break 36 CLD Ena Pin function PWM signal input pin Current direction switching pin Decay signal input pin Ground pin Capacitor pin for charge pump suction Low Capacitor pin for charge pump suction High Motor power supply input pin Capacitor pin for charge pump charge up Ground pin Output pin OUTW High side gate output pin W Low side gate output pin W Output terminal OUTV High side gate output pin V Low side gate output pin V Output pin OUTU High side gate output pin U Low side gate output pin U Ground pin Current detection pin Internal PWM current setting pin Hall device input pin HW+ Hall device input pin HWHall device input pin HV+ Hall device input pin HVHall device input pin HU+ Hall device input pin HUGround pin Lock detection time setting pin Switching frequency setting pin Logic power supply pin FG output pin Abnormality detection output pin Brake input pin Lock counter reset signal And Enable signal input pin Ground pin GND Pin name PWM Dir Decay GND CPL CPH VBB VCP GND SW GHW GLW SV GHV GLV SU GHU GLU GND Sen Ref HW+ HWHV+ HVHU+ HUGND CLD COSC VDD FG FL Brake Ena GND 2 9 2 8 PWM 1 27 HU- Dir 2 26 20 HU+ Decay 3 25 HV- GND 4 24 HV+ CPL 5 23 HW- CPH 6 22 HW+ VBB 7 21 REF VCP 8 20 SEN GND 9 19 GND 12 13 14 15 16 SV GHV GLV SU 1 7 1 8 GLU 11 GHU 10 GLW SI-6633C SW No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GHW 5. Sanken Electric Co., Ltd. 6 / 21 SI-6633C Application Note Ver. 1.1 6. Absolute maximum rating Item Power supply voltage Output voltage Logic input voltage Ref input voltage Detection voltage Maximum junction temperature Storage temperature Operation ambient temperature Package thermal resistance (*) 7. Conditions Rated value 4 phase board used (QFN36) 38 38 -0.3 - 6 -0.3 - 6 ±2 150 -40 - 150 -20 - 85 TBD Unit V V V V V °C °C °C °C /W RθJP Between junction and pad TBD °C /W The output current may be limited by duty cycle, ambient temperature, and heat release state. The specified rated current and maximum junction temperature (Tj=150°C) shall not be exceeded under any condition. Recommended operating range Item Power supply voltage Logic input voltage Symbol VBB VDD VIN(Logic) Rated value 10 - 30 3 - 5.5 0 - 5.5 Unit V V V Ref input voltage VRef 0.5 - 5.5 V Detection voltage Package temperature VSENSE TC ±0.5 105 V °C Operation ambient temperature TA -20 - 85 °C Control power supply voltage 8. Symbol VBB VOUT VIN(Logic) VRef VSENSE TJ(max) Tstg TA RθJA Notes Current control accuracy is significantly reduced at 0.5 V or less. Power dissipation Derating when package used TBD ※when JEDEC standard 4-phase board used Sanken Electric Co., Ltd. 7 / 21 SI-6633C Application Note Ver. 1.1 9. Electrical characteristics TA=+25°C、VBB=24V, VDD=5V, unless otherwise specified Rated value Item Symbol Unit Test conditions MIN TYP MAX 10 - VBBOV V - - TBD mA Operation state (output is off) - - (200) μA Standby mode 3 - 5.5 V in operation - - TBD mA Operation state (output is off) - - (500) μA Standby mode VIN(0) - - VDD×0.25 V VIN(1) VDD×0.75 - - V IIN(0) - ±1 ±10 μA VIN(0) , VIN=0V IIN(1) - ±1 ±10 μA VIN(1) , VIN=5V Input pin filter tLOGIC - (0.5) - μs COSC pin oscillation frequency fOSC - 25 - KHz High side output voltage VGS(H) 6 - (9) V IGATE=2mA for Vbb Low side output voltage VGS(L) 6 - (9) V IGATE=2mA Drive current IGATE TBD 30 ‐ mA Dead time tdead TBD 1000 TBD ns Ref pin input current Iref - ±10 - μA Ref pin input voltage range VRef 0.5 - 5.5 V Sen pin input current ISen - ±10 - μA VSen=0 - 1V Detection voltage VSen - VREF×0.1 - V Current detection filter time tLPFSen - 2 (4) μs VRef=1 - 5V Design assurance Output Drivers VBB voltage range Main power supply current VBB IBB in operation Control Logic VDD voltage range VDD VDD pin current IDD Logic input voltage Logic input current COSC=330pF Gate Drive GH=GL=4V、VCP=VBB+TBD Internal PWM ※1：Use Typ data as design information. ※2：Negative current in the table represents current flowing out from the product pin. Sanken Electric Co., Ltd. 8 / 21 SI-6633C Application Note Ver. 1.1 TA=＋25°C, VBB=24V、VDD=5V, unless otherwise specified Rated value Item Symbol Unit MIN TYP MAX (0.7) Test conditions Protection FL output saturation voltage VFI(ON) - 0.45 FL output pin on current IFI(ON) (5) 7.5 FL output leak current IFI(OFF) - - Overcurrent detection voltage VOCP (1.4) Overcurrent detection filter time tFLTOCP V IFG=2mA mA VFI=2V 50 μA VFG=5.5V 1.5 (1.65) V Low side MOSFET detection (between OUT and GND) - TBD TBD μs Design assurance OCP output OFF timer count NOCP_OFF - 256 - VBB overcurrent protection threshold voltage VBBOV - 35 (37) V VBB overvoltage protection hysteresis VBBOVhys - 2 - V CLD pin oscillation frequency fLD - 128 - Hz Lock detection timer count NLD - 256 - Thermal protection operation temperature TJTSD - 170 - °C Thermal protection hysteresis VDD low voltage protection release voltage TJTSDhys - (15) - °C VDDUV - 2.8 2.95 V VDD low voltage protection hysteresis VBB low voltage protection release voltage VDDUVhys - (0.15) - V VBBUV - (9) (9.75) V VBB low voltage protection hysteresis VBBUVhys - TBD - V FG output saturation voltage VFG(sat) - 0.45 (0.7) V IFG=2mA FG output leak current IFGlkg - - 50 μA VFG=5.5V VIN=0.2～4V CLD=0.1μF When temperature rises Design assuarnce When VDD voltage rises When VBB voltage rises FG Hall Logic Hall input current IHALL -2 -0.1 1 μA Common mode input voltage range VCMR 0.2 - (4) V AC input voltage range VHALL 60 - - mVp-p Hysteresis VHYS TBD 40 (VHALL) mV Pulse removal filter tpulse - 2 - μs Design assurance ※1：Use Typ data as design information. ※2：Negative current in the table represents current flowing out from the product pin. Sanken Electric Co., Ltd. 9 / 21 SI-6633C Application Note Ver. 1.1 10. Truth table, timing chart 10.1. Excitation control input (Hall and Logic input) Table. 10-1 Hall input and each control input Input 状態名 State F1 F2 F3 F4 F5 F6 Error Error brake disable※2 StandBy ※1 HallU + + + + X X X ※1 HallV + + + + X X X HallW + + + + X X X ※1 Enable L L L L L L L L L H H Brake H H H H H H H H L H L OUTU H H Z L L Z Z Z L Z Z Output status DIR=H OUTV OUTW OUTU L Z L Z L L H L Z H Z H Z H H L H Z Z Z Z Z Z Z L L L Z Z Z Z Z Z DIR=L OUTV OUTW H Z Z H L H L Z Z L H L Z Z Z Z L L Z Z Z Z X：don‟t care Z：High Impedance ※1 HallU、HallV、HallW：‟+‟=H+>H- 、‟-„ =H+<H※2 There are some conditions for becoming Disable. There are some conditions for becoming Disable. These are internal logic signal names. See the diagrams for conditions for becoming Disable. 10.2. FL output (flag output) Table.10-2 FL output FL output State Hi-Z Operation state L Abnormality detection Low voltage protection (UVLO) Thermal shutdown (TSD) Overvoltage protection (OVP) Overcurrent protection and output OFF period (OCP) ・Note that the internal circuit incompletely operates in a state of low power voltage (VBB, VDD) and correct diagnosis result may not be output. Sanken Electric Co., Ltd. 10 / 21 SI-6633C Application Note Ver. 1.1 10.3. FG signal Fig. 10-1 DIR HallU HallV HallW FG ・Refer to “Excitation control input (hall & Logic input)” for HalU, HallV and HallW. ・FG is put into toggle-operation in which the logic reverses every time when excitation phase is switched by hall input. 10.4. Internal PWM control Fig.10-2 tLPFSen tLPFSen COSC 0.1×REF Sen Zoom 拡大 No sensing due to filter フィルタにより無感 Sen OUTx Excitation operation ON 励磁動作ON OUTx 同期整流制御ON Synchronous rectification forced ON ・When not using this control, connect Sen to GND, and connect REF to VDD. Sanken Electric Co., Ltd. 11 / 21 SI-6633C Application Note Ver. 1.1 10.5. PWM control input (PWM and Decay) Fig. 10-3 Decay OFF PWM ON AA相 phase H/S L/S H/S L/S B B相 phase L/S H/S L/S H/S H/S L/S H/S L/S Output ON 出力オン state 状態 L/S ・Input signals on PWM pin and Decay pin are neglected at the time of Brake. ・When PWM control input is not used, the pin should be set to „L.‟ 10.6. Disable function for synchronous rectification (Fast Decay only) Fig. 10-4 PWM chopping PWMチョッピング ON OFF ON OFF ON OFF ON OFF COSC 1 2 3 1 2 3 1 2 3 4 5 6 7 1 A相 H/S A phase L/S H/S L/S H/S L/S OFF H/S L/S B phase B相 L/S H/S L/S H/S L/S H/S OFF L/S H/S 2 Output ON 出力オン state 状態 ・If a PWM chopping OFF period has continued for a certain time (approximately 7 cycles of COSC), synchronous rectification operation is stopped. ・This function does not operate at time of Brake. Sanken Electric Co., Ltd. 12 / 21 SI-6633C Application Note Ver. 1.1 10.7. OCP control Fig. 10-5 1.5V OUTx Output OFF 出力OFF 1 2 3 Output OFF 出力OFF 254 255 256 1 2 COSC FL 出力’Z’ Output „Z‟ Output „L‟ 出力’L’ （※Numerical values in the diagram are typ values） ・After overcurrent is detected, output is OFF for a certain time (256 cycles of COSC), and then auto-restarts. ・Timer count for output OFF time and FL output release are performed in timing of top of COSC. ・OFF period is released in timing of bottom of COSC. ・Timer count for output OFF time is not also reset as an output Disable. 10.8. Motor lock Fig. 10-6 RST CLD 1 2 1 2 255 出力’Z’ Output „Z‟ FLAG 256 1 2 Output „L‟ 出力’L’ COSC 出力 ON OFF ON ・Lock detection operates only in a rotation state (Enable pin =„L‟, Brake pin =„H‟). ・If there occurred no signal (RST) to release the lock detection for approximately 256 cycles in the oscillation cycle of CLD, it is judged to be motor lock and output is shut down. ・For RST signal, see Fig. 10 - 6 and “Lock Detect” in “11. Circuit configuration (individual circuit).” Sanken Electric Co., Ltd. 13 / 21 SI-6633C Application Note Ver. 1.1 10.9. Enable and Break Fig. 10-7 Enable Brake COSC 1 動作 LDLDカウンター counter Operation Operation state 動作状態 2 Reset リセット 1 Operation Reset 動作 リセット 回転 Rotation 2 Operation 動作 Brake ブレーキ 3 4 1 Operation 動作 Reset リセット 回転 Rotation Disable 2 Reset リセット Rotation 回転 Standby スタンバイ Disable ・Enable pin has the following three functions in a sequence of prioritized operation. ①Standby control (combination with Brake pin) Combination of Brake=„L‟ and Enable=„H‟ brings the operating state into standby, and out of this combination it restarts from the standby. In addition, the charge pump circuit and internal Reg stop at the time of standby. For this reason, it takes some time until start of actual operation from release of standby. Furthermore, the FL pin becomes „H‟ at the time of standby, and output is performed according to the internal state after release. ②Lock counter reset The lock counter is in reset state during a period of Enable=‟H‟. ③Output Enable/Disable operation Output Disable occurs when the number of oscillations (counted in timing of bottom) of COSC is the 4th time after „L‟ on the Enable pin changes to „H‟. Output Enable occurs in the timing of on-trigger (bottom of COSC) next after „H‟ on the Enable pin changes to „L‟. Sanken Electric Co., Ltd. 14 / 21 SI-6633C Application Note Ver. 1.1 11. Functional description; individual block 11.1. UVLO This circuit protects when the power state reaches down to normally operable voltage value or less. Voltage raised by the internal powers of the VDC, IC and the charge pump is monitored with low voltage protection. The output is shut down when the voltage monitored is lower than the set value. 11.2. TSD This is a protection circuit to monitor junction temperature of the control IC and prevent thermal shutdown of the product. The thermal shutdown protection shuts down the output when temperature of the IC rises up to near 170°C. Then, when the temperature of the IC lowers by approximately 15°C, output shutdown is released. In addition, this function is not used on a routine operation basis, therefore, conduct thermal design so as to avoid this function from operating and use. 11.3. OVP When main power voltage (VBB) applied to the product increases to approximately absolute maximum ratings, output is shut down and the product moves to an overvoltage protection (OVP) in which the most withstand is obtained against the overvoltage. The OVP of this product functions at approximately 35V. In addition, even if any voltage higher than this is applied, the motor cannot be operated. 11.4. Charge Pump This is a boost power to drive Nch MOSFET on the high side (upper arm). The CP pin is in a potential state where its voltage is higher than that of the main power (VBB) by approximately 7V during normal operation. A capacitor is required for boost operation, so be careful of the following. ☆Between CP and VBB The CP pin has higher potential than the VBB pin during normal operation, however, the voltage on the CP pin may lower by approximately 1V relative to the VBB pin during a time by which the voltage of the CP pin is increased. ☆Between CPH and CPL Since voltage equivalent to that on the VBB is applied, be careful of the withstand voltage. Sanken Electric Co., Ltd. 15 / 21 SI-6633C Application Note Ver. 1.1 11.5. Gate Drive and OCP The Gate Drive is a circuit for pre-driver to receive signals of Control Logic and drive output Nch MOS FET. A dead time is also set by this block. The dead time prevents through current which must be noted when the high side (upper arm) and low side (lower arm) are simultaneously put into switching operation. In addition, this product is also equipped with an overcurrent protection circuit (OCP). This overcurrent protection circuit monitors drain voltage (voltage between OUT pin and GND) when low side MOSFET is ON, and the threshold voltage is 1.5V (typ). 11.6. Hall Amp Connect standard hall elements. 11.7. FG Gen This receives signals from the Hall Amp and outputs a motor rotation pulse from the FG pin. This simultaneously generates signals for resetting lock detection. 11.8. Commutation and Control Logic This synthesizes the ON/OFF signal of power MOSFET sent to the Gate Drive from positional signals, PWM control signals obtained from the Hall Amp, and output off signals from the protection circuit system or the like. 11.9. Internal PWM This controls peak current flowing through the motor coil according to the externally input current reference signal (analog voltage). This is equipped with a filter for noise generated when chopping is on. For PWM operation, chopping is turned on by a trigger signal from the OSC, and chopping is turned off when the coil current reaches the set current (peak current value I Opeak). The switching frequency becomes constant at fOSC described in the term of OSC. Set value of IOpeak can be calculated by the following calculating formula. I Opeak 0.1 V REF RS [A] Wherein, VREF: REF pin voltage RS: Current detecting resistance value When this function is not used, the internal PWM control does not function by connecting the Sen pin to GND and connecting the REF pin to VDD. Sanken Electric Co., Ltd. 16 / 21 SI-6633C Application Note Ver. 1.1 11.10. OSC This determines many operation timings and time of the product. For this reason, it is necessary to operate in oscillation by always connecting a capacitor. Oscillation frequency fOSC is determined by the capacitor connected to the OSC pin and is calculated by the following calculating formula. f OSC kHz 8.3 C OSC nF 11.11. Lock Detect This functions to detect a motor lock state. When there is a state in which a hall input signal does not change for a certain time which is determined by a capacitor (CLD) on the CLD pin and internal frequency dividing rate, it is judged to be a motor lock state and power to the motor is shut down. At the same time, voltage on the FL pin becomes Low to inform that it is in a lock state. The relationship between the CLD pin capacity and lock detecting time t LD is calculated by the following calculating formula. t LD 20 C LD F In order to reset the internal counter and return from shutdown state after lock detection, it is necessary to enter any of the following signals. ☆Change hall input. ☆Set logic of Brake pin to brake („L‟). ☆Set logic of Enable pin to Disable („H‟). ☆Switch logic of Dir pin. ☆Turn on power again. When the motor rotates by any cause and a hall input is switched after the motor stops by lock detection, the counter is reset and return from the lock detection status. If you attempt to compulsorily avoid lock detection in a state where the motor is excited, switch logic of the Dir pin in a cycle shorter than the lock detection time, or enter a pulse of „H‟ with a narrow width (less than approximately 4 cycles of COSC) avoiding a Disable state. Furthermore, in operations of protection functions (Reg, and UVLO、TSD、OVP、OCP between CP and VBB), the lock counter is not reset and the timer count is continued. When the motor stops by these protection functions, it is judged to be locked and the motor may be put into stop state by this protection function. Sanken Electric Co., Ltd. 17 / 21 SI-6633C Application Note Ver. 1.1 12. Pin diagram No. Pin Sanken Electric Co., Ltd. 18 / 21 SI-6633C Application Note Ver. 1.1 13. Operation waveform TBD Sanken Electric Co., Ltd. 19 / 21 SI-6633C Application Note Ver. 1.1 14. Evaluation board circuit diagram Sanken Electric Co., Ltd. 20 / 21 SI-6633C Application Note Ver. 1.1 15. Pattern layout for evaluation board Component side Solder side ※Please note that there are some locations (such as pattern on QFN land part) partly different from the actual one due to the influence of PDF formatting. Sanken Electric Co., Ltd. 21 / 21