HCS166MS September 1995 Radiation Hardened 8-Bit Parallel-Input/Serial Output Shift Register Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD s(Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Fanout (Over Temperature Range) - Standard Outputs - 10 LSTTL Loads • Military Temperature Range: -55oC to +125oC DS 1 16 VCC D0 2 15 PE D1 3 14 D7 D2 4 13 Q7 D3 5 12 D6 CE 6 11 D5 CP 7 10 D4 GND 8 9 MR • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCS166MS is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable (PE) input. When the PE is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into internal bit position Q0 from Serial Data Input (DS), and the remaining bits are shifted one place to the right (Q0 → Q1 → Q2m etc.) with each positive-going clock transition. For expansion of the register in parallel to serial converters, the Q7 output is connected to the DS input of the succeeding stage. DS 1 16 VCC D0 2 15 PE D1 3 14 D7 D2 4 13 Q7 D3 5 12 D6 CE 6 11 D5 CP 7 10 D4 GND 8 9 MR Ordering Information The clock input is a gated OR structure which allows one input to be used as an active LOW Clock Enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and con be reversed for layout convenience. The LOW-to-HIGH transition of CE input should only take place while the CP is HIGH for predictable operation. A LOW on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state. The HCS166MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. PART NUMBER SCREENING LEVEL PACKAGE HCS166DMSR -55oC to +125oC Intersil Class S 16 Lead Equivalent SBDIP HCS166KMSR -55oC to +125oC Intersil Class S 16 Lead Equivalent Ceramic Flatpack HCS166D/ Sample +25oC Sample 16 Lead SBDIP HCS166K/ Sample +25oC Sample 16 Lead Ceramic Flatpack HCS166HMSR +25oC Die Die The HCS166MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 250 TEMPERATURE RANGE Spec Number File Number 518758 2482.2 HCS166MS Functional Diagram D0 D1 D2 D3 D4 D5 D7 D6 CP CE DS PE MR Q7 TRUTH TABLE INPUTS PARALLEL INTERNAL Q STATES SERIAL D0 - D7 Q0 Q1 X X X L L L L X X Q00 Q10 Q0 L X a...h a b h H L H X H Q0n Q6n H H L L X L Q0n Q6n H X H X X Q00 Q10 Q70 MASTER RESET PARALLEL ENABLE CLOCK ENABLE CLOCK L X X H X L H L H H = High Level L = Low Level X = Immaterial = Transition from low to high level OUTPUT Q7 a . . . h = The level of steady state input at inputs D0 thru D7, respectively. Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady state input conditions were established. Q0n, Q6n = the level of Q0 or Q6, respectively, before the most recent transition of the clock. Spec Number 251 518758 Specifications HCS166MS Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. Operating Conditions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .500ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Quiescent Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Noise Immunity Functional Test GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 40 µA 2, 3 +125oC, -55oC - 750 µA 1 +25oC 4.8 - mA 2, 3 +125oC, -55oC 4.0 - mA 1 +25oC -4.8 - mA 2, 3 +125oC, -55oC -4.0 - mA VCC = 4.5V, VIH = 3.15V, IOL = 50µA, VIL = 1.35V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 5.5V, VIH = 3.85V, IOL = 50µA, VIL = 1.65V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 3.15V, IOH = -50µA, VIL = 1.35V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIH = 3.85V, IOH = -50µA, VIL = 1.65V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIN = VCC or GND 1 +25oC - ±0.5 µA 2, 3 +125oC, -55oC - ±5.0 µA 7, 8A, 8B +25oC, +125oC, -55oC - - - (NOTE 1) CONDITIONS SYMBOL ICC IOL IOH VOL VOH IIN FN VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 2) LIMITS NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. Spec Number 252 518758 Specifications HCS166MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL CP or CE to Q7 MR to Q7 TPHL TPLH VCC = 4.5V TPHL VCC = 4.5V GROUP A SUBGROUPS LIMITS TEMPERATURE MIN MAX UNITS 9 +25oC 2 32 ns 10, 11 +125oC, -55oC 2 37 ns 9 +25oC 2 31 ns 10, 11 +125oC, -55oC 2 36 ns NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation SYMBOL CPD (NOTE 1) CONDITIONS VCC = 5.0V, f = 1MHz TEMPERATURE MIN MAX UNITS +25oC - 65 pF - 81 pF +25oC - 10 pF +125oC - 10 pF +25oC - 15 ns - 22 ns 30 - MHz 20 - MHz 20 - ns 30 - ns 16 - ns 24 - ns 16 - ns 24 - ns 1 - ns 1 - ns 0 - ns 0 - ns 29 - ns 44 - ns 0 - ns 0 - ns +125oC, Input Capacitance Output Transition Time (Figure 1) Clock Frequency (Figure 1) CIN TTHL TTLH fmax VCC = 5.0V, f = 1MHz VCC = 4.5V +125oC, tw tw Hold Time Data to Clock (Figure 4) Removal Time MR to Clock (Figure 3) Set-up Time PE to CP (Figure 4) tSU tH to +125oC +25oC VCC = 4.5V -55oC Hold Time PE to CP or CE (Figure 4) to +125oC +25oC VCC = 4.5V -55oC tSU to +125oC +25oC VCC = 4.5V -55oC tREM to +125oC +25oC VCC = 4.5V -55oC tH to +125oC +25oC VCC = 4.5V -55oC Set-up Time Data and CE to Clock, (Figure 3, 4) to +125oC +25oC VCC = 4.5V -55oC Clock Pulse Width (Figure 1) -55oC +25oC VCC = 4.5V -55oC MR Pulse Width (Figure 2) -55oC to +125oC +25oC VCC = 4.5V -55oC to +125oC NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Spec Number 253 518758 Specifications HCS166MS TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL TEMPERATURE MIN MAX UNITS Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.75 mA Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V +25oC 4.0 - mA Output Current (Source) IOH VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V +25oC -4.0 - mA Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50µA +25oC - 0.1 V Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOH = -50µA +25oC VCC -0.1 - V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - ±5 µA Noise Immunity Functional Test FN VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) +25oC - - - CP or CE to Q7 TPHL VCC = 4.5V +25oC 2 37 ns TPLH VCC = 4.5V +25oC 2 37 ns TPHL VCC = 4.5V +25oC 2 36 ns MR to Q7 NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP DELTA LIMIT ICC 5 12µA IOL/IOH 5 -15% of 0 Hour PARAMETER Spec Number 254 518758 Specifications HCS166MS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test III (Postburn-In) 100%/5004 1, 7, 9 PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Group D READ AND RECORD ICC, IOL/H Subgroups 1, 2, 3, 9, 10, 11, (Note 2) NOTES: 1. Alternate Group A testing in accordance with Method 5005 of Mil-Std-883 may be exercised. 2. Table 5 parameters only. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1) Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V 50kHz 25kHz 1 - 12, 14 - 15 - 16 - - 8 - 1 - 7, 9 - 12, 14 - 16 - - 2, 4, 6, 8, 10, 12 13 3, 5, 9, 11, 14 - 16 7 1 OPEN STATIC I BURN-IN (Note 1) 13 STATIC II BURN-IN (Note 1) 13 DYNAMIC BURN-IN (Note 2) NOTES: 1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V ± 0.5V 13 8 1 - 7, 9 - 12, 14 - 16 NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Spec Number 255 518758 HCS166MS Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Delta Calculation (T0-T1) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Interim Electrical Test 3 (T3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% PIND, Method 2020, Condition A 100% Final Electrical Test 100% External Visual 100% Fine/Gross Leak, Method 1014 100% Serialization 100% Radiographic, Method 2012 (Note 3) 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 256 518758 HCS166MS AC Timing Diagrams and AC Load Circuit tr tf t/f MAX VS INPUT LEVEL VS 50 INPUT LEVEL MR VS GND tW VS tREM INPUT LEVEL GND tW tPHL VS tPLH CP GND tPHL VS VS Q7 VS tTHL tTLH FIGURE 1. CLOCK PRE-REQUISITE TIMES AND PROPAGATION AND OUTPUT TRANSITION TIMES VALID DATA FIGURE 2. MASTER RESIT PRE-REQUISITE TIMES AND PROPAGATION DELAYS. INPUT LEVEL VALID INPUT LEVEL PE OR CE VS VS GND GND tSU tSU tH tH INPUT LEVEL INPUT LEVEL VS VS CP GND GND FIGURE 3. DATA PRE-REQUISITE TIMES FIGURE 4. PARALLEL ENABLE OR CLOCK ENABLE PREREQUISITE TIMES AC VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V DUT TEST POINT CL RL CL = 50pF RL = 500Ω FIGURE 5. AC LOAD CIRCUIT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 257 518758 HCS166MS Die Characteristics DIE DIMENSIONS: 94 x 94 mils METALLIZATION: Type: AlSi Metal Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: 100µm x 100µm 4 mils x 4 mils Metallization Mask Layout HCS166MS D1 (3) D0 (2) DS (1) VCC (16) PE (15) D2 (4) (14) D7 D3 (5) (13) Q7 CE (6) (12) D6 (7) CP (8) GND (9) MR (10) D4 (11) D5 NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS166 is TA14386A. Spec Number 258 518758