IGNS EW DES N R O F N DED EM ENT COMME R E PL AC D E N OT R E D N ter at E OMM Sheet port Cen /tsc November 19, 2004 p u S l NO REC Data a m nic tersil.co our Tech contact ERSIL or www.in T 1-888-IN Low Resistance, Single 8-Channel, CMOS Analog Multiplexer The Hl-1818A is a monolithic, high performance CMOS analog multiplexer offering built-in channel selection decoding plus an inhibit (enable) input for disabling all channels. Dielectric Isolation (Dl) processing is used for enhanced reliability and performance. Substrate leakage and parasitic capacitance are much lower, resulting in extremely low static errors and high throughput rates. Low output leakage (typically 0.1nA) and low channel ON resistance (250) assure optimum performance in low level or current mode applications. The HI-1818A is a single-ended, 8-Channel multiplexer, and is ideally suited for medical instrumentation, telemetry systems, and microprocessor based data acquisition systems. HI-1818A FN3141.4 Features • Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V • “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 • Input Leakage (Max) . . . . . . . . . . . . . . . . . . . . . . . . .50nA • Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns • Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . .5mW • DTL/TTL Compatible Address • Operation . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Applications • Data Acquisition Systems • Precision Instrumentation • Demultiplexing • Selector Switch Ordering Information PART NUMBER HI1-1818A-2 TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld CERDIP PKG. DWG. # F16.3 Pinout HI-1818A (CERDIP) TOP VIEW ADDRESS A1 1 1 16 ADDRESS A0 +5V SUPPLY 2 15 -VSUPPLY ENABLE 3 14 +VSUPPLY ADDRESS A2 4 13 IN 1 IN 8 5 12 OUT IN 7 6 11 IN 2 IN 6 7 10 IN 3 IN 5 8 9 IN 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved HI-1818A Truth Table HI-1818A TRUTH TABLE HI-1818A TRUTH TABLE ADDRESS A2 A1 A0 L L L L L H L H L L H H H L L ADDRESS EN A1 A0 EN “ON” CHANNEL H L H L 6 H H L L 7 3 H H H L 8 4 X X X H None “ON” CHANNEL A2 L 1 L 2 L L L 5 Functional Block Diagram HI-1818A DIGITAL ADDRESS A0 A1 ENABLE A2 ADDRESS INPUT BUFFERS ENABLE BUFFER MULTIPLEX SWITCHES N IN 1 P DECODERS OUT IN 8 N P Schematic Diagrams ADDRESS INPUT BUFFER P3 P5 P1 V+ N1 P4 VCC A D1 200 All N-Channel Bodies to VAll P-Channel Bodies to V+ Unless Otherwise Specified P6 P7 P8 P9 P10 N6 N7 N8 N9 N10 D2 ADDRESS INPUT V- P2 N4 A N2 N5 N3 V- 2 FN3141.4 November 19, 2004 HI-1818A Schematic Diagrams ADDRESS DECODER V+ EN P11 A2 OR A2 P12 A1 OR A1 All N-Channel Bodies to VAll P-Channel Bodies to V+ TO P-CHANNEL SWITCH P13 A0 OR A0 P15 P14 P16 TO N-CHANNEL SWITCH N11 N12 N15 N14 N13 V- N16 IN SWITCH CELL MULTIPLEXER SWITCH FROM DECODE N18 V+ All N-Channel Bodies to VAll P-Channel Bodies to V+ Unless Otherwise Specified IN N17 OUT N19 V+ P17 P18 FROM DECODE 3 FN3141.4 November 19, 2004 HI-1818A Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . (V-) to (V+) Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 20 Maximum Junction Temperature Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. Electrical Specifications Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Access Time, tA Note 4 25 - 350 500 ns Full - - 1000 ns Break-Before-Make Delay, tOPEN 25 - 25 - ns Enable Delay (ON), tON(EN) 25 - 300 500 ns Enable Delay (OFF), tOFF(EN) Settling Time To 0.1% Full - - 1000 ns 25 - 300 500 ns Full - - 1000 ns 25 - 1.08 - s 25 - 2.8 - s Channel Input Capacitance, CS(OFF) 25 - 4 - pF Channel Output Capacitance, CD(OFF) 25 - 20 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.6 - pF Digital Input Capacitance, CA 25 - 5 - pF Full - - 0.4 V To 0.025% DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH Note 3 Input Leakage Current, IA Full 4.0 - - V Full - - 1 A Full -15 - +15 V 25 - 250 400 Full - - 500 ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VlN ON Resistance, rON Note 2 OFF Input Leakage Current, IS(OFF) Full - - 50 nA ON Channel Leakage Current, lD(ON) Full - - 250 nA OFF Output Leakage Current, ID(OFF) Full - - 250 nA 4 FN3141.4 November 19, 2004 HI-1818A Electrical Specifications Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Full - - 27.5 mW Current, I+ Full - - 0.5 mA Current, I- Full - - 1 mA Current, IL Full - - 1 mA NOTES: 2. VOUT = 10V, IOUT = 1mA. 3. To drive from DTL/TTL circuits, 1k pull-up resistors to 5.0V supply are recommended. 4. Time measured to 90% of final output level; VOUT = -5.0V to 5.0V, Digital Inputs = 0V to 4.0V. Test Circuits and Waveforms +15V -15V +5V A2 V+ VAH = 4.0V 50% ENABLE DRIVE (VA) VAL = 0V tON (EN) VA 10% ENABLE DRIVE 2V/DIV. VL A1 IN 1 HI-1818A A0 IN 2-8 EN OUTPUT 90% V- +5V ENABLED (S1 ON) OUT 50 200 12.5 pF DISABLED OUTPUT 2V/DIV. tOFF (EN) 100ns/DIV. FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1C. WAVEFORMS FIGURE 1. ENABLE DELAYS +15V -15V +5V A2 V+ 4.0V 50% OUTPUT +5V IN 2 S1 ON EN S2 ON IN 3-8 A0 VA 50% VA INPUT 2V/DIV. VL IN 1 A1 HI-1818A ADDRESS DRIVE (VA) 0V V- 50 OUT 200 12.5 pF OUTPUT 1V/DIV. tOPEN 100ns/DIV. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2C. WAVEFORMS FIGURE 2. BREAK-BEFORE-MAKE DELAY 5 FN3141.4 November 19, 2004 HI-1818A 1mA V2 IN OUT VIN V2 RON = A 1mA 350 60 SWITCH CURRENT (mA) 300 125oC ON RESISTANCE () OUT V 250 25oC 200 -55oC 150 -55oC 40 125oC 20 25oC 0 -20 125oC -40 100 -10 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE OFF LEAKAGE EN 4V OUT 10V -10 -8 -6 10V 8 10 ACCESS TIME TEST CIRCUIT OUT A ID(ON) EN A1 -4 -2 0 2 4 6 VOLTAGE ACROSS SWITCH (V) FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE +5V A0 25oC -55oC ON LEAKAGE A ID(OFF) 10V -60 IN 1 IN 2 -5V IN 3-8 OUT 10 k HI-1818A 10V 50pF A0 A1 A2 EN 0.4V NOTE: OUT EN A 10V 50 0V TO 4V Two measurements per channel: 10V and 10V IS(OFF) 4V Two measurements per device for ID(OFF): 10V and 10V 10V 100nA 4V 10nA A0 INPUT 50% ID(ON) - ID(OFF) 2V/DIV. HI-1818A 1nA +5V IS(OFF) HI-1818A 100pA OUTPUT 5V/DIV. -5V 10% 10pA 25 50 75 TEMPERATURE (oC) 100 125 FIGURE 5. LEAKAGE CURRENTS vs TEMPERATURE 6 tA 100ns/DIV. FIGURE 6. ACCESS TIME FN3141.4 November 19, 2004 HI-1818A Die Characteristics METALLIZATION: PASSIVATION: Type: CuAl Thickness: 16kÅ 2kÅ Type: Nitride/Silox Thickness: Silox: 12kÅ 2kÅ, Nitride: 3.5kÅ 1kÅ WORST CASE CURRENT DENSITY: 1.43 x 105 A/cm2 at 25mA Metallization Mask Layout HI-1818A VL A1 A0 -VSUPPLY EN +VSUPPLY A2 IN 1 OUTPUT IN 8 IN 7 IN 6 IN 5 7 IN 4 IN 3 IN 2 FN3141.4 November 19, 2004 HI-1818A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL (c) E M -Bbbb S C A-B S Q -C- SEATING PLANE S1 b2 b ccc M C A-B S eA/2 - 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 c aaa M C A - B S D S D S NOTES 0.014 eA e MAX b A A MIN A A L MILLIMETERS MAX M (b) D BASE PLANE MIN b1 SECTION A-A D S INCHES SYMBOL NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 16 5. This dimension allows for off-center lid, meniscus, and glass overrun. 16 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN3141.4 November 19, 2004