ESIGNS R NEW D NT O F D E D N ME COMME EPL ACE NO T RE NDE D R E nter at e M C M t r O uppo S l NO REC a ic m/tsc n o our Tech r www.intersil.c contact Data o Sheet October 10, 2008 TERSIL 1-888-IN HSP43220 FN2486.10 Decimating Digital Filter Features The HSP43220 Decimating Digital Filter is a linear phase low pass decimation filter which is optimized for filtering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220 offers a single chip solution to signal processing applications which have historically required several boards of ICs. This reduction in component count results in faster development times as well as reduction of hardware costs. • Single Chip Narrow Band Filter with up to 96dB Attenuation The HSP43220 is implemented as a two stage filter structure. As seen in the block diagram, the first stage is a high order decimation filter (HDF) which utilizes an efficient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass filtering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a finite impulse response (FIR) decimation filter structured as a transversal FIR filter with up to 512 symmetric taps which can implement filters with sharp transition regions. The FIR can perform further decimation by up to 16 if required while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384. The HSP43220 accepts 16-bit parallel data in 2’s complement format at sampling rates up to 33MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220 also provides the capability to bypass either the HDF or the FIR for additional flexibility. • DC to 33MHz Clock Rate • 16-Bit 2’s Complement Input • 20-Bit Coefficients in FIR • 24-Bit Extended Precision Output • Programmable Decimation up to a Maximum of 16,384 • Standard 16-Bit Microprocessor Interface • Filter Design Software Available DECIMATE™ • Up to 512 Taps • Pb-Free Available (RoHS compliant) Applications • Very Narrow Band Filters • Zoom Spectral Analysis • Channelized Receivers • Large Sample Rate Converter Ordering Information PART NUMBER HSP43220JC-25 PART MARKING HSP43220JC-25 TEMP. RANGE (°C) PACKAGE PKG. DWG. # 0 to +70 84 Ld PLCC N84.1.15 HSP43220JC-25Z HSP43220JC-25Z 0 to +70 84 Ld PLCC N84.1.15 (Pb-free) HSP43220JC-33 0 to +70 84 Ld PLCC N84.1.15 0 to +70 84 Ld PLCC N84.1.15 (Pb-free) HSP43220JC-33 HSP43220JC-33Z HSP43220JC-33Z NOTE: These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. NOTE: DECIMATE Software Development Tool (This software tool may be downloaded from our internet site: www.intersil.com 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2000, 2004, 2008. All Rights Reserved DECIMATE™ is a trademark of Intersil Corporation. All other trademarks mentioned are the property of their respective owners. HSP43220 Block Diagram INPUT CLOCK DATA INPUT CONTROL AND COEFFICIENTS DECIMATION UP TO 1024 DECIMATION UP TO 16 HIGH ORDER DECIMATION FILTER FIR DECIMATION FILTER 16 16 24 DATA OUT DATA READY FIR CLOCK Pinout GND DATA_IN 0 DATA_IN 1 DATA_IN 2 DATA_IN 3 DATA_IN 4 DATA_IN 5 DATA_IN 6 DATA_IN 7 DATA_IN 8 DATA_IN 9 DATA_IN 10 DATA_IN 11 DATA_IN 12 DATA_IN 13 DATA_IN 14 DATA_IN 15 VCC GND CK_IN VCC HSP43220 84 PLASTIC LEADED CHIP CARRIER (PLCC) TOP VIEW 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 STARTOUT VCC STARTIN ASTARTIN RESET A1 A0 WR CS C_BUS 15 C_BUS 14 C_BUS 13 C_BUS 12 C_BUS 11 C_BUS 10 C_BUS 9 VCC GND C_BUS 8 C_BUS 7 C_BUS 6 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 GND DATA_OUT 0 DATA_OUT 1 DATA_OUT 2 DATA_OUT 3 DATA_OUT 4 DATA_OUT 5 DATA_OUT 6 DATA_OUT 7 DATA_OUT 8 DATA_OUT 9 DATA_OUT 10 DATA_OUT 11 GND VCC DATA_OUT 12 DATA_OUT 13 DATA_OUT 14 DATA_OUT 15 DATA_OUT 16 DATA_OUT 17 C_BUS 5 C_BUS 4 C_BUS 3 C_BUS 2 C_BUS 1 C_BUS 0 OUT_SELH OUT_ENP OUT_ENX VCC GND FIR_CK VCC GND DATA_RDY DATA_OUT 23 DATA_OUT 22 DATA_OUT 21 DATA_OUT 20 DATA_OUT 19 DATA_OUT 18 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin Description NAME TYPE DESCRIPTION VCC The +5V power supply pins. GND The device ground. CK_IN I Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN can be divided down from FIR_CK. CK_IN is a CMOS level signal. FIR_CK I Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal. 2 FN2486.10 October 10, 2008 HSP43220 Pin Description (Continued) NAME TYPE DESCRIPTION DATA_IN0-15 I Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchronous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit 15 is the MSB. C_BUS0-15 I Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0 and A1 DATA_OUT 0-23 O Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of the output, DATA_OUT16-23 will provide extension or growth bits depending on the state of OUT_SELH and whether the FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not bypassed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode. DATA_RDY O An active high output strobe that is synchronous with FIR_CK that indicates that the result of the just completed FIR cycle is available on the data bus. RESET I RESET is an asynchronous signal which requires that the input clocks CK_IN and FIR_CK are active when RESET is asserted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR filter data path is not initialized. The control register bits that are cleared are F_BYP, H_STAGES, and H_DRATE. The F_DIS bit is set. In order to guarantee consistent operation of the part, the user must reset the DDF after power-up. WR I Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of WR will latch the C_BUS0-15 data into the register specified by A0 and A1. CS I Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low, the A0 and A1 address lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate register as specified by A0 and A1. A0, A1 I Control Register Address. These lines are decoded to determine which control register is the destination for the data on C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs. ASTARTIN I ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT. STARTOUT O STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of CK_IN. STARTIN I STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's. OUT_SELH I Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from the accumulator output. Processing is not interrupted by this pin. OUT_ENP I Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin. OUT_ENX I Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin. The HDF Data Shifter The first filter section is called the High Order Decimation Filter (HDF) and is optimized to perform decimation by large factors. It implements a low pass filter using only adders and delay elements instead of a large number of multiplier/ accumulators that would be required using a standard FIR filter. After being latched into the Input Register the data enters the Data Shifter. The data is positioned at the output of the shifter to prevent errors due to overflow occurring at the output of the HDF. The number of bits to shift is controlled by H_GROWTH. The HDF is divided into 4 sections: the HDF filter section, the clock divider, the control register logic and the start logic (Figure 1). 3 FN2486.10 October 10, 2008 HSP43220 control bus and is called H_STAGES. H_STAGES is decoded to provide the enables for each integrator stage. When a given integrator stage is selected, the feedback path is enabled and the integrator accumulates the current data sample with the previous sum. The integrator section can be put in bypass mode by the H_BYP bit. When H_BYP or RESET is asserted, the feedback paths in all integrator stages are cleared. Integrator Section The data from the shifter goes to the Integrator section. This is a cascade of 5 integrator (or accumulator) stages, which implement a low pass filter. Each accumulator is implemented as an adder followed by a register in the feed forward path. The integrator is clocked by the sample clock, CK_IN as shown in Figure 2. The bit width of each integrator stage goes from 66 bits at the first integrator down to 26 bits at the output of the fifth integrator. Bit truncation is performed at each integrator stage because the data in the integrator stages is being accumulated and thus is growing, therefore the lower bits become insignificant, and can be truncated without losing significant data. Decimation Register The output of the Integrator section is latched into the Decimation Register by CK_DEC. The output of the Decimation register is cleared when RESET is asserted. The HDF decimation rate = H_DRATE +1, which is defined as HDEC for convenience. There are three signals that control the integrator section; they are H_STAGES, H_BYP and RESET. In Figure 2 these control signals have been decoded and are labelled INT_EN1 - INT_EN5. The order of the filter is loaded via the A0-1 WR CS C_BUS CK_IN RESET CK_IN ASTARTIN RESET STARTIN H_DRATE CONTROL REGISTER LOGIC 6 5 H_GROWTH ISTART CLOCK DIVIDER H_BYP STARTOUT START LOGIC 5 CK DEC COMB_EN1-5 INT_EN1-5 HDF FILTER SECTION ISTART H_GROWTH INT_EN1-5 6 DATA IN 16 INPUT REG 16 RESET COMB_EN1-5 DATA SHIFTER 66 RESET 5 5 INTEGRATOR TO FIR DEC REG 26 26 COMB FILTER ROUND 19 16 REG CK_IN 16 TO FIR CK_DEC FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE 0 FROM SHIFTER 66 CK 0 0 0 0 MUX MUX MUX MUX MUX INT_EN5 INT_EN4 INT_EN3 INT_EN2 INT_EN1 REG 63 REG 53 REG 43 REG 35 REG TO DECIMATION REGISTER 26 IN FIGURE 2. INTEGRATOR 4 FN2486.10 October 10, 2008 HSP43220 COMB_EN5 FROM DECIMATION REGISTER RESET 26 REG B A-B 22 A COMB_EN4 COMB_EN3 COMB_EN2 COMB_EN1 RESET RESET RESET RESET REG B A-B 21 A REG 19 B A-B 20 A REG B A-B 19 A REG TO ROUNDER B A-B A CK_DEC FIGURE 3. COMB FILTER Comb Filter Section The output of the Decimation Register is passed to the Comb Filter Section. The Comb section consists of 5 cascaded Comb filters or differentiators. Each Comb filter section calculates the difference between the current and previous integrator output. Each Comb filter consists of a register which is clocked by CK_DEC, followed by an subtractor, where the subtractor calculates the difference between the input and output of the register. Bit truncations are done at each stage as shown in Figure 3. The first stage bit width is 26 bits and the output of the fifth stage is 19 bits. There are three signals that control the Comb Filter; H_STAGES, H_BYP and RESET. In Figure 3 these control signals are decoded as COMB_EN1 - COMB_EN5. The order of the Comb filter is controlled by H_STAGES, which is programmed over the control bus. H_BYP is used to put the comb section in bypass mode. RESET causes the register output in each Comb stage to be cleared. The H_ BYP and RESET control pins, when asserted force the output of all registers to zero so data is passed through the subtractor unaltered. When the H_STAGES control bits enable a given stage the output of the register is subtracted from the input. It is important to note that the Comb filter section has a speed limitation. The Input sampling rate divided by the decimation factor in the HDF (CK_IN/HDEC) should not exceed 4MHz. Violating this condition causes the output of the filter to be incorrect. When the HDF is put in bypass mode this limitation does not apply. Equation 2 describes the relationship between F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK. filter stage in the HDF section has a 16-bit integer portion with a 3-bit fractional part in 2's complement format. The rounding algorithm is as follows: POSITIVE NUMBERS Fractional Portion to 0.5 Fractional Portion < 0.5 Round-Up Truncate NEGATIVE NUMBERS Fractional Portion 0.5 Round-Up Fractional Portion > 0.5 Truncate The output of the rounder is latched into the HDF output register with CK_DEC. CK_DEC is generated by the Clock Divider section. The output of the register is cleared when RESET is asserted. Clock Divider and Control Logic The clock divider divides CK_IN by the decimation factor HDEC to produce CK_DEC. CK_DEC clocks the Decimation Register, Comb Filter section, HDF output register. In the FIR filter CK_DEC is used to indicate that a new data sample is available for processing. The clock generator is cleared by RESET and is not enabled until the DDF is started by an internal start signal (see “Start Logic” on page 9). The Control Register Logic enables the updating of the Control registers which contain all of the filter parameter data. When WR and CS are asserted, the control register addressed by bits A0 and A1 is loaded with the data on the C_BUS. Rounder The filter accuracy is limited by the 16-bit data input. To maintain the maximum accuracy, the output of the comb is rounded to 16 bits. The Rounder performs a symmetric round of the 19-bit output of the last Comb stage. Symmetric rounding is done to prevent the synthesis of a 0Hz spectral component by the rounding process and thus causing a reduction in spurious free dynamic range. Saturation logic is also provided to prevent roll over from the largest positive value to the most negative value after rounding. The output of the last comb 5 FN2486.10 October 10, 2008 HSP43220 DDF Control Registers F_Register (A1 = 0, A0 = 0) F_OAD F_BYP F_ESYM FA0 FB0 ES0 15 14 13 F_DRATE F_TAPS D3 D2 D1 D0 T8 12 11 10 9 8 T7 T6 7 6 T5 T4 T3 T2 T1 T0 5 4 3 2 1 0 F_TAPS Bits T0-T8 are used to specify the number of FIR filter taps. The number entered is one less than the number of taps required. For example, to specify a 511 tap filter F_TAPS would be programmed to 510. The minimum number of FIR taps = 3 (F_TAPS = 2). F_DRATE Bits D0-D3 are used to specify the amount of FIR decimation. The number entered is one less than the decimation required. For example, to specify decimation of 16, F_DRATE would be programmed to 15. For no FIR decimation, F_DRATE would be set equal to 0. FDRATE +1 is defined as FDEC. F_ESYM Bit ES0 is used to select the FIR symmetry. F_ESYM is set equal to one to select even symmetry and set equal to zero to select odd symmetry. When F_ESYM is one, data is added in the pre-adder; when it is zero, data is subtracted. Normally set to one. F_BYP FB0 is used to select FIR bypass mode. FIR bypass mode is selected by setting F_BYP = 1. When FIR bypass mode is selected, the FIR is internally set up for a 3 tap even symmetric filter, no decimation (F_DRATE = 0) and F_OAD is set equal to one to zero one side of the preadder. In FIR bypass mode all FIR filter parameters, except F_CLA, are ignored, including the contents of the FIR coefficient RAM. In FIR bypass mode the output data is brought output on the lower 16 bits of the output bus DATA_OUT 0-15. To disable FIR bypass mode, F_BYP is set equal to zero. When F_BYP is returned to zero, the coefficients must be reloaded. F_OAD Bit FA0 is used to select the zero the preadder mode. This mode zeros one of the inputs to the pre-adder. Zero preadder mode is selected by setting F_OAD equal to one. This feature is useful when implementing arbitrary phase filters or can be used to verify the filter coefficients. To disable the Zero Preadder mode F_OAD is set equal to zero. FIGURE 4. 6 FN2486.10 October 10, 2008 HSP43220 DDF Control Registers (Continued) FC_Register (A1 = 0, A0 = 1) F_CF C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 X X X X X X X X X X X X C3 C2 C1 C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F_CF Bits C0-C19 represent the coefficient data, where C19 is the MSB. Two writes are required to write each coefficient which is 2's complement fractional format. The first write loads C19 through C4; C3 through C0 are loaded on the second write cycle. As the coefficients are written into this register they are formatted into a 20-bit coefficient and written into the Coefficient RAM sequentially starting with address location zero. The coefficients must be loaded sequentially, with the center tap being the last coefficient to be loaded. See “Coefficient RAM” on page 10. FIGURE 5. 7 FN2486.10 October 10, 2008 HSP43220 DDF Control Registers (Continued) H_Register 1 (A1 = 1, A0 = 0) RESERVED 15 14 13 F_DIS F_CLA H_BYP H_DRATE FD0 FC0 HB0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 12 11 10 9 8 7 6 5 4 3 2 1 0 H_DRATE Bits R0-R9 are used to select the amount of decimation in the HDF. The amount of decimation selected is programmed as the required decimation minus one; for instance to select decimation of 1024 H_DRATE is set equal to 1023. HDRATE +1 is defined as HDEC. H_BYP Bit HB0 is used to select HDF bypass mode. This mode is selected by setting H_BYP = 1. When this mode is selected the input data passes through the HDF unfiltered. Internally H_STAGES and H_DRATE are both set to zero and H_GROWTH is set to 50. H_REGISTER 2 must be reloaded when H_BYP is returned to 0. To disable HDF bypass mode H_BYP = 0. The relationship between CK_IN and FIR_CK in this and all other modes is defined by Equation 2. F_CLA Bit FC0 is used to select the clear accumulator mode in the FIR. This mode is enabled by setting F_CLA = 1 and is disabled by setting F_CLA = 0. In normal operation this bit should be set equal to zero. This mode zeros the feedback path in the accumulator of the multiplier/accumulator (MAC). It also allows the multiplier output to be clocked off the chip by FIR_CK, thus DATA_RDY has no meaning in this mode. This mode can be used in conjunction with the F_OAD bit to read out the FIR coefficients from the coefficient RAM. F_DIS Bit FD0 is used to select the FIR disable mode. This feature enables the FIR parameters to be changed. This feature is selected by setting F_DIS = 1. This mode terminates the current FIR cycle. While this feature is selected, the HDF continues to process data and write it into the FIR data RAM. When the FIR re-programming is completed, the FIR can be re-enabled either by clearing F_DIS, or by asserting one of the start inputs, which automatically clears F_DIS. FIGURE 6. 8 FN2486.10 October 10, 2008 HSP43220 DDF Control Registers (Continued) H_Register 2 (A1 = 1, A0 = 1) RESERVED H_GROWTH H_STAGES G5 G4 G3 G2 G1 G0 N2 N1 N0 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 H_STAGES Bits N0-N2 are used to select the number of stages or order of the HDF filter. The number that is programmed in is equal to the required number of stages. For a 5th order filter, H_STAGES would be set equal to 5. H_GROWTH Bits G0-G5 are used to select the proper amount of growth bits. H_GROWTH is calculated using Equation 1: H_GROWTH = 50 – CEILING H_STAGESx log H DEC /log(2) (EQ. 1) where the CEILING { } means use the next largest integer of the result of the value in brackets and log is the log to the base 10. The value of H_GROWTH represents the position of the LSB on the output of the data shifter. FIGURE 7. Start Logic The Start Logic generates a start signal that is used internally to synchronously start the DDF. If ASTARTIN is asserted (STARTIN must be tied high) the Start Logic synchronizes it to CK_IN by double latching the signal and generating the signal STARTOUT, which is shown in Figure 8. The STARTOUT signal is then used to synchronously start other DDFs in a multi-chip configuration (the STARTOUT signal of the first DDF would be tied to the STARTIN of the second DDF). The NAND gate shown in Figure 8 then passes this synchronized signal to be used on-chip to provide a synchronous start. Once started, the chip requires a RESET to halt operation. RESET STARTIN ASTARTIN S D S Q D Q CK_IN ISTART STARTOUT FIGURE 8. START LOGIC When STARTIN is asserted (ASTARTIN must be tied high) the NAND gate passes STARTIN which is used to provide the internal start, ISTART, for the DDF. When RESET is asserted the internal start signal is held inactive, thus it is necessary to 9 assert either ASTARTIN or STARTIN in order to start the DDF. The timing of the first valid DATA_IN with respect to START_IN is shown in the Timing Waveforms. In using ASTARTIN or STARTIN a high to low transition must be detected by the rising edge of CK_IN, therefore these signals must have been high for more than one CK_IN cycle and then taken low. The FIR Section The second filter in the top level block diagram is a Finite Impulse Response (FIR) filter which performs the final shaping of the signal spectrum and suppresses the aliasing components in the transition band of the HDF. This enables the DDF to implement filters with narrow pass bands and sharp transition bands. The FIR is implemented in a transversal structure using a single multiplier/accumulator (MAC) and RAM for storage of the data and filter coefficients as shown in Figure 9. The FIR can implement up to 512 symmetric taps and decimation up to 16. The FIR is divided into 2 sections: the FIR filter section and the FIR control logic. FN2486.10 October 10, 2008 HSP43220 Coefficient RAM The Coefficient RAM stores the coefficients for the current FIR filter being implemented. The coefficients are loaded into the Coefficient RAM over the control bus (C_BUS). The coefficients are written into the Coefficient RAM sequentially, starting at location zero. It is only necessary to write one half of the coefficients when symmetric filters are being implemented, where the last coefficient to be written in is the center tap. The coefficients are loaded into address 01 in two writes. The first write loads the upper 16 bits of the 20-bit coefficient, C4 through C19. The second write loads the lower 4 bits of the coefficient, C0 through C3, where C19 is the MSB. The two 16-bit writes are then formatted into the 20-bit coefficient that is then loaded into the Coefficient RAM starting at RAM address location zero, where the coefficient at this location is the outer tap (or the first coefficient value). To reload coefficients, the Coefficient RAM Address pointer must be reset to location zero so that the coefficients will be loaded in the order the FIR filter expects. There are two methods that can be used to reset the Coefficient RAM address pointer. The first is to assert RESET, which automatically resets the pointer, but also clears the HDF and alters some of the control register bits. (RESET does not change any of the coefficient values.) The second method is to set the F_DIS bit in control register H_ REGISTER1. This control bit allows any of the FIR control register bits to be reprogrammed, but does not automatically modify any control registers. When the programming is completed, the FIR is re-started by clearing the F_DIS bit or by asserting one of the start inputs (ASTARTIN or STARTIN). The F_DIS bit allows the filter parameters to be changed more quickly and is thus the recommended reprogramming method. Data RAM The Data RAM stores the data needed for the filter calculation. The format of the data is: 20.2-12-22-32-42-52-62-72-82-92-102-112-122-132-142-15 where the sign bit is in the 20 location. The 16-bit output of the HDF Output Register is written into the Data Ram on the rising edge of CK_DEC. RESET initializes the write pointer to the data RAM. After a RESET occurs, the output of the FIR will not be valid until the number of new data samples written to the Data RAM equals TAPS. The filter always operates on the most current sample and the taps-1 previous samples. Thus if the F_DIS bit is set, data continues to be written into the data RAM coming from the HDF section. When the FIR is enabled again the filter will be operating on the most current data samples and thus another transient response will not occur. The maximum throughput of the FIR filter is limited by the use of a single Multiplier/Accumulator (MAC). The data output from the HDF being clocked into the FIR filter by CK_DEC must not be at a rate that causes an erroneous result being calculated because data is being overwritten. Equation 2 describes the relationship between, FIR_CK, CK_DEC, the number of taps that can be implemented in the FIR, the decimation rate in the HDF and the decimation rate in the FIR. (In the Design Considerations section of the “Operational Section” on page 12 there is a chart that shows the tradeoffs between these parameters.) CK_IN TAPS/2 + 4 + F DEC FIR_CK ---------------------------------------------------------------------------------H DEC F DEC (EQ. 2) This equation expresses the minimum FIR_CK. The minimum FIR_CK is the smallest integer multiple of CK_IN that satisfies Equation 1. In addition, the TSK specification must be met (see AC Electrical Specifications). FDEC is the decimation rate in the FIR (FDEC = F_DRATE +1), where TAPS = the number of taps in the FIR for even length filters and equals the number of taps+1 for odd length filters. Solving Equation 3 for the maximum number of taps: FIR_CK H DEC F DEC TAPS = 2 ---------------------------------------------------------- – F DEC -4 CK_IN (EQ. 3) In using this equation, it must be kept in mind that CK_IN/ HDEC must be less than or equal to 4MHz (unless the HDF is in bypass mode in which case this limitation in the HDF does not apply). In the “Operational Section” on page 12 under the Design Considerations, there is a table that shows the trade-offs of these parameters. In addition, Intersil provides a software package called DECI MATE™ which designs the DDF filter from System specifications. The registered outputs of the data RAM are added or subtracted in the 17-bit pre-adder. The F_OAD control bit allows zeros to be input into one side of the pre-adder. This provides the capability to implement non-symmetric filters. The selection of adding the register outputs for an even symmetric filter or for subtracting the register outputs for odd symmetric filter is provided by the control bit F_ESYM, which is programmed over the control bus. When subtraction is selected, the new data is subtracted from the old data. The 17-bit output of the adder forms one input of the multiplier/accumulator. A control bit F_CLA provides the capability to clear the feedback path in the accumulator such that multiplier output will not be accumulated, but will instead flow directly to the output register. The bit weightings of the data and coefficients as they are processed in the FIR is shown as follows. Input Data (from HDF) 20.2-1 . . . 2-15 Pre-adder Output 2120.2-1 . . . 2-15 Coefficient 20.2-1 . . . 2-19 Accumulator 28 . . . 20 .21 . . . 2-34 10 FN2486.10 October 10, 2008 HSP43220 control the first multiplexer that selects the upper 8 bits of the output bus, DATA_OUT16-23. F_BYP controls the second multiplexer that selects the lower 16 bits of the output bus, DATA_OUT0-15. The output formatter is shown in detail in Figure 10. FIR Output The 40 most significant bits of the accumulator are latched into the output register. The lower 3 bits are not brought to the output. The 40 bits out of the output register are selected to be output by a pair of multiplexers. This register is clocked by FIR_CK (see Figure 9). FIR Control Logic There are two multiplexers that route 24 of the 40 output bits from the output register to the output pins. The first multiplexer selects the output register bits that will be routed to output pins DATA_OUT16-23 and the second multiplexer selects the output register bits that will be routed to output pins DATA_OUT0-15. The DATA_RDY strobe indicates that new data is available on the output of the FIR. The rising edge of DATA_RDY can be used to load the output data into an external register or RAM. Data Format The DDF maintains 16 bits of accuracy in both the HDF and FIR filter stages. The data formats and bit weightings are shown in Figure 11. The multiplexers are controlled by the control signal F_BYP and the OUT_SELH pin. F_BYP and OUT_SELH both PRE-ADDER LOGIC FROM HDF 16 REG 16 16 x 512 DATA RAM 16 PRE-ADDER F_OAD REG 16 REG 17 16 F_ESYM FROM COEFFICIENT FORMATTER 20 20 x 256 COEFFICIENT RAM REG 20 REG 20 17 17 17 x 20 BIT MULTIPLIER ARRAY MULTIPLIER/ ACCUMULATOR SECTION FROM CONTROL REGISTERS F_DRATE F_TAPS F_BYP 37 REG F_DIS 37 43 F_CLA 43-BIT ACCUMULATOR FIR CONTROL LOGIC 43 FIR_CK FIR_CK MUX REG DATA_RDY OUTPUT REG 40 F_CLA OUTPUT FORMATTER 24 DATA_RDY DATA_OUT 0 -23 FIGURE 9. FIR FILTER 11 FN2486.10 October 10, 2008 HSP43220 40 F_BYP = 0 OUT_SELH = 1 8 F_BYP 20 - 2-15 F_BYP = 0 8 28 - 21 2-16 - 2-23 F_BYP = 0 MUX MUX OUT_SELH = 0 OR F_BYP = 1 OUT_SELH 8 2-16 - 2-31 F_BYP = 1 16 16 F_BYP 16 OUT_ENX OUT_ENP DATA_OUT16-23 DATA_OUT0 -15 FIGURE 10. FIR OUTPUT FORMATTER INPUT DATA FORMAT Fractional Two's Complement Input 14 13 12 11 10 9 8 7 6 -20 . 2-1 15 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 5 4 3 2 1 0 2-10 2-11 2-12 2-13 2-14 2-15 FIR COEFFICIENT FORMAT Fractional Two's Complement Input 19 18 17 16 15 14 13 12 11 10 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 . 9 8 7 6 5 4 3 2-10 2-11 2-12 2-13 2-14 2-15 2 1 0 2-16 2-17 2-18 2-19 OUTPUT DATA FORMAT Fractional Two's Complement Output FOR: OUT_SELH = 1, F_BYP = 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 -28 27 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 5 4 3 2 1 0 . 5 4 3 2 1 0 2-10 2-11 2-12 2-13 2-14 2-15 FOR: OUT_SELH = 0, F_BYP = 0 15 14 13 12 11 10 9 8 7 6 -20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 15 14 2-10 2-11 2-12 2-13 2-14 2-15 23 22 21 20 19 18 17 16 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 FOR: OUT_SELH = X, F_BYP = 1 23 22 21 20 19 18 17 16 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 FIGURE 11. Operational Section Start Configurations The scenario to put the DDF into operational mode is: reset the DDF by asserting the RESET input, configure the DDF over the control bus, and apply a start signal, either by ASTARTIN or STARTIN. Until the DDF is put in operational mode with a start pulse, the DDF ignores all data inputs. To use the asynchronous start, an asynchronous active low pulse is applied to the ASTARTIN input. ASTARTIN is internally synchronized to the sample clock, CK_IN, and generates STARTOUT. This signal is also used internally 12 when the asynchronous mode is selected. It puts the DDF in operational mode and allows the DDF to begin accepting data. When the ASTARTIN input is being used, the STARTIN input must be tied high to ensure proper operation. To start the DDF synchronously, the STARTIN is asserted with a active low pulse that has been externally synchronized to CK_IN. Internally the DDF then uses this start pulse to put the DDF in operate mode and start accepting data inputs. When STARTIN is used to start the DDF the ASTARTIN input must be tied high to prevent false starts. FN2486.10 October 10, 2008 HSP43220 Multi-Chip Start Configurations Since there are two methods to start-up the DDF, there are also two configurations that can be used to start-up multiple chips. The first method is shown in Figure 12. The timing of the STARTOUT circuitry starts the second DDF on the same clock as the first. If more DDFs are also to be started synchronously, STARTOUT is connected to their STARTIN's. The second method to start-up DDFs in a multiple chip configuration is to use the synchronous start scenario. The STARTIN input is wired to all the chips in the chain, and is asserted by a active low synchronous pulse that has been externally synchronized to CK_IN. In this way all DDFs are synchronously started. The ASTARTIN input on all the chips is tied high to prevent false starts. The STARTOUT outputs are all left unconnected. This configuration is illustrated in Figure 13. TO OTHER DDF'S +5V STARTIN ASTARTIN +5V DDF ASTARTIN STARTIN STARTOUT CK_IN CK_IN FIR_CK FIR_CK STARTOUT NC STARTOUT NC DDF FIGURE 12. ASYNCHRONOUS START-UP +5V STARTIN +5V CK_IN ASTARTIN DDF STARTOUT CK_IN FIR_CK ASTARTIN STARTIN DDF FIR_CK FIGURE 13. SYNCHRONOUS START-UP Chip Set Application Design Trade-Off Considerations The HSP43220 is ideally suited for narrow band filtering in Communications, Instrumentation and Signal Processing applications. The HSP43220 provides a fully integrated solution to high order decimation filtering. Equation 2 in the Functional Description section expresses the relationship between the number of TAPS which can be implemented in the FIR as a function of CK_IN, FIR_CK, HDEC, FDEC. Table 1 provides a tradeoff of these parameters. For a given speed grade and the ratio of the clocks, and assuming minimum decimation in the HDF, the number of FIR taps that can be implemented is given in Equation 2. The combination of the HSP43220 and the HSP45116 (which is a NCOM Numerically Controlled Oscillator / Modulator) provides a complete solution to digital receivers. The diagram in Figure 14 illustrates this concept. The HSP45116 down converts the signal of interest to baseband, generating a real component and an imaginary component. A HSP43220 then performs low pass filtering and reduces the sampling rate of each of the signals. The system scenario for the use of the DDF involves a narrow band signal that has been over-sampled. The signal is over-sampled in order to capture a wide frequency band containing many narrow band signals. The NCOM is “tuned” to the frequency of the signal of interest and performs a complex down conversion to baseband of this signal, which results in a complex signal centered at baseband. A pair of DDFs then low pass filters the NCOM output, extracting the signal of interest. 13 FN2486.10 October 10, 2008 HSP43220 HSP45116 NCOM COS (WT) HSP43220 DDF SIN (WT) HSP43220 DDF SAMPLED INPUT DATA 0 10MHz 0 20MHz 0 FIGURE 14. DIGITAL CHANNELIZER TABLE 1. DESIGN TRADE OFF FOR MINIMUM HDEC SPEED GRADE (MHz) TAPS FIR_CK CK_IN MIN HDEC FDEC = 1 FDEC = 2 FDEC = 4 FDEC = 8 FDEC = 16 33 1 9 8 24 56 120 248 25.6 1 7 4 16 40 88 184 15 1 4 (Note) 4 16 40 88 33 2 5 10 28 64 136 280 25.6 2 4 6 20 48 104 216 15 2 2 (Note) 4 16 40 88 33 4 3 14 36 80 168 344 25.6 4 2 6 20 48 104 216 15 4 1 (Note) 4 16 40 88 33 8 2 22 52 112 232 472 25.6 8 1 6 20 48 104 216 15 8 1 6 20 48 104 216 NOTE: Filter not realizable. 14 FN2486.10 October 10, 2008 HSP43220 DECIMATE Intersil provides a development system which assists the design engineer to utilizing this filter. The DECIMATE software package provides the user with both filter design and simulation environments for filter evaluation and design. These tools are integrated within one standard DSP CAD environment, The Athena Group's Monarch Professional DSP Software package. The software package is designed specifically for the DDF. It provides all the filter design software for this proprietary architecture. It provides a user-friendly menu driven interface to allow the user to input system level filter requirements. It provides the frequency response curves and a data flow simulation of the specified filter design (Figure 15). It also creates all the information necessary to program the DDF, including a PROM file for programming the control registers. This software package runs on an IBM™ PC™, XT™, AT™, PS/2™ computer or 100% compatible with the following configuration: 640k RAM 5.25” or 3.5” Floppy drive hard disk math co-processor MS/PC-DOS 2.0 or higher CGA, MCGA, EGA, VGA and Hercules graphics adapters For more information, see the description of DECIMATE in “DECIMATE” on page 15. 15 FN2486.10 October 10, 2008 HSP43220 FIGURE 15. DECIMATE DESIGN MODULE SCREENS 16 FN2486.10 October 10, 2008 HSP43220 Absolute Maximum Ratings TA = +25°C Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V JA (°C/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics Component Count . . . . . . . . . . . . . . . . . . . . . . . 193,000 Transistors CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. DC Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V High Level Clock Input VIHC VCC = 5.25V 3.0 - V Low Level Clock Input VILC VCC = 4.75V - 0.8 V Output HIGH Voltage VOH IOH = -400µA, VCC = 4.75V 2.6 - V Output LOW Voltage VOL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current II VIN = VCC or GND, VCC = 5.25V -10 10 µA I/O Leakage Current IO VOUT = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.25V, (Note 3) - 500 µA Operating Power Supply Current ICCOP f = 15MHz, VIN = VCC or GND, VCC = 5.25V, (Notes 2, 4) - 120 mA Capacitance TA = +25°C, (Note 3) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance CIN - 12 pF Output Capacitance CO FREQ = 1MHz, VCC = Open, All measurements are referenced to device ground - 10 pF NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 8mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and CL = 40pF. 17 FN2486.10 October 10, 2008 HSP43220 AC Electrical Specifications VCC = +4.75V to +5.25V, TA = 0°C to +70°C (Note 7). Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. -15 PARAMETER SYMBOL NOTES -25 -33 MIN MAX MIN MAX MIN MAX UNITS 0 15 0 25.6 0 33 MHz Input Clock Frequency FCK FIR Clock Frequency FFIR 0 15 0 25.6 0 33 MHz Input Clock Period tCK 66 - 39 - 30 - ns FIR Clock Period tFIR 66 - 39 - 30 - ns Clock Pulse Width Low tSPWL 26 - 16 - 13 - ns Clock Pulse Width High tSPWH 26 - 16 - 13 - ns tSK 0 tFIR - 25 0 tFIR - 15 0 tFIR - 15 ns Clock Skew Between FIR_CK and CK_IN CK_IN Pulse Width Low tCH1L (Notes 5, 8) 29 - 19 - 19 - ns CK_IN Pulse Width High tCH1H (Notes 5, 8) 29 - 19 - 19 - ns CK_IN Setup to FIR_CK tCIS (Notes 5, 8) 27 - 17 - 17 - ns CK_IN Hold from FIR_CK tCIH (Notes 5, 8) 2 - 2 - 2 - ns RESET Pulse Width Low tRSPW 4tCK - 4tCK - 4tCK - ns Recovery Time on RESET tRTRS 8tCK - 8tCK - 8tCK - ns ASTARTIN Pulse Width Low tAST tCK + 10 - tCK + 10 - tCK + 10 - ns STARTOUT Delay from CK_IN tSTOD - 35 - 20 - 18 ns STARTIN Setup to CK_IN tSTIC 25 - 15 - 10 - ns Setup Time on DATA_IN tSET 20 - 15 - 14 - ns Hold Time on All inputs tHOLD 0 - 0 - 0 - ns Write Pulse Width Low tWL 26 - 15 - 12 - ns Write Pulse Width High tWH 26 - 20 - 18 - ns Setup Time on Address Bus Before the Rising Edge of Write tSTADD 26 - 20 - 20 - ns Setup Time On-chip Select Before the Rising Edge of Write tSTCS 26 - 20 - 20 - ns Setup Time on Control Bus Before the Rising Edge of Write tSTCB 26 - 20 - 20 - ns DATA_RDY Pulse Width Low tDRPWL 2tFIR - 20 - 2tFIR - 10 - 2tFIR - 10 - ns DATA_OUT Delay Relative to FIR_CK tFIRDV - 50 - 35 - 28 ns DATA RDY Valid Delay Relative to FIR_CK tFIRDR - 35 - 25 - 20 ns DATA_OUT Delay Relative to OUT_SELH tOUT - 25 - 20 - 20 ns Output Enable to Data Out Valid tOEV (Note 6) - 15 - 15 - 15 ns Output Disable to Data Out Three-State tOEZ (Note 5) - 15 - 15 - 15 ns Output Rise, Output Fall Times tr, tf from 0.8V to 2V, (Note 5) - 8 - 8 - 6 ns NOTES: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 6. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with and CL = 40pF. 7. AC Testing is performed as follows: Input levels (CLK Input) 4.0V and 0V, Input levels (all other Inputs) 0V and 3.0V, Timing reference levels (CLK) = 2.0V, (Others) = 1.5V, Output load per test load circuit and CL = 40pF. 8. Applies only when H_BYP = 1 or H_DRATE = 0. 18 FN2486.10 October 10, 2008 HSP43220 AC Test Load Circuit DUT S1 CL (NOTE) IOH SWITCH S1 OPEN FOR ICCSB AND ICCOP 1.5V IOL EQUIVALENT CIRCUIT NOTE: Test head capacitance. Timing Waveforms tFIR FIR_CK tSET CLK_IN tSPWH tHOLD tSPWL tCHIH tSK tCHIL DATA_IN CLK_IN tCK FIGURE 16A. FIGURE 16B. FIGURE 16. INPUT TIMING tAST ASTARTIN RESET tRSPW tRTRS CK_IN WR tSTOD STARTOUT tWL tWH tHOLD AO-1 tSET CK_IN tSTIC STARTIN C_BUS tHOLD CS tSTADD tHOLD tSTCB tHOLD tSTCS DATA_IN FIGURE 17A. FIGURE 17B. FIGURE 17. START TIMING 19 FN2486.10 October 10, 2008 HSP43220 Timing Waveforms (Continued) FIR_CK DATA_RDY tFIRDR tFIRDR DATA_OUT 16-23 tDRPWL DATA_OUT UPPER 8 BITS tFIRDV OUT_SELH PREVIOUS OUTPUT LOWER 8 BITS tOUT CURRENT OUTPUT FIGURE 18A. FIGURE 18B. OUT_ENP OUT_ENX tOEV 2.0V DATA_OUT 0-d23 tr 0.8V DATA_OUT tOEZ 1.7V 1.3V tf VALID FIGURE 18D. FIGURE 18C. FIGURE 18. 20 FN2486.10 October 10, 2008 HSP43220 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N84.1.15 (JEDEC MS-018AF ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 E1 E C L D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N 84 84 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN2486.10 October 10, 2008