HSP45240/883 TM December 1999 Features DUCT UCT E PRO UTE PROD IL T E L OBSO TERS BSTIT LE SU ns 1-888-IN m B I S S PO catio sil.co FOR A ntral Appli pp@inter ta e n call C email: ce or • FFT Processing Address Sequencer • Matrix Math Operations • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Ordering Information • Block Oriented 24-Bit Sequencer • Configurable as Two Independent 12-Bit Sequencers • 24 x 24 Crosspoint Switch • Programmable Delay on 12 Outputs 9- PART NUMBER TEMP. RANGE ( oC) HSP45240GM-25/883 -55 to 125 68 Ld PGA HSP45240GM-33/883 -55 to 125 68 Ld PGA HSP45240GM-40/883 -55 to 125 68 Ld PGA PKG. NO. PACKAGE • Multi-Chip Synchronization Signals • Standard µP Interface Description • 100pF Drive on Outputs The Intersil HSP45240/883 is a high speed Address Sequencer which provides specialized addressing for functions like FFTs, 1-D and 2-D filtering, matrix operations, and image manipulation. The sequencer supports block oriented addressing of large data sets up to 24 bits at clock speeds up to 40MHz. • DC to 40MHz Clock Rate Applications • 1-D, 2-D Filtering • Pan/Zoom Addressing Block Diagram STARTOUT ADDVAL DONE BLOCKDONE 12 REG STARTIN START CIRCUITRY SEQUENCE GENERATOR 24 CROSS-POINT SWITCH OUT12-23 OEH 12 DELAY 1-8 OUT0-11 DLYBLK OEL BUSY PROCESSOR INTERFACE D0-6, CS, A0, WR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 16 FN2816.4 HSP45240/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output Voltage Applied. . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA ( oC/W) θJC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 37.1 10.1 Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.35W Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8,388 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUPS TEMPERATURE ( oC) MIN MAX UNITS LIMITS Logical One Input Voltage VlH VDD = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VDD = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output HlGH Voltage V OH IOH = -400µA VDD = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage VOL IOL = +2.0mA 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V VCC = 4.5V (Note 2) Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Output Leakage Current IO VOUT = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Clock lnput High VIHC VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 3.0 - V Clock Input Low VILC VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.5V, Outputs Open 1, 2, 3 -55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Current ICCOP f = 33MHz VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤ TA ≤ 125 - 99 mA 7, 8 -55 ≤ TA ≤ 125 - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 3mA/MHz. 4. Tested as follows: t = 1MHz, VIH = 2.6, VIL = 0.4, VOH ≥ 1.5V, VOL < 1.5V, VIHC = 3.4V, and VILC = 0.4V. 17 HSP45240/883 TABLE 2. AC ELECTRICAL SPECIFICATIONS Device Guaranteed and 100% Tested -25 (25MHz) -33 (33MHz) -40 (40MHz) MIN MAX MIN MAX MIN MAX UNITS -55 ≤ TA ≤ 125 39 - 30 - 25 - ns 9, 10, 11 -55 ≤ TA ≤ 125 15 - 12 - 10 - ns tCL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 12 - 10 - ns Setup Time D0-6 to WR High tDS 9, 10, 11 -55 ≤ TA ≤ 125 17 - 16 - 14 - ns Hold Time D0-6 from WR Low tDH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - 0 - ns Setup Time A, CS to WR Low tAS 9, 10, 11 -55 ≤ TA ≤ 125 5 - 5 - 5 - ns Hold Time A, CS from WR High tAH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - 0 - ns Pulse Width for WR Low tWRL 9, 10, 11 -55 ≤ TA ≤ 125 18 - 14 - 12 - ns Pulse Width for WR High tWRH 9, 10, 11 -55 ≤ TA ≤ 125 18 - 14 - 12 - ns tWP 9,10,11 -55 ≤ TA ≤ 125 39 - 30 - 25 - ns Set-up Time STARTIN, DLYBLK, to Clock High tIS 9, 10, 11 -55 ≤ TA ≤ 125 15 - 12 - 10 - ns Hold Time STARTlN, DLYBLK, to Clock High tlH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - 0 - ns Clock to Output Prop. Delay on OUT0-23 tPDO 9, 10, 11 -55 ≤ TA ≤ 125 - 18 - 16 - 14 ns Clock to Prop. Delay, on STARTOUT, BLKDONE, DONE, ADVAL, and BUSY tPDS 9, 10, 11 -55 ≤ TA ≤ 125 - 18 - 16 - 14 ns tEN 9, 10, 11 -55 ≤ TA ≤ 125 - 22 - 20 - 15 ns tRST 9, 10, 11 -55 ≤ TA ≤ 125 SYMBOL GROUP A SUBGROUP TEMPERATURE (oC) Clock Period tCP 9, 10, 11 Clock Pulse Width High tCH Clock Pulse Width Low PARAMETER WR Cycle Time Output Enable Time (Note 6) RST Low Time 2 Clock Cycles ns NOTES: 5. AC Testing: VCC = 4.5V and 5.5V, inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are made at 1.5V for both a logic “1” and “‘0”. CLK is driven at 4.0V and 0V and measured at 2.0V. 6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF. TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETERS SYMBOL TEST CONDITIONS -25 (25MHz) -33 (33MHz) -40 (40MHz) NOTES TEMPERATURE MIN MAX MIN MAX MIN MAX UNITS Input Capacitance C IN VCC = Open, f = 1MHz, All measurements are referenced to device GND. 7 TA = 25 - 10 - 10 - 10 pF Output Capacitance COUT VCC = Open, f = 1MHz, All measurements are referenced to device GND. 7 TA = 25 - 10 - 10 - 10 pF Output Disable tOEZ 7, 8 -55 ≤ TA ≤ 125 - 22 - 20 - 15 ns 18 HSP45240/883 TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) PARAMETERS SYMBOL TEST CONDITIONS -25 (25MHz) -33 (33MHz) -40 (40MHz) NOTES TEMPERATURE MIN MAX MIN MAX MIN MAX UNITS Output Rise Time tOR 7, 8 -55 ≤ TA ≤ 125 - 5 - 5 - 3 ns Output Fall Time tOF 7, 8 -55 ≤ TA ≤ 125 - 5 - 5 - 3 ns NOTES: 7. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 8. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 Group A - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C and D Samples/5005 1, 7, 9 19 HSP45240/883 Burn-In Circuit L OEH DLY BLK START VCC OUT OEL START ADD VAL BUSY IN BLOCK GND DONE OUT1 NC VCC NC OUT3 K NC NC J RST VCC GND OUT4 H CLK GND OUT5 VCC G CS A0 F WR GND GND OUT8 E D6 D5 OUT9 VCC D D4 D3 OUT10 OUT11 C D2 D1 GND OUT12 B D0 NC A 1 DONE OUTO OUT2 OUT6 OUT7 OUT22 OUT21 GND OUT18 OUT17 GND GND OUT23 VCC 2 3 4 OUT20 OUT19 5 6 VCC OUT14 NC NC OUT16 OUT15 OUT13 7 8 9 10 11 BURNIN SIGNAL PGA PIN PIN NAME BURNIN SIGNAL PGA PIN PIN NAME BURNIN SIGNAL PGA PIN PIN NAME BURNIN SIGNAL PGA PIN A2 GND GND B9 OUT14 VCC/2 F11 OUT8 VCC/2 K6 BUSYB VCC/2 A3 OUT23 VCC/2 C1 D2 F10 G1 CSB F5 K7 DONEB VCC/2 A4 V CC VCC C2 D1 F9 G2 A0 F6 K8 OUT0 VCC/2 A5 OUT20 VCC/2 C10 GND GND G10 OUT6 VCC/2 K9 VCC A6 OUT19 VCC/2 C11 OUT12 VCC/2 G11 OUT7 VCC/2 K11 OUT3 VCC/2 A7 V CC VCC D1 D4 F12 H1 CLK F0 L2 OEHB F13 A8 OUT16 VCC/2 D2 D3 F11 H2 GND GND L3 DLYBLK F11 PIN NAME VCC A9 OUT15 VCC/2 D10 OUT10 VCC/2 H10 OUTS VCC/2 L4 STARTOUTB A10 OUT13 VCC/2 D11 OUT11 VCC/2 H11 VCC VCC LS VCC VCC/2 B1 D0 F8 E1 D6 F7 J1 RSTB F14 L6 BLOCKDONEB B3 OUT22 VCC/2 E2 D5 F13 J2 VCC VCC L7 GND GND VCC VCC/2 B4 OUT21 VCC/2 E10 OUT9 VCC/2 J10 GND GND L8 OUT1 VCC/2 B5 GND GND E11 VCC VCC J1 1 OUT4 VCC/2 L9 OUT2 VCC/2 B6 OUT18 VCC/2 F1 WRB F4 K3 OELB F12 B7 OUT17 VCC/2 F2 GND GND K4 START1NB F6 B8 GND GND F10 GND GND K5 ADVALB VCC/2 NOTES: 9. VCC /2 (2.7V ± ±10%) used for outputs only. 10. 47Ω (±20%) resistor connected to all pins except VCC and GND. 11. V CC = 5.5 ±0.5V. 12. 0.1µF (min) capacitor between VCC and GND per position. 13. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2....., F11 = F10/2, 40% -60% Duty Cycle. 14. Input voltage limits: VIL = 0.8V max., VIH = 4.5V ±10%. 20 HSP45240/883 Die Characteristics DIE DIMENSIONS: GLASSIVATION: 186 mils x 222 mils x 19 ±1mils Type: Nitrox Thickness: 10kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: Si - Al or Si-Al-Cu Thickness: 8kÅ 1.8 x 105A/cm 2 Metallization Mask Layout OUT13 OUT14 OUT15 GND OUT16 OUT17 VCC OUT18 OUT19 GND OUT20 OUT21 VCC OUT22 OUT23 GND HSP45240/883 OUT12 D0 GND D1 OUT11 D2 OUT10 D3 VCC D4 OUT9 D5 OUT8 D6 GND GND OUT7 WR OUT6 A0 VCC CS OUT5 GND OUT4 CLK OUT2 OUT1 VCC OUT0 GND DONE BLOCKDONE BUSY VCC ADDVAL STARTOUT STARTIN OUT3 DLYBLK RST OEL GND OEH VCC All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 21