HD-6408 Data Sheet October 1, 2015 CMOS Asynchronous Serial Manchester Adapter (ASMA) The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus. The Encoder converts serial NRZ data (typically from a shift register) to Manchester II encoded data, adding a sync pulse and parity bit. The Decoder recognizes this sync pulse and identifies it as a Command Sync or a Data Sync. The data is then decoded and shifted out in NRZ code (typically into a shift register). Finally, the parity bit is checked. If there were no Manchester or parity errors the Decoder responds with a valid word signal. The Decoder puts the Manchester code to full use to provide clock recovery and excellent noise immunity at these very high speeds. The HD-6408 can be used in many commercial applications such as security systems, environmental control systems, serial data links and many others. It utilizes a single 12 x clock and achieves data rates of up to one million bits per second with a very minimum overhead of only 4 bits out of 20, leaving 16 bits for data. FN2952.3 Features • Low Bit Error Rate • Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MBit/s • Sync Identification and Lock-In • Clock Recovery • Manchester II Encoder, Decoder • Separate Encode and Decode • Low Operating Power. . . . . . . . . . . . . . . . . . . 50mW at 5V • Single Power Supply • 24 Ld Package • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER PART MARKING HD3-6408-9 HD3-6408-9 No longer available or supported, recommended replacement HD3-6408-9Z Pinout HD-6408 (DIP) TOP VIEW TEMP. RANGE (°C) PACKAGE -40 to +85 24 Ld PDIP PKG. NO. E24.6 VW 1 24 VCC ESC 2 23 EC 22 SCI HD3-6408-9Z (Note) HD3-6408-9Z -40 to +85 24 Ld PDIP* (Pb-Free) E24.6 TD 3 SDO 4 21 SD HD1-6408-9 HD1-6408-9 F24.6 DC 5 20 SS BZI 6 19 EE BOI 7 18 SDI UDI 8 17 BOO NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. DSC 9 16 OI CDS 10 15 BZO DR 11 14 DBS 13 MR GND 12 -40 to +85 24 Ld CERDIP *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. d 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas LLC 2006, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HD-6408 Block Diagrams ENCODER EC 23 DECODER 6 14 13 SCI ESC SD SS 22 11 2 MR 1 BIT COUNTER 2 TD 21 RESET 20 18 CDS COUNT DECODER SYNC CHARACTER FORMER DATA 19 EE 15 16 17 BIT COUNTER DBS VW PARITY SDI DR DC BZO OI BOO 3 10 5 9 DSC VALID WORD LATCH VALID WORD TEST CIRCUIT PARITY CHECK CHARACTER IDENTIFIER NRZ OUTPUT PORT SYNC LATCH CLOCK SYNCHRONIZER 4 SDO 6 BZI BOI 7 8 TRANSITION FINDER UDI 2 FN2952.3 October 1, 2015 HD-6408 Pin Description PIN TYPE SYMBOL SECTION 1 O VW Decoder Output high indicates receipt of a VALID WORD. 2 O ESC Encoder ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of ESC. 3 O TD Decoder TAKE DATA output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. 4 O SDO Decoder SERIAL DATA OUT delivers received data in correct NRZ format. 5 I DC Decoder DECODER CLOCK input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the Decoder. Input a frequency equal to 12X the data rate. 6 I BZI Decoder A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative state. This pin must be held high when the Unipolar input is used. 7 I BOI Decoder A high input should be applied to BIPOLAR ONE IN when the bus is in its positive state, this pin must be held low when the Unipolar input is used. 8 I UDI Decoder With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition finder circuit. If not used this input must be held low. 9 O DSC Decoder DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ³ 12), synchronized by the recovered serial data stream. 10 O CDS Decoder COMMAND/DATA SYNC output high occurs during output of decoded data which was preceded by a Command synchronizing character. A low output indicates a Data synchronizing character. 11 I DR Decoder A high input to DECODER RESET during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. 12 I GND Both GROUND supply pin. 13 I MR Both A high on MASTER RESET clears the 2:1 counters in both the encoder and decoder and the ³ 6 counter. 14 O DBS Encoder DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER CLOCK. 15 O BZO Encoder BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative sense of a bipolar line driver. 16 I OI Encoder A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states. 17 O BOO Encoder BIPOLAR ONE OUT is an active low output designed to drive the one or positive sense of a bipolar line driver. 18 I SDI Encoder SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. 19 I EE Encoder A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preceding cycle being completed). 20 I SS Encoder SYNC SELECT actuates a Command sync for an input high and data sync for an input low. 21 O SD Encoder SEND DATA is an active high output which enables the external source of serial data. 22 I SCI Encoder SEND CLOCK IN is 2X the Encoder data rate. 23 I EC Encoder ENCODER CLOCK is the input to the 6:1 divider. 24 I VCC Both 3 DESCRIPTION VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24) to GND (pin 12) is recommended. FN2952.3 October 1, 2015 HD-6408 - (4). After the sync and Manchester II encoded data are transmitted through the BOO and BZO outputs, the Encoder adds on an additional bit which is the (odd) parity for that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (5) as shown to prevent a consecutive word from being encoded. At any time a low on OI will force both bipolar outputs to a high state but will not affect the Encoder in any other way. Encoder Operation The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SClock input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SClock by dividing the DClock. The Encoder’s cycle begins when EE is high during a falling edge of ESC (1). This cycle lasts for one word length or twenty ESC periods. At the next low-to-high transition of the ESC, a high at SS input actuates a Command sync or a low will produce a Data sync for that word (2). When the Encoder is ready to accept data, the SD output will go high and remain high for sixteen ESC periods (3) - (4). To Abort the Encoder transmission a positive pulse must be applied at MR. Any time after or during this pulse, a low-tohigh transition on SCI clears the internal counters and initializes the Encoder for a new word. During these sixteen periods the data should be clocked into the SD Input with every high-to-low transition of the ESC (3) 0 TIMING 1 2 3 4 5 6 7 15 16 17 18 19 SCI ESC EE SS DON’T CARE DON’T CARE VALID SD SDI 15 BOO 1ST HALF 2ND HALF BZO SYNC 1 2 SYNC 3 4 14 13 12 11 10 3 2 1 0 15 14 13 12 11 3 2 1 0 P 15 14 13 12 11 3 2 1 0 P 4 5 FN2952.3 October 1, 2015 HD-6408 The decoded data available at SDO is in a NRZ format. The DSC is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. Decoder Operation The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DClock input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BOI and BZI inputs will accept data from a differential output comparator. The UDI input can only accept noninverted Manchester II coded data (e.g. from BOO of an Encoder through an inverter to UDI). After all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. A high on VW output (4) indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown (1). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized (1), the type of sync is indicated by the CDS output. If the sync character was a command, this output will go high (2) and remain high for sixteen DSC periods (3), otherwise it will remain low. The TD output will go high and remain high (2) - (3) while the Decoder is transmitting the decoded data through SDO. TIMING 0 1 2 3 At any time in the above sequence a high input on DR during a low-to-high transition of DSC will abort transmission and initialize the Decoder to start looking for a new sync character. 4 5 6 7 8 16 17 18 19 14 13 12 11 10 2 1 0 P 14 13 12 11 10 2 1 0 P DSC BOI BZI 1ST HALF 2ND HALF 15 SYNC SYNC 15 TD CDS SDO UNDEFINED VW FROM PREVIOUS RECEPTION 15 1 2 5 14 13 12 4 3 2 1 0 3 4 FN2952.3 October 1, 2015 HD-6408 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Operating Conditions CERDIP Package. . . . . . . . . . . . . . . . . 50 11 PDIP Package* . . . . . . . . . . . . . . . . . . 60 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HD-6408-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications SYMBOL VCC = 5.0V ±10%, TA = -40°C to +85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIH Logical “1” Input Voltage 70% VCC - - V VIL Logical “0” Input Voltage - 20% VCC - V VIHC Logical “1” Input Voltage (Clock) VCC -0.5 - - V VILC Logical “0” Input Voltage (Clock) - GND +0.5 - V II Input Leakage VIN = VCC or GND, DIP Pins 5-8, 11, 13, 16, 18, 19, 20, 22, 23 -1.0 - +1.0 µA VOH Logical “1” Output Voltage IOH = -3mA 2.4 - - V VOL Logical “0” Output Voltage IOL = 1.8mA - - 0.4 V ICCSB Supply Current Standby VIN = VCC = 5.5V Outputs Open - 0.5 2 mA ICCOP Supply Current Operating (Note 1) VCC = 5.5V, f = 15MHz - 8.0 10.0 mA NOTE: 1. Guaranteed but not 100% tested. AC Electrical Specifications SYMBOL VCC = 5.0V ±10%, TA = -40°C to +85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ENCODER TIMING (1) FEC Encoder Clock Frequency CL = 50pF 0 - 12 MHz (2) FESC Send Clock Frequency CL = 50pF 0 - 2.0 MHz (3) TECR Encoder Clock Rise Time CL = 50pF - - 8 ns (4) TECF Encoder Clock Fall Time CL = 50pF - - 8 ns (5) FED Data Rate CL = 50pF 0 - 1.0 MHz (6) TMR Master Reset Pulse Width CL = 50pF 150 - - ns (7) TE1 Shift Clock Delay CL = 50pF - - 125 ns (8) TE2 Serial Data Setup CL = 50pF 75 - - ns (9) TE3 Serial Data Hold CL = 50pF 75 - - ns (10) TE4 Enable Setup CL = 50pF 90 - - ns (11) Enable Pulse Width CL = 50pF 100 - - ns (12) TE6 Sync Setup CL = 50pF 55 - - ns (13) TE7 Sync Pulse Width CL = 50pF 150 - - ns (14) TE8 Send Data Delay CL = 50pF 0 - 50 ns (15) TE9 Bipolar Output Delay CL = 50pF - - 130 ns TE5 6 FN2952.3 October 1, 2015 HD-6408 AC Electrical Specifications SYMBOL VCC = 5.0V ±10%, TA = -40°C to +85°C (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS (16) TE10 Enable Hold CL = 50pF 10 - - ns (17) TE11 Sync Hold CL = 50pF 95 - - ns DECODER TIMING (18) FDC Decoder Clock Frequency CL = 50pF 0 - 12 MHz (19) TDCR Decoder Clock Rise Time CL = 50pF - - 8 ns (20) TDCF Decoder Clock Fall Time CL = 50pF - - 8 ns (21) FDD Data Rate CL = 50pF 0 - 1.0 MHz (22) TDR Decoder Reset Pulse Width CL = 50pF 150 - - ns (23) TDRS Decoder Reset Setup Time CL = 50pF 75 - - ns (24) TDRH Decoder Reset Hold Time CL = 50pF 10 - - ns (25) TMR Master Reset Pulse Width CL = 50pF 150 - - ns (26) TD1 Bipolar Data Pulse Width Note 2, CL = 50pF TDC +10 - - ns (27) TD2 Sync Transition Span Note 2, CL = 50pF - 18TDC - ns (28) TD3 One Zero Overlap Note 2, CL = 50pF - - TDC -10 ns (29) TD4 Short Data Transition Span Note 2, CL = 50pF - 6TDC - ns (30) TD5 Long Data Transition Span Note 2, CL = 50pF - 12TDC - ns (31) TD6 Sync Delay (ON) CL = 50pF -20 - 110 ns (32) TD7 Take Data Delay (ON) CL = 50pF 0 - 110 ns (33) TD8 Serial Data Out Delay CL = 50pF - - 80 ns (34) TD9 Sync Delay (OFF) CL = 50pF 0 - 110 ns (35) TD10 Take Data Delay (OFF) CL = 50pF 0 - 110 ns (36) TD11 Valid Word Delay CL = 50pF 0 - 110 ns NOTE: 2. TDC = Decoder Clock Period = 1/FDC. (These parameters are guaranteed but not 100% tested). Capacitance SYMBOL TA = +25°C PARAMETER CIN Input Capacitance CO Output Capacitance 7 TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND MIN TYP MAX UNITS - 15 - pF - 15 - pF FN2952.3 October 1, 2015 HD-6408 AC Testing Input, Output Waveform INPUT VOH VIH 50% 50% VIL NOTE: VOL AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt. Encoder Timing (7) SCI TE1 ESC TE3 (9) SDI VALID VALID TE2 (8) SC (7) TE1 TE10 (16) (10) TE4 ESC (17) TE11 EE (11) TE5 (12) TE6 SS VALID TE7 (13) ESC (14) TE8 SD SC (15) TE9 BOO OR BZO 8 FN2952.3 October 1, 2015 HD-6408 Decoder Timing NOTE: UI = 0, FOR NEXT DIAGRAMS BIT PERIOD BOI TD1 (26) BIT PERIOD TD2 (27) BZI BIT PERIOD TD3 (28) TD3 (28) TD1 (26) TD2 (27) COMMAND SYNC TD1 (26) TD3 (28) BOI TD2 (27) BZI TD1 (26) (28) TD3 DATA SYNC TD2 (27) BOI BZI TD1 (26) TD1 (26) TD3 TD3 (28) TD3 (28) TD3 (28) (28) TD4 (29) TD5 (30) ONE TD1 (26) TD5 (30) ZERO ONE TD3 (28) TD4 (29) NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS (27) TD2 COMMAND SYNC (27) TD2 UI DATA SYNC UI (27) TD2 UI TD4 (29) (27) TD2 (30) TD5 ONE 9 TD5 ZERO (30) ONE (29) (29) TD4 TD4 ONE FN2952.3 October 1, 2015 HD-6408 Decoder Timing DSC (Continued) (31) TD6 CDS TD DSC TD7 (32) (33) TD8 DATA BIT SDO DSC (34) TD9 CDS (35) TD10 TD (36) TD11 VW DSC (23) TDRS (22) TDR DR (24) TDRH 10 FN2952.3 October 1, 2015 HD-6408 Decoder Timing DSC (Continued) (31) TD6 CDS TD7 TD (32) DSC (33) TD8 SDO DATA BIT DSC (34) TD8 CDS (35) TD10 TD (36) TD11 VW DSC (23) TCRS (22) TDR DR (24) TDRH 11 FN2952.3 October 1, 2015 HD-6408 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 1, 2015 FN2952.3 CHANGE Added Rev History beginning with Rev 3. Added About Intersil Verbiage. Updated Ordering Information on page 1 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN2952.3 October 1, 2015